SYSRST_CTRL Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke sysrst_ctrl_smoke 6.420s 2.111ms 50 50 100.00
V1 input_output_inverted sysrst_ctrl_in_out_inverted 7.810s 2.463ms 50 50 100.00
V1 combo_detect_ec_rst sysrst_ctrl_combo_detect_ec_rst 6.460s 2.410ms 5 5 100.00
V1 combo_detect_ec_rst_with_pre_cond sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 6.420s 2.366ms 5 5 100.00
V1 csr_hw_reset sysrst_ctrl_csr_hw_reset 8.810s 6.036ms 5 5 100.00
V1 csr_rw sysrst_ctrl_csr_rw 6.160s 2.042ms 20 20 100.00
V1 csr_bit_bash sysrst_ctrl_csr_bit_bash 2.792m 67.735ms 5 5 100.00
V1 csr_aliasing sysrst_ctrl_csr_aliasing 11.440s 2.925ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset sysrst_ctrl_csr_mem_rw_with_rand_reset 6.700s 2.147ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr sysrst_ctrl_csr_rw 6.160s 2.042ms 20 20 100.00
sysrst_ctrl_csr_aliasing 11.440s 2.925ms 5 5 100.00
V1 TOTAL 165 165 100.00
V2 combo_detect sysrst_ctrl_combo_detect 8.728m 205.983ms 50 50 100.00
V2 combo_detect_with_pre_cond sysrst_ctrl_combo_detect_with_pre_cond 8.936m 213.621ms 92 100 92.00
V2 auto_block_key_outputs sysrst_ctrl_auto_blk_key_output 5.694m 185.963ms 49 50 98.00
V2 keyboard_input_triggered_interrupt sysrst_ctrl_edge_detect 11.380m 536.463ms 50 50 100.00
V2 pin_output_keyboard_inversion_control sysrst_ctrl_pin_override_test 7.850s 2.510ms 50 50 100.00
V2 pin_input_value_accessibility sysrst_ctrl_pin_access_test 6.990s 2.260ms 50 50 100.00
V2 ec_power_on_reset sysrst_ctrl_ec_pwr_on_rst 33.871m 1.319s 49 50 98.00
V2 flash_write_protect_output sysrst_ctrl_flash_wr_prot_out 8.000s 2.611ms 50 50 100.00
V2 ultra_low_power_test sysrst_ctrl_ultra_low_pwr 5.848m 2.677s 43 50 86.00
V2 sysrst_ctrl_feature_disable sysrst_ctrl_feature_disable 23.430s 35.404ms 2 2 100.00
V2 stress_all sysrst_ctrl_stress_all 9.139m 446.041ms 49 50 98.00
V2 alert_test sysrst_ctrl_alert_test 5.930s 2.013ms 50 50 100.00
V2 intr_test sysrst_ctrl_intr_test 6.060s 2.011ms 50 50 100.00
V2 tl_d_oob_addr_access sysrst_ctrl_tl_errors 7.370s 2.091ms 20 20 100.00
V2 tl_d_illegal_access sysrst_ctrl_tl_errors 7.370s 2.091ms 20 20 100.00
V2 tl_d_outstanding_access sysrst_ctrl_csr_hw_reset 8.810s 6.036ms 5 5 100.00
sysrst_ctrl_csr_rw 6.160s 2.042ms 20 20 100.00
sysrst_ctrl_csr_aliasing 11.440s 2.925ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 32.190s 8.070ms 20 20 100.00
V2 tl_d_partial_access sysrst_ctrl_csr_hw_reset 8.810s 6.036ms 5 5 100.00
sysrst_ctrl_csr_rw 6.160s 2.042ms 20 20 100.00
sysrst_ctrl_csr_aliasing 11.440s 2.925ms 5 5 100.00
sysrst_ctrl_same_csr_outstanding 32.190s 8.070ms 20 20 100.00
V2 TOTAL 674 692 97.40
V2S tl_intg_err sysrst_ctrl_sec_cm 1.854m 42.011ms 5 5 100.00
sysrst_ctrl_tl_intg_err 1.736m 42.452ms 20 20 100.00
V2S sec_cm_bus_integrity sysrst_ctrl_tl_intg_err 1.736m 42.452ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset sysrst_ctrl_stress_all_with_rand_reset 10.877m 2.509s 40 50 80.00
V3 TOTAL 40 50 80.00
TOTAL 904 932 97.00

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 15 15 10 66.67
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
96.62 98.75 96.76 100.00 95.51 98.23 99.33 87.78

Failure Buckets

Past Results