SYSRST_CTRL Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: `6a84251492`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	6.420s	2.111ms	50	50	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	7.810s	2.463ms	50	50	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	6.460s	2.410ms	5	5	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	6.420s	2.366ms	5	5	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	8.810s	6.036ms	5	5	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	6.160s	2.042ms	20	20	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	2.792m	67.735ms	5	5	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	11.440s	2.925ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	6.700s	2.147ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	6.160s	2.042ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.440s	2.925ms	5	5	100.00
V1		TOTAL			165	165	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	8.728m	205.983ms	50	50	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	8.936m	213.621ms	92	100	92.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	5.694m	185.963ms	49	50	98.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	11.380m	536.463ms	50	50	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	7.850s	2.510ms	50	50	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	6.990s	2.260ms	50	50	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	33.871m	1.319s	49	50	98.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	8.000s	2.611ms	50	50	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	5.848m	2.677s	43	50	86.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	23.430s	35.404ms	2	2	100.00
V2	stress_all	sysrst_ctrl_stress_all	9.139m	446.041ms	49	50	98.00
V2	alert_test	sysrst_ctrl_alert_test	5.930s	2.013ms	50	50	100.00
V2	intr_test	sysrst_ctrl_intr_test	6.060s	2.011ms	50	50	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	7.370s	2.091ms	20	20	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	7.370s	2.091ms	20	20	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	8.810s	6.036ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.160s	2.042ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.440s	2.925ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	32.190s	8.070ms	20	20	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	8.810s	6.036ms	5	5	100.00
		sysrst_ctrl_csr_rw	6.160s	2.042ms	20	20	100.00
		sysrst_ctrl_csr_aliasing	11.440s	2.925ms	5	5	100.00
		sysrst_ctrl_same_csr_outstanding	32.190s	8.070ms	20	20	100.00
V2		TOTAL			674	692	97.40
V2S	tl_intg_err	sysrst_ctrl_sec_cm	1.854m	42.011ms	5	5	100.00
		sysrst_ctrl_tl_intg_err	1.736m	42.452ms	20	20	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	1.736m	42.452ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	10.877m	2.509s	40	50	80.00
V3		TOTAL			40	50	80.00
		TOTAL			904	932	97.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	15	15	10	66.67
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.62	98.75	96.76	100.00	95.51	98.23	99.33	87.78

Failure Buckets

UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 8 failures:

Test sysrst_ctrl_ultra_low_pwr has 7 failures.

6.sysrst_ctrl_ultra_low_pwr.48759051158425768564125512701295324845092402404884459243120066311380634002356
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 2331235518 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 498123735518 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 498123735518 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.sysrst_ctrl_ultra_low_pwr.102214876103479244346453093177112293071969747660085331382342519312683662470704
Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest/run.log

  UVM_ERROR @ 6100383754 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_ERROR @ 6212883754 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:215) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed cfg.vif.z3_wakeup == 0 (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 6212883754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

26.sysrst_ctrl_stress_all_with_rand_reset.113939138007523025496972794048365120017647585841075024054481153107216102410930
Line 561, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4305679084 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)    
  UVM_INFO @ 4618179084 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
  UVM_INFO @ 757773179084 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
  UVM_INFO @ 757786330857 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_common_vseq
  UVM_INFO @ 759783210857 ps: (cip_base_vseq.sv:439) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] Running intr test iteration 1/3

UVM_FATAL (sysrst_ctrl_base_vseq.sv:67) [sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == * has 4 failures:
- Test sysrst_ctrl_stress_all_with_rand_reset has 3 failures.
  - 25.sysrst_ctrl_stress_all_with_rand_reset.52160588654387002121656598802155951453094554920580445810507276972064079801856
    Line 582, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 11306928824 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 11306928824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 33.sysrst_ctrl_stress_all_with_rand_reset.110259054522520225067548246707069547589709928714030795126190662034633933305376
    Line 622, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 86720635186 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 86720635186 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
- Test sysrst_ctrl_ec_pwr_on_rst has 1 failures.
  - 46.sysrst_ctrl_ec_pwr_on_rst.22668200558462056283686640082190925312304964932319468174992801633731915294021
    Line 558, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ec_pwr_on_rst/latest/run.log
```
  UVM_FATAL @ 2430730809 ps: (sysrst_ctrl_base_vseq.sv:67) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ec_pwr_on_rst_vseq] time out waiting for ec_rst == 0
  UVM_INFO @ 2430730809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 4 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 4 failures.

66.sysrst_ctrl_combo_detect_with_pre_cond.90613188956970565097525793195836008637611203681836459946159332519697285186512
Line 591, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 41264335015 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 41264335015 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 41264335015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

75.sysrst_ctrl_combo_detect_with_pre_cond.11706721222172840799926504768467983890533861028040858939043371716724057087544
Line 589, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 38591763794 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 38771763794 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
  UVM_INFO @ 38791763794 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
  UVM_INFO @ 48898685566 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x28
  UVM_INFO @ 48898706400 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x2d

... and 2 more failures.

UVM_ERROR (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == * (* [*] vs * [*]) has 2 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 2 failures.

4.sysrst_ctrl_stress_all_with_rand_reset.19979438485654381502831238087729908178901376718563823560263660308630135985557
Line 642, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 30622988949 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 30626919529 ps: (cip_base_vseq.sv:760) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 8/10
  UVM_INFO @ 30627877264 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 30628837264 ps: (cip_base_vseq.sv:715) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 9/10

21.sysrst_ctrl_stress_all_with_rand_reset.9043361480802408045491748743254636144958189403269175211512891935065496963106
Line 618, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16918777824 ps: (sysrst_ctrl_flash_wr_prot_vseq.sv:55) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_flash_wr_prot_vseq] Check failed cfg.vif.flash_wp_l == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 16931434202 ps: (cip_base_vseq.sv:760) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 7/10
  UVM_INFO @ 16932094385 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 16934514385 ps: (cip_base_vseq.sv:715) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 8/10

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

6.sysrst_ctrl_stress_all_with_rand_reset.108875588758182258180086904929385762919854271539633722393568016737986452379862
Line 653, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 30303731659 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 30303731659 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 30303731659 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

12.sysrst_ctrl_combo_detect_with_pre_cond.85787574875794635933247760875953830910902327192309273446921881797695077640568
Line 566, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 16515145790 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 16515145790 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 16515145790 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:109) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

20.sysrst_ctrl_stress_all_with_rand_reset.10352571502385899289819807644250467016105732542859986053033166589791618347720
Line 673, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 48009326512 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
  UVM_ERROR @ 48009326512 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:115) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key2_in == inv_key2_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 48009326512 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: * has 1 failures:
- Test sysrst_ctrl_stress_all has 1 failures.
  - 31.sysrst_ctrl_stress_all.65511527791388340161214860319076488950102679831133852191091165822639767640118
    Line 614, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest/run.log
```
  UVM_ERROR @ 168351513668 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sysrst_ctrl_reg_block.combo_intr_status reset value: 0x0
  UVM_INFO @ 168657095799 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (sysrst_ctrl_combo_detect_vseq.sv:300) [sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

32.sysrst_ctrl_stress_all_with_rand_reset.48296793865739401722991088147459574184033591179962497714978183189102183053314
Line 695, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 85935139804 ps: (sysrst_ctrl_combo_detect_vseq.sv:300) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 85947550002 ps: (cip_base_vseq.sv:760) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq]
  Stress w/ reset is done for run 8/10
  UVM_INFO @ 85949187673 ps: (dv_base_reg.sv:325) [sysrst_ctrl_reg_block.regwen] lock_lockable_flds          1 val
  UVM_INFO @ 85951778608 ps: (cip_base_vseq.sv:715) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_common_vseq] running run_seq_with_rand_reset_vseq iteration 9/10

UVM_ERROR (sysrst_ctrl_edge_detect_vseq.sv:124) [sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (* [*] vs * [*]) Compare mismatch at FlashWpIdx has 1 failures:

Test sysrst_ctrl_stress_all_with_rand_reset has 1 failures.

41.sysrst_ctrl_stress_all_with_rand_reset.42144788880834761264928492618796918002644845382145889122398593872675002909071
Line 656, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 49398446920 ps: (sysrst_ctrl_edge_detect_vseq.sv:124) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[index] == edge_detect_h2l.h2l_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at FlashWpIdx
  UVM_ERROR @ 49398446920 ps: (sysrst_ctrl_edge_detect_vseq.sv:132) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_edge_detect_vseq] Check failed key_intr_status[NumInputs+index] == edge_detect_l2h.l2h_triggered (0 [0x0] vs 1 [0x1]) Compare mismatch at AcPresentIdx
  UVM_INFO @ 49398446920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (* [*] vs * [*]) has 1 failures:

Test sysrst_ctrl_auto_blk_key_output has 1 failures.

43.sysrst_ctrl_auto_blk_key_output.63734376665970898031034624409697226717828627694450382418544398380826636607670
Line 560, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_auto_blk_key_output/latest/run.log

  UVM_ERROR @ 2153521371 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Check failed override_key1_out_value == cfg.vif.key1_out (1 [0x1] vs 0 [0x0])
  UVM_INFO @ 2268608154 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 5f
  UVM_INFO @ 2893521371 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:100
  UVM_INFO @ 2993568154 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:88) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Debounce timer set for: 42
  UVM_INFO @ 3383521371 ps: (sysrst_ctrl_auto_blk_key_output_vseq.sv:100) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_auto_blk_key_output_vseq] Value of cycles:68

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

57.sysrst_ctrl_combo_detect_with_pre_cond.33493061254411009131170686806324897833536597444666620610961975437872140383929
Line 614, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 52820473752 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(7) vs exp(2) +/-4
  UVM_INFO @ 63106626110 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x2a
  UVM_INFO @ 63107126114 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x19
  UVM_INFO @ 64202051540 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3
  UVM_INFO @ 64215473752 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= f

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == *) Unexpected H2L transition of ec_rst_l_o has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

71.sysrst_ctrl_combo_detect_with_pre_cond.87445273786366433079876225635315308922097368835910447015450706764983540969567
Line 615, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/71.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 76019823050 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:119) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (ec_rst_h2l_expected == 1) Unexpected H2L transition of ec_rst_l_o
  UVM_INFO @ 76059823050 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :0
  UVM_INFO @ 76059823050 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :1
  UVM_INFO @ 76059823050 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :3
  UVM_INFO @ 76229823050 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1

UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-* has 1 failures:

Test sysrst_ctrl_combo_detect_with_pre_cond has 1 failures.

82.sysrst_ctrl_combo_detect_with_pre_cond.89250739917950425440799056721132193594809202850936823531140622479736970005235
Line 615, in log /container/opentitan-public/scratch/os_regression/sysrst_ctrl-sim-vcs/82.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log

  UVM_ERROR @ 76425436445 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:252) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) bat_disable_check: inact(6) vs exp(2) +/-4
  UVM_ERROR @ 76425436445 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE :                                       exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(6) vs exp(2) +/-4
  UVM_INFO @ 76425436445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---