Unified Coverage Report :: Group Instance : sysrst_ctrl_combo_intr_status_cg

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1319

1

T2

7

T4

7

T14

1

auto[1]

1730

1

T2

12

T4

20

T14

10

---

Summary for Variable cp_combo0_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo0_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2564

1

T2

19

T4

18

T14

11

auto[1]

485

1

T4

9

T8

1

T11

3

---

Summary for Variable cp_combo1_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo1_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2893

1

T2

19

T4

27

T14

11

auto[1]

156

1

T37

2

T38

4

T39

4

---

Summary for Variable cp_combo2_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo2_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2874

1

T2

19

T4

22

T14

11

auto[1]

175

1

T4

5

T8

1

T11

4

---

Summary for Variable cp_combo3_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_combo3_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2884

1

T2

16

T4

27

T14

11

auto[1]

165

1

T2

3

T11

2

T36

7

---

Summary for Variable cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_interrupt

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1867

1

T2

19

T4

6

T14

11

auto[1]

1182

1

T4

21

T8

19

T11

19

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1248

1

T2

6

T4

13

T8

11

auto[1]

1801

1

T2

13

T4

14

T14

11

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1292

1

T2

5

T4

10

T14

11

auto[1]

1757

1

T2

14

T4

17

T8

9

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1325

1

T2

13

T4

8

T14

11

auto[1]

1724

1

T2

6

T4

19

T8

9

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1290

1

T2

9

T4

14

T14

10

auto[1]

1759

1

T2

10

T4

13

T14

1

---

Summary for Cross cross_combo0

Samples crossed: cp_combo0_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	0	96	100.00
Automatically Generated Cross Bins	96	0	96	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo0

Bins

cp_combo0_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

53

1

T51

1

T81

1

T39

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

14

1

T60

1

T120

1

T100

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T2

1

T51

1

T49

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T8

1

T11

2

T314

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

38

1

T37

2

T103

1

T315

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

15

1

T8

4

T59

1

T60

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

37

1

T51

1

T80

1

T101

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T36

2

T120

1

T38

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

47

1

T2

1

T11

1

T49

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

12

1

T60

1

T45

2

T316

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T51

1

T49

1

T226

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

16

1

T8

2

T59

2

T317

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T2

1

T81

1

T101

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

20

1

T4

1

T8

2

T11

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

77

1

T51

1

T45

2

T226

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

36

1

T4

1

T59

1

T60

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

54

1

T4

1

T49

2

T45

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T11

1

T120

1

T38

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

38

1

T49

3

T38

1

T45

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

20

1

T4

2

T36

1

T120

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T2

1

T37

2

T237

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T11

1

T60

1

T38

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T51

1

T237

1

T103

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

16

1

T120

1

T45

2

T100

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T8

1

T51

1

T49

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T4

2

T38

2

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T60

1

T49

1

T81

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

28

1

T8

1

T11

1

T38

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T2

2

T37

1

T81

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T4

1

T36

1

T120

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

48

1

T37

1

T81

5

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

38

1

T226

4

T100

1

T237

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

47

1

T51

2

T36

1

T79

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

11

1

T8

1

T60

1

T316

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T2

1

T14

10

T49

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

18

1

T4

1

T8

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

73

1

T14

1

T45

1

T39

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

24

1

T8

1

T36

1

T60

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T45

1

T238

9

T240

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T11

1

T59

1

T45

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

36

1

T51

3

T79

1

T37

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

17

1

T11

1

T59

1

T38

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

36

1

T51

2

T79

6

T45

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

42

1

T4

1

T79

9

T38

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

37

1

T2

1

T45

1

T240

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T36

1

T120

1

T45

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

57

1

T80

9

T45

2

T103

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

23

1

T36

1

T59

1

T38

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

31

1

T51

1

T37

1

T81

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

20

1

T8

2

T11

1

T120

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

41

1

T2

6

T49

4

T81

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

40

1

T4

1

T59

1

T60

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T120

1

T45

1

T239

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

33

1

T11

1

T316

3

T314

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

79

1

T2

4

T51

4

T45

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

62

1

T8

1

T11

1

T100

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T51

1

T235

1

T239

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

34

1

T8

2

T11

1

T36

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

46

1

T49

3

T81

2

T235

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

47

1

T4

2

T11

1

T36

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

116

1

T2

1

T59

1

T39

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

34

1

T11

2

T39

3

T100

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

249

1

T4

5

T8

1

T11

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

14

1

T36

1

T60

1

T100

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

8

1

T36

1

T59

1

T45

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

7

1

T36

1

T120

1

T318

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

4

1

T251

1

T95

1

T319

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T4

1

T60

1

T38

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T4

1

T36

1

T59

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

8

1

T4

1

T59

2

T314

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

3

1

T120

1

T317

1

T319

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

15

1

T4

1

T226

1

T93

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T59

1

T60

1

T45

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T4

1

T254

1

T255

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T59

1

T316

1

T318

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T60

1

T120

1

T237

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T38

1

T318

1

T96

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

10

1

T320

1

T318

2

T96

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T11

1

T314

1

T318

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

11

1

T59

1

T316

1

T320

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

7

1

T320

1

T321

1

T322

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

9

1

T314

1

T96

1

T323

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

13

1

T4

1

T120

2

T39

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T59

1

T120

1

T314

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

10

1

T60

3

T38

1

T316

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

17

1

T4

1

T36

1

T314

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T120

1

T251

1

T324

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

10

1

T36

1

T316

1

T314

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

15

1

T59

1

T90

3

T317

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

6

1

T38

1

T314

1

T317

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

6

1

T36

1

T93

1

T316

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T8

1

T315

2

T320

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

14

1

T11

1

T38

2

T316

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T235

1

T325

1

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T11

1

T59

1

T38

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

106

1

T4

2

T36

2

T59

3

User Defined Cross Bins for cross_combo0

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo1

Samples crossed: cp_combo1_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	26	70	72.92	26
Automatically Generated Cross Bins	96	26	70	72.92	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo1

Element holes

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[0]]	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo1_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo1_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T51

1

T37

1

T81

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T36

1

T59

1

T60

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T2

1

T51

1

T49

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T8

1

T11

2

T36

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

41

1

T37

2

T103

1

T315

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T8

4

T59

1

T60

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T51

1

T80

1

T101

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T4

1

T36

2

T60

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T2

1

T11

1

T49

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T4

1

T36

1

T59

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T51

1

T49

1

T37

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T4

1

T8

2

T59

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

39

1

T2

1

T37

1

T81

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T4

1

T8

2

T11

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

75

1

T51

1

T45

2

T226

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

50

1

T4

2

T59

1

T60

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T4

1

T49

2

T45

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T11

1

T59

1

T60

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

40

1

T49

3

T38

1

T45

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T4

3

T36

1

T120

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T2

1

T37

2

T237

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T11

1

T59

1

T60

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

21

1

T51

1

T103

1

T315

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T60

1

T120

2

T45

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

52

1

T8

1

T51

1

T49

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T4

2

T38

3

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

44

1

T60

1

T49

1

T81

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T8

1

T11

1

T38

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T2

2

T37

1

T81

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T4

1

T11

1

T36

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

52

1

T37

1

T81

5

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

49

1

T59

1

T226

4

T100

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T51

2

T36

1

T79

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

17

1

T8

1

T60

1

T316

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T2

1

T14

10

T49

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T4

1

T8

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

67

1

T14

1

T45

1

T39

2

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T4

1

T8

1

T36

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T45

1

T238

9

T240

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T11

1

T59

2

T120

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

37

1

T51

3

T79

1

T37

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T11

1

T59

1

T60

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T51

2

T79

6

T37

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

59

1

T4

2

T36

1

T79

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

38

1

T2

1

T45

1

T240

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T36

1

T120

2

T45

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

57

1

T80

9

T45

2

T103

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

33

1

T36

2

T59

1

T38

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

34

1

T51

1

T37

2

T81

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

34

1

T8

2

T11

1

T59

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

45

1

T2

6

T49

4

T37

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

46

1

T4

1

T59

1

T60

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

44

1

T120

1

T45

1

T239

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

39

1

T11

1

T36

1

T93

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

77

1

T2

4

T51

4

T45

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

83

1

T8

2

T11

1

T100

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T51

1

T37

1

T235

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

48

1

T8

2

T11

2

T36

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

47

1

T49

3

T81

2

T235

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

49

1

T4

2

T11

1

T36

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

102

1

T2

1

T59

1

T39

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

39

1

T11

3

T59

1

T38

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

184

1

T4

5

T8

1

T11

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

103

1

T4

2

T36

3

T59

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T326

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T326

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T327

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T328

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T329

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T317

6

T330

1

T286

1

User Defined Cross Bins for cross_combo1

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo2

Samples crossed: cp_combo2_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	30	66	68.75	30
Automatically Generated Cross Bins	96	30	66	68.75	30
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo2

Element holes

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	*	*	*	[auto[1]]	--	--	8
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo2_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo2_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T51

1

T37

1

T81

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T36

1

T59

1

T60

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

58

1

T2

1

T51

1

T49

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T8

1

T11

2

T36

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

41

1

T37

2

T103

1

T315

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T8

4

T59

1

T60

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T51

1

T80

1

T101

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T4

1

T36

2

T60

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

46

1

T2

1

T11

1

T49

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T4

1

T36

1

T59

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T51

1

T49

1

T37

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

24

1

T4

1

T8

2

T59

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

38

1

T2

1

T37

1

T81

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T4

1

T8

2

T11

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

76

1

T51

1

T45

2

T101

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

51

1

T4

2

T59

1

T60

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

55

1

T4

1

T49

2

T45

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

24

1

T11

1

T59

1

T60

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

41

1

T49

3

T38

1

T45

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T4

3

T36

1

T120

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

59

1

T2

1

T37

2

T237

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T11

1

T59

1

T60

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T51

1

T237

1

T103

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T60

1

T120

2

T45

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T8

1

T51

1

T49

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T4

2

T38

3

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T60

1

T49

1

T81

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T8

1

T11

1

T38

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

38

1

T2

2

T37

1

T81

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T4

1

T11

1

T36

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

51

1

T37

1

T81

5

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

49

1

T59

1

T226

4

T100

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T51

2

T36

1

T79

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T8

1

T60

1

T316

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T2

1

T14

10

T49

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T4

1

T8

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

74

1

T14

1

T45

1

T39

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T4

1

T8

1

T36

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T45

1

T238

9

T240

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T11

1

T59

2

T120

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T51

3

T79

1

T37

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T11

1

T59

1

T60

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

35

1

T51

2

T79

1

T37

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

59

1

T4

2

T36

1

T79

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

34

1

T2

1

T45

1

T240

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

35

1

T36

1

T120

2

T45

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

60

1

T80

9

T45

2

T103

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

33

1

T36

2

T59

1

T38

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

34

1

T51

1

T37

2

T81

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

35

1

T8

2

T11

1

T59

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

44

1

T2

6

T49

4

T37

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

46

1

T4

1

T59

1

T60

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

45

1

T120

1

T45

1

T239

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

39

1

T11

1

T36

1

T93

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

80

1

T2

4

T51

4

T45

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

83

1

T8

2

T11

1

T100

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

45

1

T51

1

T37

1

T235

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

48

1

T8

2

T11

2

T36

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

52

1

T49

3

T81

2

T235

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

49

1

T4

2

T11

1

T36

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

116

1

T2

1

T59

1

T39

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

39

1

T11

3

T59

1

T38

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

142

1

T36

6

T60

5

T37

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

107

1

T4

2

T36

3

T59

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

1

1

T327

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

13

1

T59

1

T45

1

T320

2

User Defined Cross Bins for cross_combo2

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded

---

Summary for Cross cross_combo3

Samples crossed: cp_combo3_h2l cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel cp_interrupt

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	96	26	70	72.92	26
Automatically Generated Cross Bins	96	26	70	72.92	26
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_combo3

Element holes

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	*	*	[auto[1]]	--	--	4
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_combo3_h2l	cp_key0_in_sel	cp_key1_in_sel	cp_key2_in_sel	cp_pwrb_in_sel	cp_ac_present_sel	cp_interrupt	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_combo3_h2l

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

cp_interrupt

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

57

1

T51

1

T37

1

T81

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

22

1

T36

1

T59

1

T60

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

60

1

T2

1

T51

1

T49

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

25

1

T8

1

T11

2

T36

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

41

1

T37

2

T103

1

T315

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T8

4

T59

1

T60

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

42

1

T51

1

T80

1

T101

1

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

28

1

T4

1

T36

2

T60

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

48

1

T2

1

T11

1

T49

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T4

1

T36

1

T59

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T51

1

T37

1

T226

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T4

1

T8

2

T59

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

40

1

T2

1

T37

1

T81

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

23

1

T4

1

T8

2

T11

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

72

1

T51

1

T45

2

T226

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

51

1

T4

2

T59

1

T60

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

55

1

T4

1

T49

2

T45

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

23

1

T11

1

T59

1

T60

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

42

1

T49

3

T38

1

T45

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

28

1

T4

3

T36

1

T120

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

56

1

T2

1

T37

2

T237

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

29

1

T11

1

T59

1

T60

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

22

1

T51

1

T237

1

T103

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

25

1

T60

1

T120

2

T45

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

49

1

T8

1

T51

1

T49

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

30

1

T4

2

T38

3

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

42

1

T60

1

T49

1

T81

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

38

1

T8

1

T11

1

T38

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

38

1

T37

1

T81

1

T237

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

30

1

T4

1

T11

1

T36

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

51

1

T37

1

T81

5

T45

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

49

1

T59

1

T226

4

T100

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

49

1

T51

2

T36

1

T79

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

18

1

T8

1

T60

1

T316

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T2

1

T14

10

T49

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

27

1

T4

1

T8

1

T11

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

75

1

T14

1

T45

1

T39

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

37

1

T4

1

T8

1

T36

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

44

1

T45

1

T238

9

T240

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

20

1

T11

1

T59

2

T120

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

38

1

T51

3

T79

1

T37

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

27

1

T11

1

T59

1

T60

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

40

1

T51

2

T79

6

T37

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

59

1

T4

2

T36

1

T79

9

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

36

1

T2

1

T45

1

T240

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

34

1

T36

1

T120

2

T45

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

60

1

T80

9

T45

2

T103

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

33

1

T36

2

T59

1

T38

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

33

1

T51

1

T37

2

T81

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

34

1

T8

2

T11

1

T59

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

40

1

T2

6

T49

1

T37

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

46

1

T4

1

T59

1

T60

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T120

1

T45

1

T239

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

39

1

T11

1

T36

1

T93

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

80

1

T2

4

T51

4

T45

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

80

1

T8

2

T11

1

T100

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

44

1

T51

1

T37

1

T235

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

48

1

T8

2

T11

2

T36

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

46

1

T81

2

T93

1

T244

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

49

1

T4

2

T11

1

T36

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

115

1

T59

1

T39

1

T103

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

39

1

T11

3

T59

1

T38

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

168

1

T4

5

T8

1

T11

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

102

1

T4

2

T36

2

T59

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T326

1

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T329

1

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

1

1

T324

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

1

1

T331

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

3

1

T332

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

18

1

T36

1

T60

2

T45

3

User Defined Cross Bins for cross_combo3

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid0	0	Excluded