Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 99.35 96.43 100.00 97.44 98.78 99.61 94.03


Total tests in report: 915
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
59.85 59.85 78.71 78.71 67.64 67.64 91.89 91.89 18.59 18.59 79.08 79.08 68.21 68.21 14.85 14.85 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3411227153
73.70 13.85 87.81 9.11 79.17 11.53 94.86 2.97 48.72 30.13 87.76 8.69 82.56 14.35 35.04 20.18 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3511076046
81.24 7.54 90.95 3.13 82.71 3.54 94.86 0.00 71.79 23.08 90.39 2.62 90.56 8.00 47.42 12.38 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1413878166
85.27 4.03 96.03 5.08 90.19 7.48 96.00 1.14 72.44 0.64 95.75 5.36 95.66 5.11 50.81 3.39 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1408165070
87.93 2.66 96.27 0.24 90.39 0.20 96.23 0.23 76.92 4.49 95.97 0.22 96.24 0.58 63.46 12.65 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.108476351
89.33 1.40 96.34 0.07 90.47 0.08 96.23 0.00 78.21 1.28 96.08 0.11 96.44 0.19 71.53 8.07 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1576963616
90.73 1.40 96.40 0.06 92.90 2.43 96.23 0.00 78.21 0.00 96.16 0.07 97.11 0.67 78.09 6.57 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2692061522
92.08 1.35 96.79 0.39 93.10 0.20 96.46 0.23 82.05 3.85 96.60 0.44 97.69 0.58 81.86 3.77 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.3249216773
93.15 1.07 97.84 1.04 93.30 0.20 96.46 0.00 87.18 5.13 97.71 1.11 97.69 0.00 81.86 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.3916191907
93.70 0.55 98.21 0.37 93.45 0.15 96.46 0.00 89.74 2.56 97.86 0.15 98.07 0.39 82.08 0.22 /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1866107230
94.09 0.39 98.23 0.02 93.50 0.05 98.74 2.28 89.74 0.00 97.89 0.04 98.17 0.10 82.35 0.27 /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2969039870
94.42 0.33 98.30 0.07 93.53 0.03 98.74 0.00 91.03 1.28 98.00 0.11 98.27 0.10 83.05 0.70 /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.901110445
94.73 0.31 98.40 0.09 93.71 0.18 99.32 0.57 91.03 0.00 98.11 0.11 98.36 0.10 84.18 1.13 /workspace/coverage/default/28.sysrst_ctrl_stress_all.1181685203
95.01 0.29 98.49 0.09 93.78 0.08 99.32 0.00 91.03 0.00 98.11 0.00 98.36 0.00 86.01 1.83 /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.1101851135
95.28 0.27 98.56 0.07 93.98 0.20 99.32 0.00 92.31 1.28 98.19 0.07 98.55 0.19 86.06 0.05 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.61399365
95.54 0.26 98.82 0.26 94.14 0.15 99.77 0.46 92.95 0.64 98.26 0.07 98.75 0.19 86.11 0.05 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.4028521265
95.78 0.23 98.88 0.06 94.16 0.03 99.77 0.00 94.23 1.28 98.34 0.07 98.94 0.19 86.11 0.00 /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3108057576
95.97 0.19 98.90 0.02 94.31 0.15 99.77 0.00 94.23 0.00 98.34 0.00 99.04 0.10 87.19 1.08 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3346345102
96.13 0.16 98.90 0.00 95.17 0.86 99.77 0.00 94.23 0.00 98.34 0.00 99.04 0.00 87.46 0.27 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.2978773743
96.28 0.15 98.90 0.00 95.22 0.05 99.77 0.00 94.23 0.00 98.34 0.00 99.04 0.00 88.48 1.02 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3419981828
96.43 0.15 98.94 0.04 95.25 0.03 99.77 0.00 94.87 0.64 98.37 0.04 99.13 0.10 88.70 0.22 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1003351549
96.57 0.13 98.97 0.04 95.27 0.03 99.77 0.00 95.51 0.64 98.41 0.04 99.23 0.10 88.81 0.11 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1085160529
96.70 0.13 98.97 0.00 95.27 0.00 99.77 0.00 95.51 0.00 98.41 0.00 99.23 0.00 89.72 0.91 /workspace/coverage/default/30.sysrst_ctrl_combo_detect.2194850346
96.82 0.12 99.01 0.04 95.30 0.03 99.77 0.00 96.15 0.64 98.45 0.04 99.33 0.10 89.72 0.00 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.864686741
96.94 0.12 99.05 0.04 95.32 0.03 99.77 0.00 96.79 0.64 98.48 0.04 99.42 0.10 89.72 0.00 /workspace/coverage/default/20.sysrst_ctrl_stress_all.2475244269
97.06 0.12 99.09 0.04 95.35 0.03 99.77 0.00 97.44 0.64 98.52 0.04 99.52 0.10 89.72 0.00 /workspace/coverage/default/47.sysrst_ctrl_edge_detect.1869108075
97.14 0.08 99.09 0.00 95.48 0.13 99.77 0.00 97.44 0.00 98.52 0.00 99.52 0.00 90.15 0.43 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.4266729222
97.20 0.06 99.09 0.00 95.78 0.30 99.77 0.00 97.44 0.00 98.52 0.00 99.52 0.00 90.26 0.11 /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3884474405
97.25 0.06 99.10 0.02 95.78 0.00 99.77 0.00 97.44 0.00 98.52 0.00 99.52 0.00 90.64 0.38 /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.1288122803
97.30 0.05 99.16 0.06 95.85 0.08 100.00 0.23 97.44 0.00 98.52 0.00 99.52 0.00 90.64 0.00 /workspace/coverage/default/16.sysrst_ctrl_alert_test.2833993610
97.35 0.05 99.20 0.04 96.01 0.15 100.00 0.00 97.44 0.00 98.60 0.07 99.61 0.10 90.64 0.00 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3439705577
97.40 0.05 99.20 0.00 96.01 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 90.96 0.32 /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1578113607
97.45 0.05 99.20 0.00 96.01 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 91.28 0.32 /workspace/coverage/default/15.sysrst_ctrl_combo_detect.1644097256
97.49 0.04 99.20 0.00 96.01 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 91.55 0.27 /workspace/coverage/default/24.sysrst_ctrl_stress_all.4112810906
97.52 0.04 99.25 0.06 96.06 0.05 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 91.71 0.16 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1503117742
97.56 0.03 99.25 0.00 96.28 0.23 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 91.71 0.00 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.324848806
97.59 0.03 99.25 0.00 96.28 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 91.93 0.22 /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1597417355
97.61 0.02 99.25 0.00 96.28 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 92.09 0.16 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3031897032
97.63 0.02 99.25 0.00 96.28 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 92.25 0.16 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.3834074815
97.66 0.02 99.25 0.00 96.28 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 92.41 0.16 /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.2736503312
97.68 0.02 99.25 0.00 96.28 0.00 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 92.57 0.16 /workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.3056760233
97.70 0.02 99.25 0.00 96.31 0.03 100.00 0.00 97.44 0.00 98.60 0.00 99.61 0.00 92.68 0.11 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.1701556319
97.71 0.02 99.29 0.04 96.31 0.00 100.00 0.00 97.44 0.00 98.67 0.07 99.61 0.00 92.68 0.00 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.2335364011
97.73 0.02 99.29 0.00 96.31 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 92.79 0.11 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.4133802491
97.75 0.02 99.29 0.00 96.31 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 92.90 0.11 /workspace/coverage/default/17.sysrst_ctrl_combo_detect.3925021809
97.76 0.02 99.29 0.00 96.31 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 93.00 0.11 /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3990487644
97.78 0.02 99.29 0.00 96.31 0.00 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 93.11 0.11 /workspace/coverage/default/9.sysrst_ctrl_stress_all.3868393314
97.79 0.01 99.29 0.00 96.36 0.05 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 93.16 0.05 /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.3230788851
97.80 0.01 99.29 0.00 96.39 0.03 100.00 0.00 97.44 0.00 98.67 0.00 99.61 0.00 93.22 0.05 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.2530480190
97.81 0.01 99.31 0.02 96.39 0.00 100.00 0.00 97.44 0.00 98.71 0.04 99.61 0.00 93.22 0.00 /workspace/coverage/default/14.sysrst_ctrl_edge_detect.1648738705
97.82 0.01 99.33 0.02 96.39 0.00 100.00 0.00 97.44 0.00 98.74 0.04 99.61 0.00 93.22 0.00 /workspace/coverage/default/16.sysrst_ctrl_stress_all.739259774
97.83 0.01 99.35 0.02 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.04 99.61 0.00 93.22 0.00 /workspace/coverage/default/2.sysrst_ctrl_stress_all.3397733793
97.83 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.27 0.05 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.1654268214
97.84 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.33 0.05 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.285658839
97.85 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.38 0.05 /workspace/coverage/default/1.sysrst_ctrl_combo_detect.900219060
97.86 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.43 0.05 /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.332037497
97.86 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.49 0.05 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1306243459
97.87 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.54 0.05 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.4254738340
97.88 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.60 0.05 /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1682948603
97.89 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.65 0.05 /workspace/coverage/default/20.sysrst_ctrl_combo_detect.2416924230
97.90 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.70 0.05 /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.3662039549
97.90 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.76 0.05 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3096616270
97.91 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.81 0.05 /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3744609404
97.92 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.86 0.05 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.1787140070
97.93 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.92 0.05 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3706791840
97.93 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 93.97 0.05 /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.635079583
97.94 0.01 99.35 0.00 96.39 0.00 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 94.03 0.05 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.970523869
97.94 0.01 99.35 0.00 96.41 0.03 100.00 0.00 97.44 0.00 98.78 0.00 99.61 0.00 94.03 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2741054923


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3407657394
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1009982010
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.3108711002
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2297027731
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2302605969
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3440265518
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2555912585
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3257684622
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.1938987364
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1740332356
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.35656899
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3397700710
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.111970084
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2850413471
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.563631063
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1620326561
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.331314747
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3846057425
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.553211909
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.4094061292
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1026954050
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.4061191976
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1275588324
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.965398104
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1100292942
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.1984345959
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.3890065846
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2852271904
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.394202748
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.2978933987
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.2013048024
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.1092221825
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2543041137
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.490714507
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3559722423
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.2091478284
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2801533812
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.4045771755
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.1108620302
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.4220542217
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.797923192
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2134093433
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.4126141444
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2341301971
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.498717208
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.537844529
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2270162562
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.2458280817
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3240028550
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.2779168776
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1870189008
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.3329906160
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.661463525
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.2168216821
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3339931405
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.132568256
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3625030602
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3966438089
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.992490777
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.489136195
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.1926624308
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.755569879
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.484977168
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.3418965096
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1715937665
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.3174499885
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.1440484145
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1227656859
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2444784318
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3940611777
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2822570924
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1181711972
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2986798233
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.439077833
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.2678240262
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1872049937
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2959687398
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.9004192
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1152964634
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2230507197
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.672668012
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/workspace/coverage/default/42.sysrst_ctrl_alert_test.3706469310
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.92359907
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.1199500017
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1649343911
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.1257020187
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3651278380
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1034897568
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.1438293050
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2969877744
/workspace/coverage/default/42.sysrst_ctrl_smoke.1738130951
/workspace/coverage/default/42.sysrst_ctrl_stress_all.3489143522
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.939553941
/workspace/coverage/default/43.sysrst_ctrl_alert_test.1172602031
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.224352440
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.209077538
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2265896009
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.125880835
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.3327676880
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1402179958
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2202162391
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.95731125
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.1863813557
/workspace/coverage/default/43.sysrst_ctrl_smoke.117488167
/workspace/coverage/default/43.sysrst_ctrl_stress_all.2706251476
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3325077901
/workspace/coverage/default/44.sysrst_ctrl_alert_test.1325047655
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2427483628
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.2016332413
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2907637377
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3057483378
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.149691643
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.376227597
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1000401332
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2489492754
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.1923232094
/workspace/coverage/default/44.sysrst_ctrl_smoke.1437728550
/workspace/coverage/default/44.sysrst_ctrl_stress_all.1653567277
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.3133845506
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.292059449
/workspace/coverage/default/45.sysrst_ctrl_alert_test.3101567228
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1867891313
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.3674764238
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4007941602
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.4170125768
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.1634747517
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.1696790029
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1880444486
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.4047298536
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.200975485
/workspace/coverage/default/45.sysrst_ctrl_smoke.1276502266
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.640847693
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1119033118
/workspace/coverage/default/46.sysrst_ctrl_alert_test.3154205839
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3568237906
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.1641751793
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2628551525
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.3853477578
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.2931841127
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.163987446
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1695018347
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.4186088695
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1684914537
/workspace/coverage/default/46.sysrst_ctrl_smoke.3040917702
/workspace/coverage/default/46.sysrst_ctrl_stress_all.1758772180
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.670299195
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.4156930884
/workspace/coverage/default/47.sysrst_ctrl_alert_test.869408174
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3088210106
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2358673326
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1650238539
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.25474542
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.1736092078
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.3178100854
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.1835621474
/workspace/coverage/default/47.sysrst_ctrl_smoke.2209167164
/workspace/coverage/default/47.sysrst_ctrl_stress_all.2269700625
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2269156464
/workspace/coverage/default/48.sysrst_ctrl_alert_test.3760676659
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.189861430
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.2785531473
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3380375030
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.886912960
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.3261705620
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2819963213
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.885113950
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2605397342
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.2545399255
/workspace/coverage/default/48.sysrst_ctrl_smoke.1119737007
/workspace/coverage/default/48.sysrst_ctrl_stress_all.4076692336
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.493332924
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3944574445
/workspace/coverage/default/49.sysrst_ctrl_alert_test.2376439611
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.727420687
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.360671157
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.1171150089
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.1595167204
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.4118317275
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.2161067117
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1708973125
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.3980094126
/workspace/coverage/default/49.sysrst_ctrl_smoke.2978380215
/workspace/coverage/default/49.sysrst_ctrl_stress_all.370515678
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2452156718
/workspace/coverage/default/5.sysrst_ctrl_alert_test.3772476761
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.3709475517
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2676756739
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1954445251
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2631585146
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.2873396727
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3609571999
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2470906998
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.595367369
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.3263965479
/workspace/coverage/default/5.sysrst_ctrl_smoke.1370832365
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3129714864
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.1915554742
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.341892893
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.1914195934
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1119076632
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2590180606
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.1496297886
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.1774171444
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2590163071
/workspace/coverage/default/6.sysrst_ctrl_alert_test.556674982
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.4138440623
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2658376497
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1157830406
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2501084637
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1355830499
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3597691719
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.180489573
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.2068276656
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.1255262209
/workspace/coverage/default/6.sysrst_ctrl_smoke.1390859296
/workspace/coverage/default/6.sysrst_ctrl_stress_all.1785807867
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.335882692
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.395052048
/workspace/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.4009121197
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.811833432
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.643911142
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.4034017507
/workspace/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.2368257873
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.788297664
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2158796870
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3846342926
/workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2603165804
/workspace/coverage/default/7.sysrst_ctrl_alert_test.1727513637
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.670030537
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.2408493885
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1718270469
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1050729801
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1481462969
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.2666451751
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.917740701
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.3644184528
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.4264766409
/workspace/coverage/default/7.sysrst_ctrl_smoke.2968551240
/workspace/coverage/default/7.sysrst_ctrl_stress_all.1210790594
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1762506914
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1907192337
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2358266616
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.3300742384
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1565851566
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.266880819
/workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.1907853578
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2231646337
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3585126451
/workspace/coverage/default/8.sysrst_ctrl_alert_test.377308708
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.3821913903
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.4136899201
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2884878194
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3961340565
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.4067747596
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1718156266
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3872025828
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.3738344556
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.1178204508
/workspace/coverage/default/8.sysrst_ctrl_smoke.2311167880
/workspace/coverage/default/8.sysrst_ctrl_stress_all.3603171674
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3668102025
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3800413724
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2534003696
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1660638212
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3588727449
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2333986349
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3500343671
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.468522984
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.4075747114
/workspace/coverage/default/9.sysrst_ctrl_alert_test.473108325
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1500101765
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.737858619
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1507312641
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.3614230042
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.1029847222
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1128502555
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.938088957
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.450375709
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.1271172402
/workspace/coverage/default/9.sysrst_ctrl_smoke.4050124980
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.694394193
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1426954241
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.25131165
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.934196906
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.278319114
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3554426294
/workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3992971693
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.783977584
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.4103418992
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1377853459




Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T5 /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.3298262333 Jul 10 06:23:24 PM PDT 24 Jul 10 06:23:35 PM PDT 24 3693309420 ps
T6 /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2625832226 Jul 10 06:20:10 PM PDT 24 Jul 10 06:20:13 PM PDT 24 2179943621 ps
T7 /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.1939017581 Jul 10 06:22:46 PM PDT 24 Jul 10 06:22:49 PM PDT 24 2188024005 ps
T1 /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3884474405 Jul 10 06:22:19 PM PDT 24 Jul 10 06:25:00 PM PDT 24 2824913236210 ps
T2 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3411227153 Jul 10 06:24:27 PM PDT 24 Jul 10 06:28:36 PM PDT 24 105640924668 ps
T3 /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2562864042 Jul 10 06:22:49 PM PDT 24 Jul 10 06:22:53 PM PDT 24 4128436459 ps
T4 /workspace/coverage/default/28.sysrst_ctrl_stress_all.1181685203 Jul 10 06:22:59 PM PDT 24 Jul 10 06:25:51 PM PDT 24 127326703228 ps
T14 /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.33233655 Jul 10 06:22:08 PM PDT 24 Jul 10 06:23:59 PM PDT 24 42334822347 ps
T15 /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.1307733554 Jul 10 06:21:57 PM PDT 24 Jul 10 06:22:02 PM PDT 24 2472931411 ps
T16 /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.573432087 Jul 10 06:23:27 PM PDT 24 Jul 10 06:24:31 PM PDT 24 25081169248 ps
T17 /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1520023965 Jul 10 06:23:46 PM PDT 24 Jul 10 06:23:50 PM PDT 24 2283628235 ps
T18 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1650238539 Jul 10 06:24:06 PM PDT 24 Jul 10 06:24:23 PM PDT 24 4391870250 ps
T8 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.3072080941 Jul 10 06:22:54 PM PDT 24 Jul 10 06:23:39 PM PDT 24 98006977573 ps
T50 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.2717726846 Jul 10 06:20:50 PM PDT 24 Jul 10 06:21:57 PM PDT 24 26829126342 ps
T61 /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3005964581 Jul 10 06:21:04 PM PDT 24 Jul 10 06:21:10 PM PDT 24 3133469382 ps
T26 /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.2492157085 Jul 10 06:22:54 PM PDT 24 Jul 10 06:23:02 PM PDT 24 2466072472 ps
T28 /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.288299536 Jul 10 06:23:46 PM PDT 24 Jul 10 06:23:51 PM PDT 24 2529971194 ps
T69 /workspace/coverage/default/16.sysrst_ctrl_alert_test.2833993610 Jul 10 06:22:14 PM PDT 24 Jul 10 06:22:21 PM PDT 24 2013499951 ps
T75 /workspace/coverage/default/28.sysrst_ctrl_alert_test.4266738408 Jul 10 06:23:02 PM PDT 24 Jul 10 06:23:09 PM PDT 24 2015163546 ps
T76 /workspace/coverage/default/44.sysrst_ctrl_smoke.1437728550 Jul 10 06:23:52 PM PDT 24 Jul 10 06:23:56 PM PDT 24 2117673271 ps
T9 /workspace/coverage/default/21.sysrst_ctrl_stress_all.3664829114 Jul 10 06:22:37 PM PDT 24 Jul 10 06:22:47 PM PDT 24 14778145220 ps
T10 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.4028521265 Jul 10 06:23:00 PM PDT 24 Jul 10 06:23:03 PM PDT 24 4489781691 ps
T27 /workspace/coverage/default/41.sysrst_ctrl_stress_all.3640902674 Jul 10 06:23:44 PM PDT 24 Jul 10 06:23:56 PM PDT 24 6616751990 ps
T58 /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.296357781 Jul 10 06:23:41 PM PDT 24 Jul 10 06:23:51 PM PDT 24 3456388476 ps
T29 /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.326423889 Jul 10 06:23:30 PM PDT 24 Jul 10 06:23:33 PM PDT 24 2623540524 ps
T11 /workspace/coverage/default/45.sysrst_ctrl_combo_detect.3674764238 Jul 10 06:23:59 PM PDT 24 Jul 10 06:28:59 PM PDT 24 111191165537 ps
T12 /workspace/coverage/default/41.sysrst_ctrl_edge_detect.3665797379 Jul 10 06:23:48 PM PDT 24 Jul 10 06:24:03 PM PDT 24 5128874488 ps
T13 /workspace/coverage/default/19.sysrst_ctrl_edge_detect.3354198602 Jul 10 06:22:24 PM PDT 24 Jul 10 06:22:32 PM PDT 24 18006931344 ps
T77 /workspace/coverage/default/1.sysrst_ctrl_smoke.3887122934 Jul 10 06:20:21 PM PDT 24 Jul 10 06:20:26 PM PDT 24 2116357805 ps
T70 /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3978552139 Jul 10 06:23:00 PM PDT 24 Jul 10 06:23:06 PM PDT 24 2614373373 ps
T35 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1408165070 Jul 10 06:24:04 PM PDT 24 Jul 10 06:25:11 PM PDT 24 24381802094 ps
T51 /workspace/coverage/default/11.sysrst_ctrl_combo_detect.3611755223 Jul 10 06:21:47 PM PDT 24 Jul 10 06:22:45 PM PDT 24 45961503195 ps
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T30 /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3568237906 Jul 10 06:24:05 PM PDT 24 Jul 10 06:24:15 PM PDT 24 3382097231 ps
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T25 /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.3108057576 Jul 10 06:23:14 PM PDT 24 Jul 10 06:23:16 PM PDT 24 5595140502 ps
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T67 /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.50203048 Jul 10 06:22:08 PM PDT 24 Jul 10 06:22:11 PM PDT 24 2487930742 ps
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T73 /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.3684822992 Jul 10 06:20:32 PM PDT 24 Jul 10 06:20:40 PM PDT 24 2510800302 ps
T296 /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.4283637994 Jul 10 06:23:36 PM PDT 24 Jul 10 06:23:39 PM PDT 24 3134268603 ps
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T74 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.789427479 Jul 10 06:20:57 PM PDT 24 Jul 10 06:21:03 PM PDT 24 2512540391 ps
T376 /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.3885056909 Jul 10 06:23:24 PM PDT 24 Jul 10 06:23:29 PM PDT 24 2619394723 ps
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T54 /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.3202704677 Jul 10 06:22:18 PM PDT 24 Jul 10 06:22:47 PM PDT 24 42840375114 ps
T379 /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3333102624 Jul 10 06:22:06 PM PDT 24 Jul 10 06:22:10 PM PDT 24 4389312350 ps
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T63 /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2676619652 Jul 10 06:22:49 PM PDT 24 Jul 10 06:23:29 PM PDT 24 36998180021 ps
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T55 /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.670030537 Jul 10 06:21:25 PM PDT 24 Jul 10 06:21:32 PM PDT 24 4011358479 ps
T48 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.865684819 Jul 10 06:20:44 PM PDT 24 Jul 10 06:20:51 PM PDT 24 2368867324 ps
T43 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3511076046 Jul 10 06:24:10 PM PDT 24 Jul 10 06:26:26 PM PDT 24 54014205840 ps
T38 /workspace/coverage/default/42.sysrst_ctrl_stress_all.3489143522 Jul 10 06:23:44 PM PDT 24 Jul 10 06:24:41 PM PDT 24 80208541869 ps
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T218 /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.2372615180 Jul 10 06:22:31 PM PDT 24 Jul 10 06:22:34 PM PDT 24 4394013263 ps
T68 /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.2555681679 Jul 10 06:22:25 PM PDT 24 Jul 10 06:22:32 PM PDT 24 2453259126 ps
T219 /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3200454715 Jul 10 06:23:08 PM PDT 24 Jul 10 06:25:28 PM PDT 24 960260243318 ps
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T220 /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.524588634 Jul 10 06:22:28 PM PDT 24 Jul 10 06:22:40 PM PDT 24 3797099880 ps
T80 /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1954445251 Jul 10 06:21:11 PM PDT 24 Jul 10 06:22:39 PM PDT 24 32360182986 ps
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T81 /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.1507312641 Jul 10 06:21:36 PM PDT 24 Jul 10 06:24:51 PM PDT 24 79680453783 ps
T42 /workspace/coverage/default/31.sysrst_ctrl_stress_all.4112944051 Jul 10 06:23:14 PM PDT 24 Jul 10 06:23:22 PM PDT 24 18076732289 ps
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T384 /workspace/coverage/default/32.sysrst_ctrl_smoke.157395994 Jul 10 06:23:16 PM PDT 24 Jul 10 06:23:19 PM PDT 24 2127879013 ps
T374 /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.419750305 Jul 10 06:22:49 PM PDT 24 Jul 10 06:22:58 PM PDT 24 2511340643 ps
T385 /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1931252476 Jul 10 06:23:46 PM PDT 24 Jul 10 06:23:51 PM PDT 24 2814225051 ps
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T57 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1576963616 Jul 10 06:23:45 PM PDT 24 Jul 10 06:24:04 PM PDT 24 54618447555 ps
T112 /workspace/coverage/default/1.sysrst_ctrl_sec_cm.2969039870 Jul 10 06:20:33 PM PDT 24 Jul 10 06:21:02 PM PDT 24 22020356697 ps
T113 /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.3257014626 Jul 10 06:23:08 PM PDT 24 Jul 10 06:32:59 PM PDT 24 330715927343 ps
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T116 /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.821688637 Jul 10 06:20:38 PM PDT 24 Jul 10 06:36:46 PM PDT 24 812466463334 ps
T82 /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.670458392 Jul 10 06:22:50 PM PDT 24 Jul 10 06:22:58 PM PDT 24 8912604804 ps
T117 /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3088210106 Jul 10 06:24:07 PM PDT 24 Jul 10 06:24:17 PM PDT 24 3981974318 ps
T118 /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.2605397342 Jul 10 06:24:13 PM PDT 24 Jul 10 06:24:25 PM PDT 24 2184804744 ps
T119 /workspace/coverage/default/17.sysrst_ctrl_smoke.1286897672 Jul 10 06:22:11 PM PDT 24 Jul 10 06:22:14 PM PDT 24 2131247561 ps
T282 /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3828884973 Jul 10 06:22:49 PM PDT 24 Jul 10 06:22:55 PM PDT 24 2471449273 ps
T373 /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.2756160648 Jul 10 06:23:22 PM PDT 24 Jul 10 06:23:27 PM PDT 24 2525152202 ps
T387 /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1402179958 Jul 10 06:23:52 PM PDT 24 Jul 10 06:23:57 PM PDT 24 2613024934 ps
T388 /workspace/coverage/default/12.sysrst_ctrl_smoke.3632301759 Jul 10 06:21:47 PM PDT 24 Jul 10 06:21:53 PM PDT 24 2112531301 ps
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T83 /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3800413724 Jul 10 06:21:30 PM PDT 24 Jul 10 06:21:33 PM PDT 24 2872719477 ps
T269 /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3668102025 Jul 10 06:21:30 PM PDT 24 Jul 10 06:22:05 PM PDT 24 266411154327 ps
T288 /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.479372922 Jul 10 06:22:16 PM PDT 24 Jul 10 06:22:19 PM PDT 24 2496080335 ps
T45 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1413878166 Jul 10 06:22:27 PM PDT 24 Jul 10 06:23:07 PM PDT 24 221037060113 ps
T39 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3031897032 Jul 10 06:21:48 PM PDT 24 Jul 10 06:22:28 PM PDT 24 60426725886 ps
T224 /workspace/coverage/default/46.sysrst_ctrl_smoke.3040917702 Jul 10 06:24:03 PM PDT 24 Jul 10 06:24:13 PM PDT 24 2111898315 ps
T225 /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1805073731 Jul 10 06:23:06 PM PDT 24 Jul 10 06:23:10 PM PDT 24 2516008096 ps
T226 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2231646337 Jul 10 06:24:17 PM PDT 24 Jul 10 06:31:12 PM PDT 24 160357959415 ps
T227 /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.1501057381 Jul 10 06:23:21 PM PDT 24 Jul 10 06:23:24 PM PDT 24 4739373297 ps
T228 /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.395052048 Jul 10 06:21:16 PM PDT 24 Jul 10 06:21:18 PM PDT 24 3660563153 ps
T229 /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.95731125 Jul 10 06:23:53 PM PDT 24 Jul 10 06:23:56 PM PDT 24 2164716616 ps
T230 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.984088593 Jul 10 06:20:32 PM PDT 24 Jul 10 06:20:39 PM PDT 24 2297266102 ps
T231 /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.3730495841 Jul 10 06:22:31 PM PDT 24 Jul 10 06:22:39 PM PDT 24 2513336394 ps
T390 /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.152959881 Jul 10 06:23:16 PM PDT 24 Jul 10 06:23:19 PM PDT 24 2211796063 ps
T391 /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.333765074 Jul 10 06:23:00 PM PDT 24 Jul 10 06:23:02 PM PDT 24 2728669075 ps
T99 /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.25131165 Jul 10 06:24:22 PM PDT 24 Jul 10 06:25:01 PM PDT 24 24586496459 ps
T100 /workspace/coverage/default/22.sysrst_ctrl_combo_detect.783429295 Jul 10 06:22:43 PM PDT 24 Jul 10 06:23:21 PM PDT 24 59366873379 ps
T392 /workspace/coverage/default/14.sysrst_ctrl_smoke.210898920 Jul 10 06:21:58 PM PDT 24 Jul 10 06:22:04 PM PDT 24 2112258107 ps
T101 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.3503266419 Jul 10 06:23:36 PM PDT 24 Jul 10 06:25:01 PM PDT 24 33405240922 ps
T170 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.1029847222 Jul 10 06:21:37 PM PDT 24 Jul 10 06:21:40 PM PDT 24 3767128502 ps
T102 /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.811833432 Jul 10 06:24:17 PM PDT 24 Jul 10 06:24:32 PM PDT 24 27081966075 ps
T46 /workspace/coverage/default/36.sysrst_ctrl_edge_detect.1038180405 Jul 10 06:23:27 PM PDT 24 Jul 10 06:23:29 PM PDT 24 3686203658 ps
T393 /workspace/coverage/default/36.sysrst_ctrl_alert_test.1961196339 Jul 10 06:23:29 PM PDT 24 Jul 10 06:23:33 PM PDT 24 2019309014 ps
T394 /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.1345908057 Jul 10 06:21:04 PM PDT 24 Jul 10 06:21:09 PM PDT 24 2246765678 ps
T84 /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.3248954938 Jul 10 06:22:25 PM PDT 24 Jul 10 06:22:35 PM PDT 24 224485302933 ps
T237 /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3346345102 Jul 10 06:23:42 PM PDT 24 Jul 10 06:25:08 PM PDT 24 39563948611 ps
T395 /workspace/coverage/default/30.sysrst_ctrl_alert_test.3423105678 Jul 10 06:23:14 PM PDT 24 Jul 10 06:23:18 PM PDT 24 2027283722 ps
T396 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.790157446 Jul 10 06:20:21 PM PDT 24 Jul 10 06:20:24 PM PDT 24 2439754268 ps
T103 /workspace/coverage/default/33.sysrst_ctrl_combo_detect.813268303 Jul 10 06:23:21 PM PDT 24 Jul 10 06:24:06 PM PDT 24 85434232550 ps
T397 /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.109069242 Jul 10 06:22:58 PM PDT 24 Jul 10 06:23:00 PM PDT 24 2820455917 ps
T398 /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3406633653 Jul 10 06:23:33 PM PDT 24 Jul 10 06:23:40 PM PDT 24 3335904262 ps
T283 /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3966481007 Jul 10 06:21:49 PM PDT 24 Jul 10 06:21:56 PM PDT 24 3744769695 ps
T270 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2923010100 Jul 10 06:22:02 PM PDT 24 Jul 10 06:24:24 PM PDT 24 53653343625 ps
T399 /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.935666462 Jul 10 06:22:43 PM PDT 24 Jul 10 06:22:49 PM PDT 24 2267084269 ps
T235 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3419981828 Jul 10 06:24:16 PM PDT 24 Jul 10 06:24:59 PM PDT 24 83669108374 ps
T289 /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.1695018347 Jul 10 06:24:03 PM PDT 24 Jul 10 06:24:09 PM PDT 24 2483873303 ps
T238 /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2590163071 Jul 10 06:24:16 PM PDT 24 Jul 10 06:24:54 PM PDT 24 67923367131 ps
T85 /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3255168962 Jul 10 06:22:43 PM PDT 24 Jul 10 06:22:51 PM PDT 24 5105247128 ps
T86 /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.292059449 Jul 10 06:23:59 PM PDT 24 Jul 10 06:24:09 PM PDT 24 10789989594 ps
T400 /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.995067047 Jul 10 06:23:39 PM PDT 24 Jul 10 06:23:47 PM PDT 24 2511891769 ps
T401 /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1142974493 Jul 10 06:23:10 PM PDT 24 Jul 10 06:23:12 PM PDT 24 2680500369 ps
T402 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.4170125768 Jul 10 06:23:58 PM PDT 24 Jul 10 06:24:05 PM PDT 24 3778631180 ps
T403 /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.2426214378 Jul 10 06:20:05 PM PDT 24 Jul 10 06:20:09 PM PDT 24 2464782076 ps
T149 /workspace/coverage/default/39.sysrst_ctrl_edge_detect.1524343721 Jul 10 06:23:47 PM PDT 24 Jul 10 06:23:52 PM PDT 24 4519374666 ps
T121 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2410269467 Jul 10 06:23:02 PM PDT 24 Jul 10 06:23:05 PM PDT 24 9357168012 ps
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T236 /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.2590180606 Jul 10 06:24:16 PM PDT 24 Jul 10 06:24:34 PM PDT 24 26725405307 ps
T248 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2328943508 Jul 10 06:21:52 PM PDT 24 Jul 10 06:22:21 PM PDT 24 81458695840 ps
T239 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2265896009 Jul 10 06:23:52 PM PDT 24 Jul 10 06:27:46 PM PDT 24 88589557584 ps
T405 /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.4163776496 Jul 10 06:20:12 PM PDT 24 Jul 10 06:20:14 PM PDT 24 2194709536 ps
T406 /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.2202162391 Jul 10 06:23:51 PM PDT 24 Jul 10 06:23:55 PM PDT 24 2462442460 ps
T407 /workspace/coverage/default/28.sysrst_ctrl_smoke.1163471323 Jul 10 06:23:00 PM PDT 24 Jul 10 06:23:08 PM PDT 24 2110585852 ps
T93 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.108476351 Jul 10 06:23:46 PM PDT 24 Jul 10 06:24:46 PM PDT 24 971967455116 ps
T408 /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2246836275 Jul 10 06:23:33 PM PDT 24 Jul 10 06:23:42 PM PDT 24 3321932859 ps
T409 /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.3804209850 Jul 10 06:21:39 PM PDT 24 Jul 10 06:21:47 PM PDT 24 2473239726 ps
T290 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.984631277 Jul 10 06:23:23 PM PDT 24 Jul 10 06:23:31 PM PDT 24 2445874413 ps
T240 /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2158796870 Jul 10 06:24:15 PM PDT 24 Jul 10 06:26:57 PM PDT 24 55469606115 ps
T410 /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.3875534036 Jul 10 06:22:55 PM PDT 24 Jul 10 06:23:03 PM PDT 24 2511228275 ps
T411 /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3809628260 Jul 10 06:23:08 PM PDT 24 Jul 10 06:23:14 PM PDT 24 2084371222 ps
T150 /workspace/coverage/default/43.sysrst_ctrl_edge_detect.3327676880 Jul 10 06:23:56 PM PDT 24 Jul 10 06:23:59 PM PDT 24 4558042432 ps
T412 /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.2778460900 Jul 10 06:23:00 PM PDT 24 Jul 10 06:23:11 PM PDT 24 3536136134 ps
T316 /workspace/coverage/default/30.sysrst_ctrl_combo_detect.2194850346 Jul 10 06:23:14 PM PDT 24 Jul 10 06:24:05 PM PDT 24 98621821728 ps
T413 /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.600886623 Jul 10 06:23:21 PM PDT 24 Jul 10 06:23:30 PM PDT 24 2611687546 ps
T156 /workspace/coverage/default/28.sysrst_ctrl_edge_detect.1928432585 Jul 10 06:23:01 PM PDT 24 Jul 10 06:24:13 PM PDT 24 1219452398331 ps
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T122 /workspace/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.3771748053 Jul 10 06:22:05 PM PDT 24 Jul 10 06:22:15 PM PDT 24 40700500267 ps
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T416 /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1867891313 Jul 10 06:23:57 PM PDT 24 Jul 10 06:24:09 PM PDT 24 3608737146 ps
T417 /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.986609104 Jul 10 06:20:38 PM PDT 24 Jul 10 06:20:44 PM PDT 24 2053206266 ps
T418 /workspace/coverage/default/6.sysrst_ctrl_alert_test.556674982 Jul 10 06:21:16 PM PDT 24 Jul 10 06:21:23 PM PDT 24 2011460095 ps
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T419 /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3745707334 Jul 10 06:23:42 PM PDT 24 Jul 10 06:23:48 PM PDT 24 2628290768 ps
T249 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.4254738340 Jul 10 06:22:06 PM PDT 24 Jul 10 06:24:30 PM PDT 24 57293108284 ps
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T428 /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.2698224840 Jul 10 06:22:24 PM PDT 24 Jul 10 06:22:31 PM PDT 24 3632226478 ps
T315 /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1019731882 Jul 10 06:22:16 PM PDT 24 Jul 10 06:26:05 PM PDT 24 83166154265 ps
T124 /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.1389012831 Jul 10 06:23:34 PM PDT 24 Jul 10 06:23:43 PM PDT 24 10795525150 ps
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T183 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.640847693 Jul 10 06:24:01 PM PDT 24 Jul 10 06:25:36 PM PDT 24 39967240741 ps
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T432 /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.939553941 Jul 10 06:23:45 PM PDT 24 Jul 10 06:23:48 PM PDT 24 3629457866 ps
T433 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.2820686239 Jul 10 06:22:55 PM PDT 24 Jul 10 06:22:58 PM PDT 24 2626471331 ps
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T436 /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.3858728369 Jul 10 06:22:02 PM PDT 24 Jul 10 06:22:05 PM PDT 24 2628876882 ps
T437 /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1896849152 Jul 10 06:22:02 PM PDT 24 Jul 10 06:22:06 PM PDT 24 3103859368 ps
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T250 /workspace/coverage/default/24.sysrst_ctrl_combo_detect.297698470 Jul 10 06:22:49 PM PDT 24 Jul 10 06:29:14 PM PDT 24 149407077143 ps
T439 /workspace/coverage/default/45.sysrst_ctrl_smoke.1276502266 Jul 10 06:24:03 PM PDT 24 Jul 10 06:24:13 PM PDT 24 2112392996 ps
T440 /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1827747557 Jul 10 06:20:50 PM PDT 24 Jul 10 06:21:01 PM PDT 24 4035536809 ps
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T292 /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.4264766409 Jul 10 06:21:21 PM PDT 24 Jul 10 06:21:28 PM PDT 24 2508020232 ps
T259 /workspace/coverage/default/4.sysrst_ctrl_sec_cm.856385549 Jul 10 06:21:05 PM PDT 24 Jul 10 06:21:20 PM PDT 24 22154972468 ps
T253 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1306243459 Jul 10 06:21:55 PM PDT 24 Jul 10 06:22:54 PM PDT 24 83718648533 ps
T142 /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.915123483 Jul 10 06:23:33 PM PDT 24 Jul 10 06:24:26 PM PDT 24 263680904541 ps
T442 /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.3015685796 Jul 10 06:23:41 PM PDT 24 Jul 10 06:23:51 PM PDT 24 2464048504 ps
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T445 /workspace/coverage/default/49.sysrst_ctrl_stress_all.370515678 Jul 10 06:24:09 PM PDT 24 Jul 10 06:24:18 PM PDT 24 6917171735 ps
T446 /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.3569952983 Jul 10 06:20:57 PM PDT 24 Jul 10 06:21:02 PM PDT 24 2616874441 ps
T447 /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.4008999682 Jul 10 06:21:52 PM PDT 24 Jul 10 06:21:59 PM PDT 24 2037734989 ps
T448 /workspace/coverage/default/46.sysrst_ctrl_alert_test.3154205839 Jul 10 06:24:03 PM PDT 24 Jul 10 06:24:13 PM PDT 24 2011777354 ps
T449 /workspace/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3997391042 Jul 10 06:23:09 PM PDT 24 Jul 10 06:23:17 PM PDT 24 7867172076 ps
T155 /workspace/coverage/default/45.sysrst_ctrl_edge_detect.1634747517 Jul 10 06:23:58 PM PDT 24 Jul 10 06:24:01 PM PDT 24 4135739622 ps
T450 /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2308865656 Jul 10 06:22:10 PM PDT 24 Jul 10 06:22:19 PM PDT 24 2508238439 ps
T206 /workspace/coverage/default/16.sysrst_ctrl_stress_all.739259774 Jul 10 06:22:13 PM PDT 24 Jul 10 06:23:38 PM PDT 24 168679316666 ps
T343 /workspace/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.3992971693 Jul 10 06:24:20 PM PDT 24 Jul 10 06:24:46 PM PDT 24 78661516952 ps
T451 /workspace/coverage/default/18.sysrst_ctrl_smoke.514823492 Jul 10 06:22:16 PM PDT 24 Jul 10 06:22:18 PM PDT 24 2162432693 ps
T320 /workspace/coverage/default/39.sysrst_ctrl_combo_detect.2711323634 Jul 10 06:23:41 PM PDT 24 Jul 10 06:28:57 PM PDT 24 150732648998 ps
T167 /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1085160529 Jul 10 06:21:05 PM PDT 24 Jul 10 06:22:03 PM PDT 24 23461274339 ps
T171 /workspace/coverage/default/14.sysrst_ctrl_stress_all.3811285888 Jul 10 06:22:11 PM PDT 24 Jul 10 06:22:31 PM PDT 24 10727847603 ps
T172 /workspace/coverage/default/49.sysrst_ctrl_smoke.2978380215 Jul 10 06:24:10 PM PDT 24 Jul 10 06:24:23 PM PDT 24 2116242304 ps
T173 /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.3864924394 Jul 10 06:23:28 PM PDT 24 Jul 10 06:23:31 PM PDT 24 2264430801 ps
T174 /workspace/coverage/default/23.sysrst_ctrl_stress_all.4134256564 Jul 10 06:22:41 PM PDT 24 Jul 10 06:22:47 PM PDT 24 14162130625 ps
T175 /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.464368858 Jul 10 06:22:59 PM PDT 24 Jul 10 06:23:06 PM PDT 24 2075119778 ps
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