Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2054

1

T14

39

T2

1

T4

5

auto[1]

590

1

T14

21

T2

2

T4

9

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2018

1

T14

60

T2

3

T4

9

auto[1]

626

1

T4

5

T12

11

T26

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1968

1

T14

53

T4

6

T12

8

auto[1]

676

1

T14

7

T2

3

T4

8

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2049

1

T14

50

T2

2

T4

10

auto[1]

595

1

T14

10

T2

1

T4

4

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2371

1

T14

50

T2

3

T4

14

auto[1]

273

1

T14

10

T26

1

T51

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2444

1

T14

53

T2

3

T4

14

auto[1]

200

1

T14

7

T26

4

T27

20

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2435

1

T14

60

T2

3

T4

14

auto[1]

209

1

T26

4

T27

20

T46

10

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2448

1

T14

25

T2

3

T4

14

auto[1]

196

1

T14

35

T26

1

T51

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2330

1

T14

60

T2

3

T4

14

auto[1]

314

1

T26

1

T51

3

T70

4

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2037

1

T14

29

T2

2

T4

7

auto[1]

607

1

T14

31

T2

1

T4

7

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	*	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

884

1

T2

3

T4

14

T12

19

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

103

1

T14

4

T183

9

T185

2

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

162

1

T279

9

T258

1

T386

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T253

3

T378

2

T310

7

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

47

1

T14

12

T185

2

T369

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

19

1

T51

2

T70

3

T387

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

18

1

T26

1

T183

3

T264

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

39

1

T261

2

T375

1

T388

6

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

22

1

T376

3

T389

2

T390

12

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

16

1

T183

2

T298

3

T391

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

12

1

T300

1

T392

2

T390

8

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

10

1

T309

2

T393

3

T394

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

2

1

T395

1

T396

1

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

9

1

T261

1

T109

3

T279

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

1

1

T397

1

-

-

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

37

1

T46

5

T261

3

T109

13

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

6

1

T376

1

T398

1

T399

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

8

1

T51

3

T177

1

T300

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

3

1

T398

1

T396

2

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

35

1

T14

2

T261

2

T279

7

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

3

1

T259

1

T400

2

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

11

1

T109

6

T259

5

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

34

1

T26

3

T27

14

T46

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T26

1

T185

1

T401

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

6

1

T402

6

-

-

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

4

1

T402

4

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

124

1

T14

6

T12

8

T26

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

153

1

T14

6

T26

1

T27

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

46

1

T4

6

T63

5

T271

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

73

1

T31

1

T261

2

T86

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

56

1

T32

4

T188

7

T109

13

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

58

1

T14

4

T48

6

T27

7

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

13

1

T375

1

T97

1

T303

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

144

1

T31

5

T109

6

T135

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

61

1

T2

2

T33

2

T51

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

68

1

T33

6

T30

4

T31

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T14

2

T31

1

T188

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

68

1

T271

4

T183

9

T277

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

26

1

T4

3

T261

3

T149

4

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

32

1

T2

1

T73

6

T188

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T137

1

T403

1

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

143

1

T32

10

T73

9

T70

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

62

1

T26

1

T261

1

T183

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

33

1

T30

6

T77

1

T149

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

37

1

T32

2

T185

2

T264

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

82

1

T31

2

T269

8

T404

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T266

3

T347

2

T367

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

18

1

T33

2

T271

1

T347

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T48

3

T135

4

T95

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

62

1

T4

4

T12

10

T253

3

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

18

1

T377

9

T305

3

T396

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

32

1

T32

2

T369

4

T135

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T96

2

T405

1

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

22

1

T31

1

T253

3

T368

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

21

1

T30

3

T271

1

T226

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

11

1

T4

1

T12

1

T48

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T93

4

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded