Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

998

1

T7

12

T18

9

T9

9

auto[1]

1080

1

T7

8

T18

11

T9

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

501

1

T7

4

T18

5

T9

4

from_0to1

487

1

T7

4

T18

5

T9

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T7

13

T18

11

T9

11

auto[1]

1024

1

T7

7

T18

9

T9

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1072

1

T7

9

T18

11

T9

9

auto[1]

1006

1

T7

11

T18

9

T9

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T18

1

T65

2

T41

2

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T41

1

T31

1

T414

2

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T9

1

T41

3

T83

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T18

1

T65

2

T41

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T7

1

T18

1

T83

2

auto[0]

from_0to1

auto[0]

auto[1]

43

1

T9

1

T41

1

T31

1

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T18

1

T41

4

T31

2

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T7

2

T9

1

T65

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T7

2

T18

1

T9

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T7

1

T9

1

T41

4

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T7

1

T18

1

T9

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T18

1

T41

2

T31

3

auto[1]

from_0to1

auto[0]

auto[0]

56

1

T18

1

T65

2

T41

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T7

1

T9

1

T41

3

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T18

1

T9

1

T65

2

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T18

1

T65

1

T41

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1010

1

T7

9

T18

11

T9

13

auto[1]

1068

1

T7

11

T18

9

T9

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

507

1

T7

6

T18

4

T9

7

from_0to1

512

1

T7

5

T18

4

T9

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T7

10

T18

6

T9

11

auto[1]

1046

1

T7

10

T18

14

T9

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T7

11

T18

7

T9

6

auto[1]

1024

1

T7

9

T18

13

T9

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T9

2

T65

1

T41

2

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T7

1

T9

1

T41

3

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T18

1

T41

3

T83

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T7

1

T18

1

T9

3

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T7

1

T41

4

T415

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T7

1

T9

2

T65

2

auto[0]

from_0to1

auto[1]

auto[0]

48

1

T7

1

T65

1

T415

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T18

1

T9

2

T41

3

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T7

2

T18

1

T9

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T7

1

T65

1

T41

2

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T41

2

T31

1

T414

2

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T7

1

T18

1

T65

1

auto[1]

from_0to1

auto[0]

auto[0]

71

1

T9

1

T83

1

T31

3

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T18

2

T9

1

T41

2

auto[1]

from_0to1

auto[1]

auto[0]

66

1

T7

1

T65

1

T41

3

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T7

1

T18

1

T9

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1034

1

T7

10

T18

6

T9

12

auto[1]

1044

1

T7

10

T18

14

T9

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

505

1

T7

4

T18

4

T9

6

from_0to1

500

1

T7

4

T18

5

T9

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1025

1

T7

12

T18

11

T9

6

auto[1]

1053

1

T7

8

T18

9

T9

14

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1050

1

T7

10

T18

9

T9

14

auto[1]

1028

1

T7

10

T18

11

T9

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T9

1

T65

1

T41

3

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T7

1

T41

1

T31

2

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T9

1

T65

1

T41

4

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T7

1

T18

1

T9

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T18

1

T65

1

T41

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T7

2

T41

3

T31

2

auto[0]

from_0to1

auto[1]

auto[0]

68

1

T9

2

T65

1

T41

3

auto[0]

from_0to1

auto[1]

auto[1]

71

1

T7

1

T18

1

T65

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T18

1

T9

1

T65

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T7

1

T18

1

T9

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T7

1

T41

1

T31

2

auto[1]

from_1to0

auto[1]

auto[1]

55

1

T18

1

T9

1

T41

2

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T18

2

T65

1

T83

1

auto[1]

from_0to1

auto[0]

auto[1]

47

1

T65

1

T41

1

T83

4

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T18

1

T9

2

T65

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T7

1

T9

1

T41

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1053

1

T7

14

T18

13

T9

10

auto[1]

1025

1

T7

6

T18

7

T9

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

498

1

T7

5

T18

6

T9

4

from_0to1

502

1

T7

4

T18

6

T9

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T7

15

T18

8

T9

11

auto[1]

1011

1

T7

5

T18

12

T9

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T7

10

T18

12

T9

9

auto[1]

1046

1

T7

10

T18

8

T9

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T18

2

T9

1

T41

1

auto[0]

from_1to0

auto[0]

auto[1]

59

1

T7

3

T18

1

T41

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T7

1

T18

1

T65

2

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T18

1

T9

1

T65

1

auto[0]

from_0to1

auto[0]

auto[0]

53

1

T18

1

T65

1

T41

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T41

1

T31

2

T80

2

auto[0]

from_0to1

auto[1]

auto[0]

75

1

T18

1

T9

1

T65

2

auto[0]

from_0to1

auto[1]

auto[1]

59

1

T7

1

T18

1

T65

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T18

1

T9

1

T65

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T7

1

T65

2

T41

2

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T9

1

T41

2

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T41

1

T83

1

T31

2

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T7

1

T18

1

T9

2

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T65

2

T31

1

T415

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T7

2

T18

1

T41

2

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T18

1

T9

1

T65

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T7

12

T18

11

T9

11

auto[1]

1024

1

T7

8

T18

9

T9

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

496

1

T7

4

T18

4

T9

5

from_0to1

499

1

T7

4

T18

5

T9

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1032

1

T7

9

T18

9

T9

8

auto[1]

1046

1

T7

11

T18

11

T9

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1044

1

T7

14

T18

11

T9

7

auto[1]

1034

1

T7

6

T18

9

T9

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T41

1

T415

2

T414

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T18

2

T65

1

T41

2

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T7

4

T9

1

T65

2

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T9

1

T41

1

T83

1

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T18

1

T9

1

T65

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T7

1

T18

1

T41

2

auto[0]

from_0to1

auto[1]

auto[0]

58

1

T18

1

T65

1

T41

3

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T7

1

T18

2

T65

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T18

1

T65

1

T41

2

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T18

1

T41

4

T83

2

auto[1]

from_1to0

auto[1]

auto[0]

54

1

T65

1

T41

3

T31

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T9

3

T41

1

T83

2

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T9

1

T65

1

T41

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T7

1

T83

2

T216

2

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T7

1

T9

1

T41

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T9

2

T41

4

T416

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027

1

T7

8

T18

9

T9

10

auto[1]

1051

1

T7

12

T18

11

T9

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

495

1

T7

5

T18

3

T9

5

from_0to1

491

1

T7

6

T18

2

T9

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1047

1

T7

8

T18

10

T9

13

auto[1]

1031

1

T7

12

T18

10

T9

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1030

1

T7

11

T18

12

T9

7

auto[1]

1048

1

T7

9

T18

8

T9

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T41

1

T83

1

T31

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T7

2

T18

1

T9

2

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T41

2

T31

1

T80

2

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T41

4

T31

2

T216

1

auto[0]

from_0to1

auto[0]

auto[0]

48

1

T414

1

T340

2

T417

1

auto[0]

from_0to1

auto[0]

auto[1]

74

1

T65

1

T41

3

T31

1

auto[0]

from_0to1

auto[1]

auto[0]

46

1

T7

1

T18

1

T41

5

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T7

1

T65

1

T41

4

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T7

1

T9

1

T65

3

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T18

2

T9

1

T65

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T7

1

T41

2

T83

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T7

1

T9

1

T65

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T7

1

T65

1

T41

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T7

1

T9

2

T65

2

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T7

1

T9

1

T65

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T7

1

T18

1

T9

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1042

1

T7

9

T18

13

T9

9

auto[1]

1036

1

T7

11

T18

7

T9

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

487

1

T7

4

T18

3

T9

4

from_0to1

481

1

T7

4

T18

2

T9

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1049

1

T7

11

T18

11

T9

7

auto[1]

1029

1

T7

9

T18

9

T9

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1005

1

T7

11

T18

8

T9

12

auto[1]

1073

1

T7

9

T18

12

T9

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T41

2

T31

2

T414

2

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T18

1

T65

1

T83

2

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T65

1

T41

2

T415

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T7

1

T18

1

T9

2

auto[0]

from_0to1

auto[0]

auto[0]

49

1

T7

2

T65

3

T83

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T7

1

T18

1

T41

3

auto[0]

from_0to1

auto[1]

auto[0]

54

1

T7

1

T18

1

T65

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T9

1

T65

1

T41

2

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T7

1

T41

2

T31

3

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T18

1

T65

1

T41

2

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T7

1

T9

1

T65

1

auto[1]

from_1to0

auto[1]

auto[1]

50

1

T7

1

T9

1

T65

2

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T65

1

T41

2

T83

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T41

3

T31

2

T416

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T9

2

T41

1

T83

1

auto[1]

from_0to1

auto[1]

auto[1]

62

1

T41

1

T83

1

T31

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1027

1

T7

8

T18

8

T9

11

auto[1]

1051

1

T7

12

T18

12

T9

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

515

1

T7

6

T18

3

T9

6

from_0to1

511

1

T7

6

T18

3

T9

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1078

1

T7

8

T18

9

T9

13

auto[1]

1000

1

T7

12

T18

11

T9

7

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T7

10

T18

11

T9

11

auto[1]

1010

1

T7

10

T18

9

T9

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T9

1

T41

1

T83

1

auto[0]

from_1to0

auto[0]

auto[1]

66

1

T41

5

T414

2

T416

1

auto[0]

from_1to0

auto[1]

auto[0]

64

1

T7

1

T41

2

T83

1

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T7

1

T9

2

T65

2

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T7

1

T18

1

T65

1

auto[0]

from_0to1

auto[0]

auto[1]

57

1

T7

1

T9

2

T41

2

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T7

1

T41

2

T83

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T7

1

T18

1

T9

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T7

1

T18

1

T9

2

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T9

1

T65

1

T41

2

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T41

1

T31

1

T414

1

auto[1]

from_1to0

auto[1]

auto[1]

54

1

T7

3

T18

2

T414

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T9

1

T65

1

T41

1

auto[1]

from_0to1

auto[0]

auto[1]

79

1

T7

2

T9

1

T65

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T41

3

T415

3

T414

1

auto[1]

from_0to1

auto[1]

auto[1]

56

1

T18

1

T41

2

T83

1