Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	160379	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

124973

1

T5

12

T7

37

T20

28

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	147688	1			T5	2		T6	2		T7	62
values[0x0]	68238	1			T5	27		T7	28		T20	1
values[0x1]	69426	1			T5	33		T7	32		T1	126

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	129841	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

155511

1

T5

20

T7

50

T20

33

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1230	1			T5	3		T7	1		T1	1
valid_sources[0x01]	1184	1			T7	1		T1	5		T14	3
valid_sources[0x02]	1010	1			T1	2		T14	2		T12	1
valid_sources[0x03]	1161	1			T1	3		T14	1		T2	2
valid_sources[0x04]	1849	1			T1	5		T14	9		T9	1
valid_sources[0x05]	1018	1			T7	2		T1	1		T14	6
valid_sources[0x06]	1018	1			T1	3		T14	4		T2	2
valid_sources[0x07]	920	1			T1	3		T14	6		T2	5
valid_sources[0x08]	814	1			T5	2		T1	4		T14	7
valid_sources[0x09]	1036	1			T1	6		T14	3		T2	5
valid_sources[0x0a]	1129	1			T1	2		T14	3		T2	3
valid_sources[0x0b]	1002	1			T14	3		T2	3		T9	1
valid_sources[0x0c]	1176	1			T7	2		T1	6		T14	8
valid_sources[0x0d]	1028	1			T1	3		T14	1		T2	1
valid_sources[0x0e]	1201	1			T1	3		T14	8		T2	1
valid_sources[0x0f]	877	1			T1	3		T14	7		T2	1
valid_sources[0x10]	999	1			T1	3		T14	6		T18	122
valid_sources[0x11]	928	1			T7	1		T1	1		T14	6
valid_sources[0x12]	973	1			T7	2		T1	4		T14	6
valid_sources[0x13]	1378	1			T1	5		T14	3		T2	6
valid_sources[0x14]	938	1			T1	3		T14	2		T2	5
valid_sources[0x15]	1415	1			T1	3		T14	1		T2	4
valid_sources[0x16]	861	1			T1	2		T14	3		T2	3
valid_sources[0x17]	700	1			T1	5		T14	4		T2	1
valid_sources[0x18]	1287	1			T1	1		T14	6		T2	4
valid_sources[0x19]	879	1			T7	1		T1	2		T14	7
valid_sources[0x1a]	996	1			T1	4		T14	3		T15	2
valid_sources[0x1b]	971	1			T1	2		T14	4		T9	1
valid_sources[0x1c]	1033	1			T1	5		T14	7		T2	2
valid_sources[0x1d]	1116	1			T20	3		T14	8		T2	1
valid_sources[0x1e]	778	1			T7	2		T14	4		T9	1
valid_sources[0x1f]	716	1			T7	2		T1	1		T14	2
valid_sources[0x20]	832	1			T1	2		T14	11		T2	1
valid_sources[0x21]	2986	1			T7	1		T1	4		T14	6
valid_sources[0x22]	888	1			T1	3		T14	3		T2	3
valid_sources[0x23]	1072	1			T1	2		T14	7		T2	2
valid_sources[0x24]	1355	1			T7	1		T1	5		T14	9
valid_sources[0x25]	1154	1			T1	1		T14	4		T2	2
valid_sources[0x26]	844	1			T1	5		T14	2		T2	1
valid_sources[0x27]	906	1			T1	4		T14	4		T2	4
valid_sources[0x28]	1946	1			T1	5		T14	2		T9	2
valid_sources[0x29]	710	1			T7	1		T1	2		T14	9
valid_sources[0x2a]	869	1			T1	2		T14	3		T2	1
valid_sources[0x2b]	1210	1			T7	9		T1	5		T14	2
valid_sources[0x2c]	732	1			T1	5		T14	4		T2	1
valid_sources[0x2d]	930	1			T1	2		T14	3		T2	4
valid_sources[0x2e]	998	1			T7	4		T20	3		T1	1
valid_sources[0x2f]	1149	1			T1	3		T14	5		T2	4
valid_sources[0x30]	846	1			T5	3		T7	1		T1	6
valid_sources[0x31]	872	1			T1	4		T14	5		T2	2
valid_sources[0x32]	1059	1			T1	2		T14	3		T65	1
valid_sources[0x33]	1001	1			T1	2		T14	8		T2	2
valid_sources[0x34]	794	1			T1	2		T14	3		T2	1
valid_sources[0x35]	950	1			T20	2		T1	5		T14	4
valid_sources[0x36]	824	1			T7	1		T1	2		T14	1
valid_sources[0x37]	688	1			T1	1		T2	1		T12	7
valid_sources[0x38]	874	1			T20	1		T1	5		T14	1
valid_sources[0x39]	1008	1			T7	1		T1	2		T14	5
valid_sources[0x3a]	1133	1			T1	4		T14	3		T2	1
valid_sources[0x3b]	933	1			T5	10		T20	3		T1	2
valid_sources[0x3c]	951	1			T7	3		T1	2		T2	3
valid_sources[0x3d]	1112	1			T1	4		T14	5		T2	1
valid_sources[0x3e]	872	1			T1	3		T14	11		T26	1
valid_sources[0x3f]	1215	1			T1	2		T14	5		T2	2
valid_sources[0x40]	1277	1			T7	1		T1	2		T14	3
valid_sources[0x41]	1728	1			T7	2		T14	1		T12	13
valid_sources[0x42]	846	1			T20	1		T1	4		T14	4
valid_sources[0x43]	795	1			T1	3		T14	5		T2	2
valid_sources[0x44]	854	1			T1	1		T14	4		T2	1
valid_sources[0x45]	1040	1			T20	3		T1	1		T14	3
valid_sources[0x46]	781	1			T7	1		T1	6		T14	4
valid_sources[0x47]	2111	1			T1	2		T14	3		T2	3
valid_sources[0x48]	963	1			T1	1		T14	4		T9	2
valid_sources[0x49]	835	1			T1	2		T14	2		T9	1
valid_sources[0x4a]	989	1			T1	1		T14	2		T9	1
valid_sources[0x4b]	830	1			T1	2		T14	4		T9	1
valid_sources[0x4c]	925	1			T1	2		T14	4		T2	1
valid_sources[0x4d]	1395	1			T20	2		T1	5		T14	10
valid_sources[0x4e]	892	1			T5	3		T1	4		T14	1
valid_sources[0x4f]	809	1			T7	2		T1	3		T14	2
valid_sources[0x50]	974	1			T7	4		T1	5		T14	6
valid_sources[0x51]	2307	1			T7	2		T1	3		T14	7
valid_sources[0x52]	1108	1			T1	6		T14	3		T26	4
valid_sources[0x53]	1026	1			T5	2		T1	1		T14	7
valid_sources[0x54]	924	1			T1	3		T14	10		T9	1
valid_sources[0x55]	1164	1			T7	1		T1	3		T14	6
valid_sources[0x56]	1088	1			T7	1		T1	3		T14	4
valid_sources[0x57]	936	1			T14	7		T2	1		T9	1
valid_sources[0x58]	853	1			T1	3		T14	6		T2	1
valid_sources[0x59]	1102	1			T5	1		T20	1		T1	5
valid_sources[0x5a]	928	1			T1	9		T14	7		T9	1
valid_sources[0x5b]	1596	1			T1	3		T14	6		T26	1
valid_sources[0x5c]	895	1			T1	2		T14	4		T9	1
valid_sources[0x5d]	974	1			T1	1		T14	5		T2	1
valid_sources[0x5e]	876	1			T1	2		T14	1		T65	2
valid_sources[0x5f]	1239	1			T20	1		T1	2		T14	5
valid_sources[0x60]	1721	1			T7	1		T20	2		T1	2
valid_sources[0x61]	771	1			T20	4		T1	2		T14	4
valid_sources[0x62]	1066	1			T7	1		T1	2		T14	1
valid_sources[0x63]	1051	1			T7	1		T14	4		T2	3
valid_sources[0x64]	855	1			T1	5		T14	4		T2	1
valid_sources[0x65]	791	1			T5	2		T1	1		T14	4
valid_sources[0x66]	1037	1			T1	2		T14	3		T2	4
valid_sources[0x67]	842	1			T7	3		T1	3		T14	7
valid_sources[0x68]	1001	1			T1	3		T14	4		T9	2
valid_sources[0x69]	865	1			T1	2		T14	4		T2	4
valid_sources[0x6a]	1705	1			T20	1		T1	6		T14	5
valid_sources[0x6b]	786	1			T14	4		T2	4		T9	2
valid_sources[0x6c]	1244	1			T1	1		T14	2		T2	2
valid_sources[0x6d]	952	1			T1	3		T14	1		T2	2
valid_sources[0x6e]	957	1			T1	1		T14	2		T2	1
valid_sources[0x6f]	929	1			T7	2		T1	3		T14	3
valid_sources[0x70]	892	1			T1	1		T14	3		T2	2
valid_sources[0x71]	896	1			T1	2		T14	7		T2	2
valid_sources[0x72]	1131	1			T7	1		T1	3		T14	1
valid_sources[0x73]	917	1			T7	1		T1	4		T14	5
valid_sources[0x74]	1275	1			T7	1		T1	6		T14	3
valid_sources[0x75]	809	1			T1	3		T14	7		T2	2
valid_sources[0x76]	944	1			T20	1		T1	1		T14	9
valid_sources[0x77]	1482	1			T1	3		T14	1		T2	1
valid_sources[0x78]	833	1			T1	4		T14	3		T2	1
valid_sources[0x79]	877	1			T7	1		T1	3		T14	12
valid_sources[0x7a]	983	1			T1	2		T14	2		T2	2
valid_sources[0x7b]	964	1			T7	2		T1	3		T2	3
valid_sources[0x7c]	942	1			T1	4		T14	3		T2	2
valid_sources[0x7d]	1549	1			T5	2		T7	1		T1	4
valid_sources[0x7e]	780	1			T1	2		T14	5		T2	1
valid_sources[0x7f]	1400	1			T1	4		T14	3		T2	1
valid_sources[0x80]	991	1			T20	1		T1	2		T14	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

67451

1

T5

1

T7

22

T20

27

values[0x0]

all_enables

biggest_size

33532

1

T5

8

T7

9

T20

1

values[0x1]

all_enables

biggest_size

23990

1

T5

3

T7

6

T1

40