Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T7,T20
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T9,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T9,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T9,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T47
1	0	Covered	T5,T6,T7
1	1	Covered	T2,T9,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T47
0	1	Covered	T85,T89,T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T47
0	1	Covered	T2,T9,T47
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T47
1	-	Covered	T2,T9,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T47
DetectSt	168	Covered	T2,T9,T47
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T9,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T47
DebounceSt->IdleSt	163	Covered	T31,T53,T80
DetectSt->IdleSt	186	Covered	T85,T89,T90
DetectSt->StableSt	191	Covered	T2,T9,T47
IdleSt->DebounceSt	148	Covered	T2,T9,T47
StableSt->IdleSt	206	Covered	T2,T9,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T47
0	1	Covered	T2,T9,T47
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T47
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T47
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T31,T77,T114
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T47
DetectSt	-	-	-	-	1	-	-	Covered	T85,T89,T90
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T47
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	319	0	0
CntIncr_A	7194251	190039	0	0
CntNoWrap_A	7194251	6507453	0	0
DetectStDropOut_A	7194251	5	0	0
DetectedOut_A	7194251	977	0	0
DetectedPulseOut_A	7194251	147	0	0
DisabledIdleSt_A	7194251	6310329	0	0
DisabledNoDetection_A	7194251	6312751	0	0
EnterDebounceSt_A	7194251	174	0	0
EnterDetectSt_A	7194251	152	0	0
EnterStableSt_A	7194251	147	0	0
PulseIsPulse_A	7194251	147	0	0
StayInStableSt	7194251	830	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7194251	6983	0	0
gen_low_level_sva.LowLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	147	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	319	0	0
T2	8283	6	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	4	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	5	0	0
T39	0	2	0	0
T47	0	6	0	0
T49	0	2	0	0
T50	0	4	0	0
T52	0	6	0	0
T53	0	1	0	0
T81	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	190039	0	0
T2	8283	124	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	123	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	117	0	0
T39	0	65	0	0
T47	0	118	0	0
T49	0	60	0	0
T50	0	106	0	0
T52	0	139	0	0
T53	0	10	0	0
T81	0	11	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507453	0	0
T1	10715	2574	0	0
T2	8283	3692	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	5	0	0
T85	587	1	0	0
T89	0	1	0	0
T90	0	1	0	0
T92	0	1	0	0
T97	0	1	0	0
T101	716	0	0	0
T102	527	0	0	0
T103	728	0	0	0
T104	503	0	0	0
T105	423	0	0	0
T106	420	0	0	0
T107	408	0	0	0
T108	491	0	0	0
T109	42213	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	977	0	0
T2	8283	23	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	7	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	8	0	0
T39	0	9	0	0
T47	0	16	0	0
T49	0	7	0	0
T50	0	6	0	0
T52	0	14	0	0
T80	0	8	0	0
T81	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	147	0	0
T2	8283	3	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	2	0	0
T39	0	1	0	0
T47	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T52	0	3	0	0
T80	0	3	0	0
T81	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6310329	0	0
T1	10715	2574	0	0
T2	8283	3451	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6312751	0	0
T1	10715	2598	0	0
T2	8283	3463	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	174	0	0
T2	8283	3	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	3	0	0
T39	0	1	0	0
T47	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T52	0	3	0	0
T53	0	1	0	0
T81	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	152	0	0
T2	8283	3	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	2	0	0
T39	0	1	0	0
T47	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T52	0	3	0	0
T80	0	3	0	0
T81	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	147	0	0
T2	8283	3	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	2	0	0
T39	0	1	0	0
T47	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T52	0	3	0	0
T80	0	3	0	0
T81	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	147	0	0
T2	8283	3	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	2	0	0
T39	0	1	0	0
T47	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T52	0	3	0	0
T80	0	3	0	0
T81	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	830	0	0
T2	8283	20	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	5	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	6	0	0
T39	0	8	0	0
T47	0	13	0	0
T49	0	6	0	0
T50	0	4	0	0
T52	0	11	0	0
T80	0	5	0	0
T81	0	2	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6983	0	0
T1	10715	43	0	0
T2	8283	26	0	0
T3	2437	10	0	0
T4	0	14	0	0
T5	526	4	0	0
T6	8487	0	0	0
T7	503	5	0	0
T14	25334	35	0	0
T15	424	4	0	0
T16	422	0	0	0
T18	0	4	0	0
T20	451	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	147	0	0
T2	8283	3	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	2	0	0
T39	0	1	0	0
T47	0	3	0	0
T49	0	1	0	0
T50	0	2	0	0
T52	0	3	0	0
T80	0	3	0	0
T81	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T7,T20
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T3,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T3,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T3,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T10
1	0	Covered	T5,T6,T7
1	1	Covered	T3,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T10
0	1	Covered	T58,T80,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T10
0	1	Unreachable
1	0	Covered	T3,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T10
DetectSt	168	Covered	T3,T8,T10
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T3,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T10
DebounceSt->IdleSt	163	Covered	T11,T53,T72
DetectSt->IdleSt	186	Covered	T58,T80,T79
DetectSt->StableSt	191	Covered	T3,T8,T10
IdleSt->DebounceSt	148	Covered	T3,T8,T10
StableSt->IdleSt	206	Covered	T3,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T10
0	1	Covered	T3,T8,T10
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T10
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T72,T37
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T58,T80,T79
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	219	0	0
CntIncr_A	7194251	284000	0	0
CntNoWrap_A	7194251	6507553	0	0
DetectStDropOut_A	7194251	19	0	0
DetectedOut_A	7194251	128023	0	0
DetectedPulseOut_A	7194251	58	0	0
DisabledIdleSt_A	7194251	5501925	0	0
DisabledNoDetection_A	7194251	5504412	0	0
EnterDebounceSt_A	7194251	142	0	0
EnterDetectSt_A	7194251	77	0	0
EnterStableSt_A	7194251	58	0	0
PulseIsPulse_A	7194251	58	0	0
StayInStableSt	7194251	127965	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7194251	6983	0	0
gen_low_level_sva.LowLevelEvent_A	7194251	6510260	0	0
gen_sticky_sva.StableStDropOut_A	7194251	326021	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	219	0	0
T3	2437	4	0	0
T4	21648	0	0	0
T8	1409	2	0	0
T9	4783	0	0	0
T10	1525	2	0	0
T11	1039	6	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	2	0	0
T53	0	2	0	0
T56	0	4	0	0
T58	0	4	0	0
T71	0	2	0	0
T72	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	284000	0	0
T3	2437	166	0	0
T4	21648	0	0	0
T8	1409	66	0	0
T9	4783	0	0	0
T10	1525	73	0	0
T11	1039	192	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	98	0	0
T53	0	12	0	0
T56	0	134	0	0
T58	0	74	0	0
T71	0	100	0	0
T72	0	276	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507553	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2032	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	19	0	0
T31	37784	0	0	0
T37	0	2	0	0
T45	6346	0	0	0
T51	18684	0	0	0
T58	807	1	0	0
T79	0	1	0	0
T80	0	2	0	0
T115	0	1	0	0
T116	0	4	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	2	0	0
T121	405	0	0	0
T122	521	0	0	0
T123	484	0	0	0
T124	402	0	0	0
T125	426	0	0	0
T126	432	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	128023	0	0
T3	2437	458	0	0
T4	21648	0	0	0
T8	1409	396	0	0
T9	4783	0	0	0
T10	1525	149	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	78	0	0
T56	0	81	0	0
T58	0	78	0	0
T71	0	415	0	0
T72	0	187	0	0
T79	0	292	0	0
T112	0	59	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	58	0	0
T3	2437	2	0	0
T4	21648	0	0	0
T8	1409	1	0	0
T9	4783	0	0	0
T10	1525	1	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T56	0	2	0	0
T58	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T79	0	2	0	0
T112	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	5501925	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	1014	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	5504412	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	1015	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	142	0	0
T3	2437	2	0	0
T4	21648	0	0	0
T8	1409	1	0	0
T9	4783	0	0	0
T10	1525	1	0	0
T11	1039	6	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T53	0	2	0	0
T56	0	2	0	0
T58	0	2	0	0
T71	0	1	0	0
T72	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	77	0	0
T3	2437	2	0	0
T4	21648	0	0	0
T8	1409	1	0	0
T9	4783	0	0	0
T10	1525	1	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T56	0	2	0	0
T58	0	2	0	0
T71	0	1	0	0
T72	0	1	0	0
T80	0	2	0	0
T112	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	58	0	0
T3	2437	2	0	0
T4	21648	0	0	0
T8	1409	1	0	0
T9	4783	0	0	0
T10	1525	1	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T56	0	2	0	0
T58	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T79	0	2	0	0
T112	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	58	0	0
T3	2437	2	0	0
T4	21648	0	0	0
T8	1409	1	0	0
T9	4783	0	0	0
T10	1525	1	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T56	0	2	0	0
T58	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T79	0	2	0	0
T112	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	127965	0	0
T3	2437	456	0	0
T4	21648	0	0	0
T8	1409	395	0	0
T9	4783	0	0	0
T10	1525	148	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	77	0	0
T56	0	79	0	0
T58	0	77	0	0
T71	0	414	0	0
T72	0	186	0	0
T79	0	290	0	0
T112	0	58	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6983	0	0
T1	10715	43	0	0
T2	8283	26	0	0
T3	2437	10	0	0
T4	0	14	0	0
T5	526	4	0	0
T6	8487	0	0	0
T7	503	5	0	0
T14	25334	35	0	0
T15	424	4	0	0
T16	422	0	0	0
T18	0	4	0	0
T20	451	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	326021	0	0
T3	2437	362	0	0
T4	21648	0	0	0
T8	1409	80	0	0
T9	4783	0	0	0
T10	1525	96	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	30	0	0
T56	0	172	0	0
T58	0	149	0	0
T71	0	551	0	0
T72	0	126837	0	0
T79	0	134	0	0
T112	0	35	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T7,T20

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T7,T20
1	1	Covered	T5,T7,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T3,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T3,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T3,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T10
1	0	Covered	T5,T7,T20
1	1	Covered	T3,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T56
0	1	Covered	T8,T56,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T56
0	1	Unreachable
1	0	Covered	T3,T11,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T10
DetectSt	168	Covered	T3,T8,T11
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T3,T11,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T11
DebounceSt->IdleSt	163	Covered	T8,T10,T56
DetectSt->IdleSt	186	Covered	T8,T56,T79
DetectSt->StableSt	191	Covered	T3,T11,T56
IdleSt->DebounceSt	148	Covered	T3,T8,T10
StableSt->IdleSt	206	Covered	T3,T11,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T10
0	1	Covered	T3,T8,T10
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T11
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T7,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T10,T56
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T8,T56,T79
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T56
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	204	0	0
CntIncr_A	7194251	308557	0	0
CntNoWrap_A	7194251	6507568	0	0
DetectStDropOut_A	7194251	16	0	0
DetectedOut_A	7194251	221559	0	0
DetectedPulseOut_A	7194251	59	0	0
DisabledIdleSt_A	7194251	5501925	0	0
DisabledNoDetection_A	7194251	5504412	0	0
EnterDebounceSt_A	7194251	129	0	0
EnterDetectSt_A	7194251	75	0	0
EnterStableSt_A	7194251	59	0	0
PulseIsPulse_A	7194251	59	0	0
StayInStableSt	7194251	221500	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_sticky_sva.StableStDropOut_A	7194251	168499	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	204	0	0
T3	2437	4	0	0
T4	21648	0	0	0
T8	1409	5	0	0
T9	4783	0	0	0
T10	1525	3	0	0
T11	1039	6	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	2	0	0
T53	0	2	0	0
T56	0	5	0	0
T58	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	308557	0	0
T3	2437	50	0	0
T4	21648	0	0	0
T8	1409	80	0	0
T9	4783	0	0	0
T10	1525	243	0	0
T11	1039	57	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	37	0	0
T53	0	13	0	0
T56	0	123	0	0
T58	0	32	0	0
T71	0	75	0	0
T72	0	41900	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507568	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2032	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	16	0	0
T8	1409	1	0	0
T9	4783	0	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T56	0	1	0	0
T65	503	0	0	0
T79	0	1	0	0
T98	450	0	0	0
T99	442	0	0	0
T116	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	0	3	0	0
T130	0	1	0	0
T131	0	2	0	0
T132	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	221559	0	0
T3	2437	154	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T10	1525	0	0	0
T11	1039	104	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	34	0	0
T56	0	1	0	0
T58	0	125	0	0
T71	0	339	0	0
T72	0	169866	0	0
T79	0	181	0	0
T80	0	149	0	0
T112	0	48	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	59	0	0
T3	2437	2	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T10	1525	0	0	0
T11	1039	3	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T112	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	5501925	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	1014	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	5504412	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	1015	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	129	0	0
T3	2437	2	0	0
T4	21648	0	0	0
T8	1409	4	0	0
T9	4783	0	0	0
T10	1525	3	0	0
T11	1039	3	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T53	0	2	0	0
T56	0	3	0	0
T58	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	75	0	0
T3	2437	2	0	0
T4	21648	0	0	0
T8	1409	1	0	0
T9	4783	0	0	0
T10	1525	0	0	0
T11	1039	3	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T56	0	2	0	0
T58	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T80	0	1	0	0
T112	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	59	0	0
T3	2437	2	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T10	1525	0	0	0
T11	1039	3	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T112	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	59	0	0
T3	2437	2	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T10	1525	0	0	0
T11	1039	3	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T56	0	1	0	0
T58	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0
T79	0	1	0	0
T80	0	1	0	0
T112	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	221500	0	0
T3	2437	152	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T10	1525	0	0	0
T11	1039	101	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	33	0	0
T58	0	124	0	0
T71	0	338	0	0
T72	0	169865	0	0
T79	0	180	0	0
T80	0	148	0	0
T112	0	47	0	0
T113	0	143	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	168499	0	0
T3	2437	786	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T10	1525	0	0	0
T11	1039	353	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	135	0	0
T56	0	148	0	0
T58	0	198	0	0
T71	0	661	0	0
T72	0	96	0	0
T79	0	161	0	0
T80	0	33	0	0
T112	0	81	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T7,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T3,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T3,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T8,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T10
1	0	Covered	T5,T7,T20
1	1	Covered	T3,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T11
0	1	Covered	T8,T37,T77
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T10,T11
0	1	Unreachable
1	0	Covered	T8,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T10
DetectSt	168	Covered	T8,T10,T11
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T8,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T10,T11
DebounceSt->IdleSt	163	Covered	T3,T58,T53
DetectSt->IdleSt	186	Covered	T8,T37,T77
DetectSt->StableSt	191	Covered	T8,T10,T11
IdleSt->DebounceSt	148	Covered	T3,T8,T10
StableSt->IdleSt	206	Covered	T8,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T10
0	1	Covered	T3,T8,T10
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T10,T11
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T7,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T58,T71
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T8,T37,T77
DetectSt	-	-	-	-	0	1	-	Covered	T8,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T8,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	217	0	0
CntIncr_A	7194251	30289	0	0
CntNoWrap_A	7194251	6507555	0	0
DetectStDropOut_A	7194251	20	0	0
DetectedOut_A	7194251	10594	0	0
DetectedPulseOut_A	7194251	61	0	0
DisabledIdleSt_A	7194251	5501925	0	0
DisabledNoDetection_A	7194251	5504412	0	0
EnterDebounceSt_A	7194251	136	0	0
EnterDetectSt_A	7194251	81	0	0
EnterStableSt_A	7194251	61	0	0
PulseIsPulse_A	7194251	61	0	0
StayInStableSt	7194251	10533	0	0
gen_high_event_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_sticky_sva.StableStDropOut_A	7194251	626931	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	217	0	0
T3	2437	5	0	0
T4	21648	0	0	0
T8	1409	4	0	0
T9	4783	0	0	0
T10	1525	2	0	0
T11	1039	6	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	2	0	0
T53	0	2	0	0
T56	0	4	0	0
T58	0	4	0	0
T71	0	5	0	0
T72	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	30289	0	0
T3	2437	285	0	0
T4	21648	0	0	0
T8	1409	54	0	0
T9	4783	0	0	0
T10	1525	17	0	0
T11	1039	129	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	28	0	0
T53	0	11	0	0
T56	0	198	0	0
T58	0	124	0	0
T71	0	470	0	0
T72	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507555	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2031	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	20	0	0
T8	1409	1	0	0
T9	4783	0	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T37	0	1	0	0
T65	503	0	0	0
T77	0	3	0	0
T96	0	2	0	0
T98	450	0	0	0
T99	442	0	0	0
T116	0	1	0	0
T128	0	1	0	0
T133	0	2	0	0
T134	0	1	0	0
T135	0	4	0	0
T136	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	10594	0	0
T8	1409	58	0	0
T9	4783	0	0	0
T10	1525	44	0	0
T11	1039	239	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T31	0	10	0	0
T37	0	96	0	0
T56	0	314	0	0
T65	503	0	0	0
T72	0	248	0	0
T79	0	371	0	0
T80	0	113	0	0
T98	450	0	0	0
T99	442	0	0	0
T113	0	77	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	61	0	0
T8	1409	1	0	0
T9	4783	0	0	0
T10	1525	1	0	0
T11	1039	3	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T31	0	1	0	0
T37	0	1	0	0
T56	0	2	0	0
T65	503	0	0	0
T72	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0
T98	450	0	0	0
T99	442	0	0	0
T113	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	5501925	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	1014	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	5504412	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	1015	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	136	0	0
T3	2437	5	0	0
T4	21648	0	0	0
T8	1409	2	0	0
T9	4783	0	0	0
T10	1525	1	0	0
T11	1039	3	0	0
T12	28453	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T53	0	2	0	0
T56	0	2	0	0
T58	0	4	0	0
T71	0	5	0	0
T72	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	81	0	0
T8	1409	2	0	0
T9	4783	0	0	0
T10	1525	1	0	0
T11	1039	3	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T31	0	1	0	0
T37	0	2	0	0
T56	0	2	0	0
T65	503	0	0	0
T72	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0
T98	450	0	0	0
T99	442	0	0	0
T113	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	61	0	0
T8	1409	1	0	0
T9	4783	0	0	0
T10	1525	1	0	0
T11	1039	3	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T31	0	1	0	0
T37	0	1	0	0
T56	0	2	0	0
T65	503	0	0	0
T72	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0
T98	450	0	0	0
T99	442	0	0	0
T113	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	61	0	0
T8	1409	1	0	0
T9	4783	0	0	0
T10	1525	1	0	0
T11	1039	3	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T31	0	1	0	0
T37	0	1	0	0
T56	0	2	0	0
T65	503	0	0	0
T72	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0
T98	450	0	0	0
T99	442	0	0	0
T113	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	10533	0	0
T8	1409	57	0	0
T9	4783	0	0	0
T10	1525	43	0	0
T11	1039	236	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T31	0	9	0	0
T37	0	95	0	0
T56	0	312	0	0
T65	503	0	0	0
T72	0	247	0	0
T79	0	369	0	0
T80	0	112	0	0
T98	450	0	0	0
T99	442	0	0	0
T113	0	76	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	626931	0	0
T8	1409	333	0	0
T9	4783	0	0	0
T10	1525	266	0	0
T11	1039	169	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T31	0	185	0	0
T37	0	38	0	0
T56	0	56	0	0
T65	503	0	0	0
T72	0	211569	0	0
T79	0	208	0	0
T80	0	143	0	0
T98	450	0	0	0
T99	442	0	0	0
T113	0	177	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T36,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T36,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T36,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T40,T41,T36
1	0	Covered	T5,T6,T7
1	1	Covered	T36,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T34,T35
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T34,T35
0	1	Covered	T36,T34,T75
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T34,T35
1	-	Covered	T36,T34,T75

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T34,T35
DetectSt	168	Covered	T36,T34,T35
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T36,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T34,T35
DebounceSt->IdleSt	163	Covered	T53,T37,T74
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T36,T34,T35
IdleSt->DebounceSt	148	Covered	T36,T34,T35
StableSt->IdleSt	206	Covered	T36,T34,T75

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T34,T35
0	1	Covered	T36,T34,T35
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T34,T35
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T118,T137
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T34,T35
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T36,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T34,T75
StableSt	-	-	-	-	-	-	0	Covered	T36,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	88	0	0
CntIncr_A	7194251	50412	0	0
CntNoWrap_A	7194251	6507684	0	0
DetectStDropOut_A	7194251	0	0	0
DetectedOut_A	7194251	3277	0	0
DetectedPulseOut_A	7194251	42	0	0
DisabledIdleSt_A	7194251	6261778	0	0
DisabledNoDetection_A	7194251	6264208	0	0
EnterDebounceSt_A	7194251	47	0	0
EnterDetectSt_A	7194251	42	0	0
EnterStableSt_A	7194251	42	0	0
PulseIsPulse_A	7194251	42	0	0
StayInStableSt	7194251	3210	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	88	0	0
T34	862	2	0	0
T35	0	2	0	0
T36	920	2	0	0
T44	0	2	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T53	0	1	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T75	0	2	0	0
T78	0	2	0	0
T82	424	0	0	0
T83	502	0	0	0
T128	0	2	0	0
T138	0	2	0	0
T139	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	50412	0	0
T34	862	42	0	0
T35	0	93	0	0
T36	920	52	0	0
T37	0	543	0	0
T44	0	67	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T53	0	18	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T75	0	83	0	0
T78	0	62	0	0
T82	424	0	0	0
T83	502	0	0	0
T138	0	54	0	0
T139	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507684	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	3277	0	0
T34	862	113	0	0
T35	0	43	0	0
T36	920	132	0	0
T44	0	46	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T75	0	92	0	0
T78	0	40	0	0
T82	424	0	0	0
T83	502	0	0	0
T128	0	42	0	0
T138	0	42	0	0
T139	0	197	0	0
T140	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	42	0	0
T34	862	1	0	0
T35	0	1	0	0
T36	920	1	0	0
T44	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T75	0	1	0	0
T78	0	1	0	0
T82	424	0	0	0
T83	502	0	0	0
T128	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6261778	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6264208	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	47	0	0
T34	862	1	0	0
T35	0	1	0	0
T36	920	1	0	0
T37	0	1	0	0
T44	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T53	0	1	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T75	0	1	0	0
T78	0	1	0	0
T82	424	0	0	0
T83	502	0	0	0
T138	0	1	0	0
T139	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	42	0	0
T34	862	1	0	0
T35	0	1	0	0
T36	920	1	0	0
T44	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T75	0	1	0	0
T78	0	1	0	0
T82	424	0	0	0
T83	502	0	0	0
T128	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	42	0	0
T34	862	1	0	0
T35	0	1	0	0
T36	920	1	0	0
T44	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T75	0	1	0	0
T78	0	1	0	0
T82	424	0	0	0
T83	502	0	0	0
T128	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	42	0	0
T34	862	1	0	0
T35	0	1	0	0
T36	920	1	0	0
T44	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T75	0	1	0	0
T78	0	1	0	0
T82	424	0	0	0
T83	502	0	0	0
T128	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	3210	0	0
T34	862	112	0	0
T35	0	41	0	0
T36	920	131	0	0
T44	0	44	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T75	0	91	0	0
T78	0	39	0	0
T82	424	0	0	0
T83	502	0	0	0
T128	0	40	0	0
T138	0	40	0	0
T139	0	195	0	0
T140	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	17	0	0
T34	862	1	0	0
T36	920	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T75	0	1	0	0
T78	0	1	0	0
T82	424	0	0	0
T83	502	0	0	0
T118	0	1	0	0
T129	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T9,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T9,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T9,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T13
1	0	Covered	T5,T6,T7
1	1	Covered	T2,T9,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T13
0	1	Covered	T86,T145
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T13
0	1	Covered	T2,T9,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T13
1	-	Covered	T2,T9,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T13
DetectSt	168	Covered	T2,T9,T13
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T9,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T13
DebounceSt->IdleSt	163	Covered	T53,T88,T74
DetectSt->IdleSt	186	Covered	T86,T145
DetectSt->StableSt	191	Covered	T2,T9,T13
IdleSt->DebounceSt	148	Covered	T2,T9,T13
StableSt->IdleSt	206	Covered	T2,T9,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T13
0	1	Covered	T2,T9,T13
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T13
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T13
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T88,T146,T147
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T13
DetectSt	-	-	-	-	1	-	-	Covered	T86,T145
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	128	0	0
CntIncr_A	7194251	158366	0	0
CntNoWrap_A	7194251	6507644	0	0
DetectStDropOut_A	7194251	2	0	0
DetectedOut_A	7194251	68577	0	0
DetectedPulseOut_A	7194251	59	0	0
DisabledIdleSt_A	7194251	6084030	0	0
DisabledNoDetection_A	7194251	6086461	0	0
EnterDebounceSt_A	7194251	68	0	0
EnterDetectSt_A	7194251	61	0	0
EnterStableSt_A	7194251	59	0	0
PulseIsPulse_A	7194251	59	0	0
StayInStableSt	7194251	68489	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7194251	2707	0	0
gen_low_level_sva.LowLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	30	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	128	0	0
T2	8283	4	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	4	0	0
T13	0	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	4	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T53	0	1	0	0
T123	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	158366	0	0
T2	8283	178	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	154	0	0
T13	0	75	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	84	0	0
T37	0	39	0	0
T39	0	29	0	0
T43	0	88	0	0
T44	0	111	0	0
T53	0	18	0	0
T123	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507644	0	0
T1	10715	2574	0	0
T2	8283	3694	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	2	0	0
T86	30240	1	0	0
T145	0	1	0	0
T148	506	0	0	0
T149	31456	0	0	0
T150	106235	0	0	0
T151	1762	0	0	0
T152	428	0	0	0
T153	522	0	0	0
T154	421	0	0	0
T155	11593	0	0	0
T156	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	68577	0	0
T2	8283	88	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	286	0	0
T13	0	118	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	127	0	0
T37	0	43	0	0
T39	0	40	0	0
T43	0	357	0	0
T44	0	190	0	0
T78	0	86	0	0
T123	0	62	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	59	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T13	0	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T78	0	2	0	0
T123	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6084030	0	0
T1	10715	2574	0	0
T2	8283	3237	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6086461	0	0
T1	10715	2598	0	0
T2	8283	3249	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	68	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T13	0	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T53	0	1	0	0
T123	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	61	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T13	0	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T78	0	2	0	0
T123	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	59	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T13	0	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T78	0	2	0	0
T123	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	59	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T13	0	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T78	0	2	0	0
T123	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	68489	0	0
T2	8283	85	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	283	0	0
T13	0	116	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	124	0	0
T37	0	41	0	0
T39	0	39	0	0
T43	0	355	0	0
T44	0	187	0	0
T78	0	83	0	0
T123	0	60	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	2707	0	0
T1	10715	34	0	0
T2	8283	17	0	0
T3	2437	0	0	0
T5	526	5	0	0
T6	8487	0	0	0
T7	503	5	0	0
T9	0	8	0	0
T14	25334	0	0	0
T15	424	5	0	0
T16	422	3	0	0
T18	0	4	0	0
T20	451	7	0	0
T98	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	30	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T39	0	1	0	0
T44	0	1	0	0
T78	0	1	0	0
T86	0	1	0	0
T138	0	1	0	0
T139	0	1	0	0
T150	0	1	0	0