Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T53,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T53,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T43,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T5,T6,T7
1	1	Covered	T2,T53,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T43,T44
0	1	Covered	T157
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T43,T44
0	1	Covered	T2,T44,T101
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T43,T44
1	-	Covered	T2,T44,T101

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T53,T43
DetectSt	168	Covered	T2,T43,T44
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T43,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T43,T44
DebounceSt->IdleSt	163	Covered	T53,T74,T141
DetectSt->IdleSt	186	Covered	T157
DetectSt->StableSt	191	Covered	T2,T43,T44
IdleSt->DebounceSt	148	Covered	T2,T53,T43
StableSt->IdleSt	206	Covered	T2,T44,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T53,T43
0	1	Covered	T2,T53,T43
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T43,T44
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T53,T43
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T43,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T141,T119
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T53,T43
DetectSt	-	-	-	-	1	-	-	Covered	T157
DetectSt	-	-	-	-	0	1	-	Covered	T2,T43,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T44,T101
StableSt	-	-	-	-	-	-	0	Covered	T2,T43,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	76	0	0
CntIncr_A	7194251	2022	0	0
CntNoWrap_A	7194251	6507696	0	0
DetectStDropOut_A	7194251	1	0	0
DetectedOut_A	7194251	2334	0	0
DetectedPulseOut_A	7194251	35	0	0
DisabledIdleSt_A	7194251	6162201	0	0
DisabledNoDetection_A	7194251	6164633	0	0
EnterDebounceSt_A	7194251	40	0	0
EnterDetectSt_A	7194251	36	0	0
EnterStableSt_A	7194251	35	0	0
PulseIsPulse_A	7194251	35	0	0
StayInStableSt	7194251	2281	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	76	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T38	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T53	0	1	0	0
T78	0	2	0	0
T101	0	2	0	0
T129	0	4	0	0
T140	0	2	0	0
T158	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	2022	0	0
T2	8283	89	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T38	0	65	0	0
T43	0	88	0	0
T44	0	139	0	0
T53	0	18	0	0
T78	0	62	0	0
T101	0	25	0	0
T129	0	94	0	0
T140	0	89	0	0
T158	0	45	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507696	0	0
T1	10715	2574	0	0
T2	8283	3696	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1	0	0
T157	188475	1	0	0
T159	9057	0	0	0
T160	1505	0	0	0
T161	496	0	0	0
T162	402	0	0	0
T163	432	0	0	0
T164	435	0	0	0
T165	404	0	0	0
T166	636	0	0	0
T167	9622	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	2334	0	0
T2	8283	43	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T38	0	38	0	0
T43	0	39	0	0
T44	0	153	0	0
T78	0	86	0	0
T101	0	80	0	0
T129	0	245	0	0
T140	0	131	0	0
T158	0	37	0	0
T168	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	35	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T78	0	1	0	0
T101	0	1	0	0
T129	0	2	0	0
T140	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6162201	0	0
T1	10715	2497	0	0
T2	8283	3237	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6164633	0	0
T1	10715	2520	0	0
T2	8283	3249	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	40	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T53	0	1	0	0
T78	0	1	0	0
T101	0	1	0	0
T129	0	2	0	0
T140	0	1	0	0
T158	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	36	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T78	0	1	0	0
T101	0	1	0	0
T129	0	2	0	0
T140	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	35	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T78	0	1	0	0
T101	0	1	0	0
T129	0	2	0	0
T140	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	35	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T38	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T78	0	1	0	0
T101	0	1	0	0
T129	0	2	0	0
T140	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	2281	0	0
T2	8283	42	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T38	0	36	0	0
T43	0	37	0	0
T44	0	151	0	0
T78	0	84	0	0
T101	0	79	0	0
T129	0	242	0	0
T140	0	129	0	0
T158	0	35	0	0
T168	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	17	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T44	0	2	0	0
T97	0	4	0	0
T101	0	1	0	0
T118	0	1	0	0
T129	0	1	0	0
T144	0	2	0	0
T157	0	1	0	0
T169	0	1	0	0
T170	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T9,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T9,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T9,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T41
1	0	Covered	T5,T6,T7
1	1	Covered	T1,T9,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T41
0	1	Covered	T44,T96,T97
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T41
0	1	Covered	T9,T34,T75
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T41
1	-	Covered	T9,T34,T75

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T41
DetectSt	168	Covered	T1,T9,T41
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T9,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T41
DebounceSt->IdleSt	163	Covered	T53,T38,T74
DetectSt->IdleSt	186	Covered	T44,T96,T97
DetectSt->StableSt	191	Covered	T1,T9,T41
IdleSt->DebounceSt	148	Covered	T1,T9,T41
StableSt->IdleSt	206	Covered	T1,T9,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T41
0	1	Covered	T1,T9,T41
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T41
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T41
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T171
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T41
DetectSt	-	-	-	-	1	-	-	Covered	T44,T96,T97
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T34,T75
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	128	0	0
CntIncr_A	7194251	128461	0	0
CntNoWrap_A	7194251	6507644	0	0
DetectStDropOut_A	7194251	5	0	0
DetectedOut_A	7194251	152005	0	0
DetectedPulseOut_A	7194251	57	0	0
DisabledIdleSt_A	7194251	6087071	0	0
DisabledNoDetection_A	7194251	6089507	0	0
EnterDebounceSt_A	7194251	67	0	0
EnterDetectSt_A	7194251	62	0	0
EnterStableSt_A	7194251	57	0	0
PulseIsPulse_A	7194251	57	0	0
StayInStableSt	7194251	151925	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7194251	3138	0	0
gen_low_level_sva.LowLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	128	0	0
T1	10715	2	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T9	0	2	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T35	0	2	0	0
T36	0	2	0	0
T39	0	2	0	0
T41	0	2	0	0
T43	0	2	0	0
T53	0	1	0	0
T75	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	128461	0	0
T1	10715	46	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T9	0	77	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	42	0	0
T35	0	93	0	0
T36	0	52	0	0
T39	0	29	0	0
T41	0	41	0	0
T43	0	88	0	0
T53	0	19	0	0
T75	0	166	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507644	0	0
T1	10715	2572	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	5	0	0
T37	98633	0	0	0
T44	14450	1	0	0
T76	7655	0	0	0
T96	0	1	0	0
T97	0	2	0	0
T113	1420	0	0	0
T172	0	1	0	0
T173	494	0	0	0
T174	524	0	0	0
T175	422	0	0	0
T176	63033	0	0	0
T177	9930	0	0	0
T178	503	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	152005	0	0
T1	10715	26	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T9	0	332	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	200	0	0
T35	0	116	0	0
T36	0	392	0	0
T39	0	178	0	0
T41	0	67	0	0
T43	0	62	0	0
T44	0	38	0	0
T75	0	254	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	57	0	0
T1	10715	1	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T9	0	1	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T75	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6087071	0	0
T1	10715	2497	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6089507	0	0
T1	10715	2520	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	67	0	0
T1	10715	1	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T9	0	1	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T53	0	1	0	0
T75	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	62	0	0
T1	10715	1	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T9	0	1	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T75	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	57	0	0
T1	10715	1	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T9	0	1	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T75	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	57	0	0
T1	10715	1	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T9	0	1	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T39	0	1	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T75	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	151925	0	0
T1	10715	24	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T9	0	331	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	199	0	0
T35	0	114	0	0
T36	0	390	0	0
T39	0	176	0	0
T41	0	65	0	0
T43	0	61	0	0
T44	0	36	0	0
T75	0	251	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	3138	0	0
T1	10715	49	0	0
T2	8283	12	0	0
T3	2437	0	0	0
T5	526	7	0	0
T6	8487	0	0	0
T7	503	7	0	0
T9	0	9	0	0
T14	25334	0	0	0
T15	424	2	0	0
T16	422	2	0	0
T18	0	8	0	0
T19	0	4	0	0
T20	451	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	34	0	0
T9	4783	1	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	1	0	0
T40	687	0	0	0
T43	0	1	0	0
T65	503	0	0	0
T75	0	1	0	0
T77	0	1	0	0
T98	450	0	0	0
T99	442	0	0	0
T101	0	1	0	0
T116	0	1	0	0
T129	0	2	0	0
T158	0	1	0	0
T179	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T7,T20

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T7,T20
1	1	Covered	T5,T7,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T41,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T41,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T41,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T41,T36
1	0	Covered	T5,T7,T20
1	1	Covered	T2,T41,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T41,T36
0	1	Covered	T78
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T41,T36
0	1	Covered	T36,T31,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T41,T36
1	-	Covered	T36,T31,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T41,T36
DetectSt	168	Covered	T2,T41,T36
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T41,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T41,T36
DebounceSt->IdleSt	163	Covered	T2,T53,T74
DetectSt->IdleSt	186	Covered	T78
DetectSt->StableSt	191	Covered	T2,T41,T36
IdleSt->DebounceSt	148	Covered	T2,T41,T36
StableSt->IdleSt	206	Covered	T2,T41,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T41,T36
0	1	Covered	T2,T41,T36
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T41,T36
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T41,T36
IdleSt	0	-	-	-	-	-	-	Covered	T5,T7,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T41,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T180
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T41,T36
DetectSt	-	-	-	-	1	-	-	Covered	T78
DetectSt	-	-	-	-	0	1	-	Covered	T2,T41,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T31,T39
StableSt	-	-	-	-	-	-	0	Covered	T2,T41,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	120	0	0
CntIncr_A	7194251	81059	0	0
CntNoWrap_A	7194251	6507652	0	0
DetectStDropOut_A	7194251	1	0	0
DetectedOut_A	7194251	70408	0	0
DetectedPulseOut_A	7194251	57	0	0
DisabledIdleSt_A	7194251	6256848	0	0
DisabledNoDetection_A	7194251	6259282	0	0
EnterDebounceSt_A	7194251	62	0	0
EnterDetectSt_A	7194251	58	0	0
EnterStableSt_A	7194251	57	0	0
PulseIsPulse_A	7194251	57	0	0
StayInStableSt	7194251	70323	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	120	0	0
T2	8283	3	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	2	0	0
T35	0	2	0	0
T36	0	6	0	0
T39	0	2	0	0
T41	0	2	0	0
T44	0	6	0	0
T53	0	1	0	0
T78	0	4	0	0
T123	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	81059	0	0
T2	8283	178	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	24	0	0
T35	0	93	0	0
T36	0	156	0	0
T39	0	29	0	0
T41	0	41	0	0
T44	0	190	0	0
T53	0	19	0	0
T78	0	124	0	0
T123	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507652	0	0
T1	10715	2574	0	0
T2	8283	3695	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1	0	0
T78	723	1	0	0
T138	569	0	0	0
T181	504	0	0	0
T182	504	0	0	0
T183	28907	0	0	0
T184	2553	0	0	0
T185	17423	0	0	0
T186	583	0	0	0
T187	490	0	0	0
T188	13569	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	70408	0	0
T2	8283	46	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	10	0	0
T35	0	44	0	0
T36	0	191	0	0
T39	0	97	0	0
T41	0	67	0	0
T44	0	544	0	0
T78	0	85	0	0
T123	0	42	0	0
T138	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	57	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	3	0	0
T78	0	1	0	0
T123	0	1	0	0
T138	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6256848	0	0
T1	10715	2574	0	0
T2	8283	3237	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6259282	0	0
T1	10715	2598	0	0
T2	8283	3249	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	62	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	3	0	0
T53	0	1	0	0
T78	0	2	0	0
T123	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	58	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	3	0	0
T78	0	2	0	0
T123	0	1	0	0
T138	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	57	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	3	0	0
T78	0	1	0	0
T123	0	1	0	0
T138	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	57	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T36	0	3	0	0
T39	0	1	0	0
T41	0	1	0	0
T44	0	3	0	0
T78	0	1	0	0
T123	0	1	0	0
T138	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	70323	0	0
T2	8283	44	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	9	0	0
T35	0	42	0	0
T36	0	187	0	0
T39	0	96	0	0
T41	0	65	0	0
T44	0	538	0	0
T78	0	83	0	0
T123	0	40	0	0
T138	0	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	29	0	0
T31	0	1	0	0
T34	862	0	0	0
T36	920	2	0	0
T39	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T116	0	1	0	0
T129	0	1	0	0
T138	0	1	0	0
T141	0	1	0	0
T169	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T7,T20
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T40,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T40,T31

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T40,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T13,T40
1	0	Covered	T5,T6,T7
1	1	Covered	T2,T40,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T40,T31
0	1	Covered	T97,T137,T191
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T40,T31
0	1	Covered	T2,T40,T78
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T40,T31
1	-	Covered	T2,T40,T78

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T40,T31
DetectSt	168	Covered	T2,T40,T31
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T40,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T40,T31
DebounceSt->IdleSt	163	Covered	T53,T74,T141
DetectSt->IdleSt	186	Covered	T97,T137,T191
DetectSt->StableSt	191	Covered	T2,T40,T31
IdleSt->DebounceSt	148	Covered	T2,T40,T31
StableSt->IdleSt	206	Covered	T2,T40,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T40,T31
0	1	Covered	T2,T40,T31
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T40,T31
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T40,T31
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T40,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T141
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T40,T31
DetectSt	-	-	-	-	1	-	-	Covered	T97,T137,T191
DetectSt	-	-	-	-	0	1	-	Covered	T2,T40,T31
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T40,T78
StableSt	-	-	-	-	-	-	0	Covered	T2,T40,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	73	0	0
CntIncr_A	7194251	1890	0	0
CntNoWrap_A	7194251	6507699	0	0
DetectStDropOut_A	7194251	3	0	0
DetectedOut_A	7194251	2413	0	0
DetectedPulseOut_A	7194251	32	0	0
DisabledIdleSt_A	7194251	6325165	0	0
DisabledNoDetection_A	7194251	6327603	0	0
EnterDebounceSt_A	7194251	38	0	0
EnterDetectSt_A	7194251	35	0	0
EnterStableSt_A	7194251	32	0	0
PulseIsPulse_A	7194251	32	0	0
StayInStableSt	7194251	2361	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7194251	6627	0	0
gen_low_level_sva.LowLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	73	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T53	0	1	0	0
T78	0	2	0	0
T128	0	2	0	0
T138	0	2	0	0
T179	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1890	0	0
T2	8283	89	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	24	0	0
T39	0	29	0	0
T40	0	36	0	0
T42	0	91	0	0
T53	0	18	0	0
T78	0	62	0	0
T128	0	12	0	0
T138	0	54	0	0
T179	0	178	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507699	0	0
T1	10715	2574	0	0
T2	8283	3696	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	3	0	0
T97	21160	1	0	0
T119	10600	0	0	0
T131	1525	0	0	0
T137	0	1	0	0
T191	0	1	0	0
T192	503	0	0	0
T193	819	0	0	0
T194	433	0	0	0
T195	429	0	0	0
T196	1048	0	0	0
T197	421	0	0	0
T198	494	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	2413	0	0
T2	8283	218	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	45	0	0
T39	0	36	0	0
T40	0	31	0	0
T42	0	222	0	0
T78	0	41	0	0
T128	0	40	0	0
T138	0	43	0	0
T158	0	123	0	0
T179	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	32	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T78	0	1	0	0
T128	0	1	0	0
T138	0	1	0	0
T158	0	1	0	0
T179	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6325165	0	0
T1	10715	2574	0	0
T2	8283	3237	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6327603	0	0
T1	10715	2598	0	0
T2	8283	3249	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	38	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T53	0	1	0	0
T78	0	1	0	0
T128	0	1	0	0
T138	0	1	0	0
T179	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	35	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T78	0	1	0	0
T128	0	1	0	0
T138	0	1	0	0
T158	0	1	0	0
T179	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	32	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T78	0	1	0	0
T128	0	1	0	0
T138	0	1	0	0
T158	0	1	0	0
T179	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	32	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T78	0	1	0	0
T128	0	1	0	0
T138	0	1	0	0
T158	0	1	0	0
T179	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	2361	0	0
T2	8283	217	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T31	0	43	0	0
T39	0	34	0	0
T40	0	30	0	0
T42	0	220	0	0
T78	0	40	0	0
T128	0	39	0	0
T138	0	41	0	0
T158	0	122	0	0
T179	0	77	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6627	0	0
T1	10715	38	0	0
T2	8283	20	0	0
T3	2437	10	0	0
T4	0	12	0	0
T5	526	5	0	0
T6	8487	0	0	0
T7	503	7	0	0
T14	25334	29	0	0
T15	424	1	0	0
T16	422	3	0	0
T20	451	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	12	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T40	0	1	0	0
T78	0	1	0	0
T128	0	1	0	0
T143	0	1	0	0
T158	0	1	0	0
T168	0	1	0	0
T179	0	1	0	0
T199	0	1	0	0
T200	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T7,T20

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T7,T20
1	1	Covered	T5,T7,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T2,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T2,T13

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T13
1	0	Covered	T5,T7,T20
1	1	Covered	T1,T2,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T201,T118
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T13
0	1	Covered	T40,T36,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T13
1	-	Covered	T40,T36,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T13
DetectSt	168	Covered	T1,T2,T13
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T1,T2,T13

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T13
DebounceSt->IdleSt	163	Covered	T53,T74,T130
DetectSt->IdleSt	186	Covered	T201,T118
DetectSt->StableSt	191	Covered	T1,T2,T13
IdleSt->DebounceSt	148	Covered	T1,T2,T13
StableSt->IdleSt	206	Covered	T1,T2,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T13
0	1	Covered	T1,T2,T13
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T13
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T13
IdleSt	0	-	-	-	-	-	-	Covered	T5,T7,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T13
DebounceSt	-	0	1	0	-	-	-	Covered	T142,T202,T203
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T13
DetectSt	-	-	-	-	1	-	-	Covered	T201,T118
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T13
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T36,T34
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T13
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	142	0	0
CntIncr_A	7194251	37196	0	0
CntNoWrap_A	7194251	6507630	0	0
DetectStDropOut_A	7194251	3	0	0
DetectedOut_A	7194251	5280	0	0
DetectedPulseOut_A	7194251	65	0	0
DisabledIdleSt_A	7194251	6430290	0	0
DisabledNoDetection_A	7194251	6432717	0	0
EnterDebounceSt_A	7194251	75	0	0
EnterDetectSt_A	7194251	68	0	0
EnterStableSt_A	7194251	65	0	0
PulseIsPulse_A	7194251	65	0	0
StayInStableSt	7194251	5192	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	42	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	142	0	0
T1	10715	2	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T13	0	2	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	4	0	0
T36	0	4	0	0
T40	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T53	0	1	0	0
T123	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	37196	0	0
T1	10715	46	0	0
T2	8283	89	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T13	0	75	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	84	0	0
T36	0	104	0	0
T40	0	36	0	0
T42	0	91	0	0
T43	0	88	0	0
T53	0	18	0	0
T123	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507630	0	0
T1	10715	2572	0	0
T2	8283	3696	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	3	0	0
T88	13510	0	0	0
T118	0	2	0	0
T201	2954	1	0	0
T204	4316	0	0	0
T205	874	0	0	0
T206	435	0	0	0
T207	26518	0	0	0
T208	586	0	0	0
T209	496916	0	0	0
T210	4753	0	0	0
T211	7101	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	5280	0	0
T1	10715	26	0	0
T2	8283	367	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T13	0	42	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	166	0	0
T36	0	32	0	0
T40	0	110	0	0
T42	0	353	0	0
T43	0	43	0	0
T44	0	126	0	0
T123	0	62	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	65	0	0
T1	10715	1	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T13	0	1	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T123	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6430290	0	0
T1	10715	2497	0	0
T2	8283	3237	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6432717	0	0
T1	10715	2520	0	0
T2	8283	3249	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	75	0	0
T1	10715	1	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T13	0	1	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	0	1	0	0
T123	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	68	0	0
T1	10715	1	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T13	0	1	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T123	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	65	0	0
T1	10715	1	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T13	0	1	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T123	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	65	0	0
T1	10715	1	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T13	0	1	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T123	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	5192	0	0
T1	10715	24	0	0
T2	8283	365	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T13	0	40	0	0
T14	25334	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	164	0	0
T36	0	30	0	0
T40	0	109	0	0
T42	0	351	0	0
T43	0	42	0	0
T44	0	122	0	0
T123	0	60	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	42	0	0
T25	497	0	0	0
T34	862	2	0	0
T36	920	2	0	0
T38	0	1	0	0
T40	687	1	0	0
T41	7493	0	0	0
T43	0	1	0	0
T47	657	0	0	0
T59	488	0	0	0
T66	531	0	0	0
T67	524	0	0	0
T78	0	1	0	0
T100	421	0	0	0
T116	0	1	0	0
T128	0	2	0	0
T158	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T7,T20
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T40,T36,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T40,T36,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T40,T36,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T40,T36,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T36,T34
0	1	Covered	T75
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T36,T34
0	1	Covered	T36,T34,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T36,T34
1	-	Covered	T36,T34,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T36,T34
DetectSt	168	Covered	T40,T36,T34
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T40,T36,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T36,T34
DebounceSt->IdleSt	163	Covered	T53,T74,T172
DetectSt->IdleSt	186	Covered	T75
DetectSt->StableSt	191	Covered	T40,T36,T34
IdleSt->DebounceSt	148	Covered	T40,T36,T34
StableSt->IdleSt	206	Covered	T36,T34,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T36,T34
0	1	Covered	T40,T36,T34
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T36,T34
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T36,T34
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T36,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T172
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T36,T34
DetectSt	-	-	-	-	1	-	-	Covered	T75
DetectSt	-	-	-	-	0	1	-	Covered	T40,T36,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T34,T37
StableSt	-	-	-	-	-	-	0	Covered	T40,T36,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	73	0	0
CntIncr_A	7194251	55866	0	0
CntNoWrap_A	7194251	6507699	0	0
DetectStDropOut_A	7194251	1	0	0
DetectedOut_A	7194251	10932	0	0
DetectedPulseOut_A	7194251	34	0	0
DisabledIdleSt_A	7194251	6169933	0	0
DisabledNoDetection_A	7194251	6172370	0	0
EnterDebounceSt_A	7194251	38	0	0
EnterDetectSt_A	7194251	35	0	0
EnterStableSt_A	7194251	34	0	0
PulseIsPulse_A	7194251	34	0	0
StayInStableSt	7194251	10876	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7194251	6246	0	0
gen_low_level_sva.LowLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	73	0	0
T25	497	0	0	0
T34	862	4	0	0
T36	920	4	0	0
T37	0	2	0	0
T38	0	2	0	0
T40	687	2	0	0
T41	7493	0	0	0
T43	0	2	0	0
T47	657	0	0	0
T53	0	1	0	0
T59	488	0	0	0
T66	531	0	0	0
T67	524	0	0	0
T75	0	2	0	0
T100	421	0	0	0
T128	0	4	0	0
T140	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	55866	0	0
T25	497	0	0	0
T34	862	84	0	0
T36	920	104	0	0
T37	0	39	0	0
T38	0	63	0	0
T40	687	36	0	0
T41	7493	0	0	0
T43	0	88	0	0
T47	657	0	0	0
T53	0	18	0	0
T59	488	0	0	0
T66	531	0	0	0
T67	524	0	0	0
T75	0	83	0	0
T100	421	0	0	0
T128	0	31	0	0
T140	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507699	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1	0	0
T69	14576	0	0	0
T75	983	1	0	0
T212	534	0	0	0
T213	545	0	0	0
T214	426	0	0	0
T215	453	0	0	0
T216	505	0	0	0
T217	492	0	0	0
T218	422	0	0	0
T219	404	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	10932	0	0
T25	497	0	0	0
T34	862	115	0	0
T36	920	268	0	0
T37	0	3	0	0
T38	0	312	0	0
T40	687	42	0	0
T41	7493	0	0	0
T43	0	58	0	0
T47	657	0	0	0
T59	488	0	0	0
T66	531	0	0	0
T67	524	0	0	0
T100	421	0	0	0
T128	0	52	0	0
T140	0	132	0	0
T158	0	37	0	0
T189	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	34	0	0
T25	497	0	0	0
T34	862	2	0	0
T36	920	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	687	1	0	0
T41	7493	0	0	0
T43	0	1	0	0
T47	657	0	0	0
T59	488	0	0	0
T66	531	0	0	0
T67	524	0	0	0
T100	421	0	0	0
T128	0	2	0	0
T140	0	1	0	0
T158	0	1	0	0
T189	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6169933	0	0
T1	10715	2497	0	0
T2	8283	3237	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6172370	0	0
T1	10715	2520	0	0
T2	8283	3249	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	38	0	0
T25	497	0	0	0
T34	862	2	0	0
T36	920	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	687	1	0	0
T41	7493	0	0	0
T43	0	1	0	0
T47	657	0	0	0
T53	0	1	0	0
T59	488	0	0	0
T66	531	0	0	0
T67	524	0	0	0
T75	0	1	0	0
T100	421	0	0	0
T128	0	2	0	0
T140	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	35	0	0
T25	497	0	0	0
T34	862	2	0	0
T36	920	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	687	1	0	0
T41	7493	0	0	0
T43	0	1	0	0
T47	657	0	0	0
T59	488	0	0	0
T66	531	0	0	0
T67	524	0	0	0
T75	0	1	0	0
T100	421	0	0	0
T128	0	2	0	0
T140	0	1	0	0
T189	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	34	0	0
T25	497	0	0	0
T34	862	2	0	0
T36	920	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	687	1	0	0
T41	7493	0	0	0
T43	0	1	0	0
T47	657	0	0	0
T59	488	0	0	0
T66	531	0	0	0
T67	524	0	0	0
T100	421	0	0	0
T128	0	2	0	0
T140	0	1	0	0
T158	0	1	0	0
T189	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	34	0	0
T25	497	0	0	0
T34	862	2	0	0
T36	920	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	687	1	0	0
T41	7493	0	0	0
T43	0	1	0	0
T47	657	0	0	0
T59	488	0	0	0
T66	531	0	0	0
T67	524	0	0	0
T100	421	0	0	0
T128	0	2	0	0
T140	0	1	0	0
T158	0	1	0	0
T189	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	10876	0	0
T25	497	0	0	0
T34	862	112	0	0
T36	920	265	0	0
T37	0	2	0	0
T38	0	310	0	0
T40	687	40	0	0
T41	7493	0	0	0
T43	0	56	0	0
T47	657	0	0	0
T59	488	0	0	0
T66	531	0	0	0
T67	524	0	0	0
T100	421	0	0	0
T128	0	49	0	0
T140	0	130	0	0
T158	0	35	0	0
T189	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6246	0	0
T1	10715	32	0	0
T2	8283	15	0	0
T3	2437	0	0	0
T4	0	15	0	0
T5	526	3	0	0
T6	8487	0	0	0
T7	503	4	0	0
T14	25334	33	0	0
T15	424	2	0	0
T16	422	3	0	0
T18	0	3	0	0
T20	451	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	12	0	0
T34	862	1	0	0
T36	920	1	0	0
T37	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T97	0	1	0	0
T117	0	1	0	0
T128	0	1	0	0
T142	0	1	0	0
T180	0	1	0	0
T220	0	1	0	0
T221	0	1	0	0