Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T7,T20

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T7,T20
1	1	Covered	T5,T7,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T9,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T9,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T9,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T13
1	0	Covered	T5,T7,T20
1	1	Covered	T2,T9,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T40
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T40
0	1	Covered	T2,T40,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T40
1	-	Covered	T2,T40,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T13
DetectSt	168	Covered	T2,T9,T40
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T9,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T40
DebounceSt->IdleSt	163	Covered	T9,T13,T53
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T9,T40
IdleSt->DebounceSt	148	Covered	T2,T9,T13
StableSt->IdleSt	206	Covered	T2,T9,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T13
0	1	Covered	T2,T9,T13
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T40
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T13
IdleSt	0	-	-	-	-	-	-	Covered	T5,T7,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T13,T43
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T13
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T40,T36
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	121	0	0
CntIncr_A	7194251	112572	0	0
CntNoWrap_A	7194251	6507651	0	0
DetectStDropOut_A	7194251	0	0	0
DetectedOut_A	7194251	95777	0	0
DetectedPulseOut_A	7194251	54	0	0
DisabledIdleSt_A	7194251	6086640	0	0
DisabledNoDetection_A	7194251	6089074	0	0
EnterDebounceSt_A	7194251	67	0	0
EnterDetectSt_A	7194251	54	0	0
EnterStableSt_A	7194251	54	0	0
PulseIsPulse_A	7194251	54	0	0
StayInStableSt	7194251	95700	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	31	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	121	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	3	0	0
T13	0	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T36	0	6	0	0
T40	0	4	0	0
T43	0	3	0	0
T44	0	2	0	0
T53	0	1	0	0
T222	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	112572	0	0
T2	8283	89	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	154	0	0
T13	0	75	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	42	0	0
T36	0	156	0	0
T40	0	72	0	0
T43	0	176	0	0
T44	0	51	0	0
T53	0	18	0	0
T222	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507651	0	0
T1	10715	2574	0	0
T2	8283	3696	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	95777	0	0
T2	8283	44	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	37	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	29	0	0
T36	0	71	0	0
T40	0	123	0	0
T43	0	190	0	0
T44	0	7	0	0
T128	0	42	0	0
T222	0	41	0	0
T223	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	54	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T36	0	3	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T128	0	2	0	0
T222	0	1	0	0
T223	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6086640	0	0
T1	10715	2574	0	0
T2	8283	3237	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6089074	0	0
T1	10715	2598	0	0
T2	8283	3249	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	67	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T13	0	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T36	0	3	0	0
T40	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T53	0	1	0	0
T222	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	54	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T36	0	3	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T128	0	2	0	0
T222	0	1	0	0
T223	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	54	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T36	0	3	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T128	0	2	0	0
T222	0	1	0	0
T223	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	54	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T36	0	3	0	0
T40	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T128	0	2	0	0
T222	0	1	0	0
T223	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	95700	0	0
T2	8283	43	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	35	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	28	0	0
T36	0	68	0	0
T40	0	120	0	0
T43	0	188	0	0
T44	0	6	0	0
T128	0	39	0	0
T222	0	39	0	0
T223	0	39	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	31	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T36	0	3	0	0
T40	0	1	0	0
T44	0	1	0	0
T128	0	1	0	0
T129	0	1	0	0
T150	0	1	0	0
T158	0	1	0	0
T223	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T7,T20
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T34,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T34,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T34,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T41
1	0	Covered	T5,T6,T7
1	1	Covered	T9,T34,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T34,T39
0	1	Covered	T224,T196,T225
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T34,T39
0	1	Covered	T9,T39,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T34,T39
1	-	Covered	T9,T39,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T34,T39
DetectSt	168	Covered	T9,T34,T39
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T9,T34,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T34,T39
DebounceSt->IdleSt	163	Covered	T53,T74
DetectSt->IdleSt	186	Covered	T224,T196,T225
DetectSt->StableSt	191	Covered	T9,T34,T39
IdleSt->DebounceSt	148	Covered	T9,T34,T39
StableSt->IdleSt	206	Covered	T9,T39,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T34,T39
0	1	Covered	T9,T34,T39
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T34,T39
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T34,T39
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T34,T39
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T34,T39
DetectSt	-	-	-	-	1	-	-	Covered	T224,T196,T225
DetectSt	-	-	-	-	0	1	-	Covered	T9,T34,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T39,T37
StableSt	-	-	-	-	-	-	0	Covered	T9,T34,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	90	0	0
CntIncr_A	7194251	86145	0	0
CntNoWrap_A	7194251	6507682	0	0
DetectStDropOut_A	7194251	3	0	0
DetectedOut_A	7194251	75224	0	0
DetectedPulseOut_A	7194251	41	0	0
DisabledIdleSt_A	7194251	6093286	0	0
DisabledNoDetection_A	7194251	6095711	0	0
EnterDebounceSt_A	7194251	46	0	0
EnterDetectSt_A	7194251	44	0	0
EnterStableSt_A	7194251	41	0	0
PulseIsPulse_A	7194251	41	0	0
StayInStableSt	7194251	75164	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7194251	6257	0	0
gen_low_level_sva.LowLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	90	0	0
T9	4783	2	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	2	0	0
T37	0	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	687	0	0	0
T44	0	2	0	0
T53	0	1	0	0
T65	503	0	0	0
T77	0	2	0	0
T98	450	0	0	0
T99	442	0	0	0
T139	0	4	0	0
T179	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	86145	0	0
T9	4783	77	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	42	0	0
T37	0	78	0	0
T38	0	63	0	0
T39	0	29	0	0
T40	687	0	0	0
T44	0	51	0	0
T53	0	18	0	0
T65	503	0	0	0
T77	0	22	0	0
T98	450	0	0	0
T99	442	0	0	0
T139	0	106	0	0
T179	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507682	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	3	0	0
T91	4162	0	0	0
T196	0	1	0	0
T224	2700	1	0	0
T225	0	1	0	0
T226	34037	0	0	0
T227	3024	0	0	0
T228	653	0	0	0
T229	2867	0	0	0
T230	624	0	0	0
T231	492	0	0	0
T232	424	0	0	0
T233	989	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	75224	0	0
T9	4783	333	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	168	0	0
T37	0	41	0	0
T38	0	205	0	0
T39	0	26	0	0
T40	687	0	0	0
T44	0	38	0	0
T65	503	0	0	0
T77	0	62	0	0
T98	450	0	0	0
T99	442	0	0	0
T139	0	102	0	0
T179	0	40	0	0
T223	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	41	0	0
T9	4783	1	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	687	0	0	0
T44	0	1	0	0
T65	503	0	0	0
T77	0	1	0	0
T98	450	0	0	0
T99	442	0	0	0
T139	0	2	0	0
T179	0	1	0	0
T223	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6093286	0	0
T1	10715	2497	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6095711	0	0
T1	10715	2520	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	46	0	0
T9	4783	1	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	687	0	0	0
T44	0	1	0	0
T53	0	1	0	0
T65	503	0	0	0
T77	0	1	0	0
T98	450	0	0	0
T99	442	0	0	0
T139	0	2	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	44	0	0
T9	4783	1	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	687	0	0	0
T44	0	1	0	0
T65	503	0	0	0
T77	0	1	0	0
T98	450	0	0	0
T99	442	0	0	0
T139	0	2	0	0
T179	0	1	0	0
T223	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	41	0	0
T9	4783	1	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	687	0	0	0
T44	0	1	0	0
T65	503	0	0	0
T77	0	1	0	0
T98	450	0	0	0
T99	442	0	0	0
T139	0	2	0	0
T179	0	1	0	0
T223	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	41	0	0
T9	4783	1	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	1	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	687	0	0	0
T44	0	1	0	0
T65	503	0	0	0
T77	0	1	0	0
T98	450	0	0	0
T99	442	0	0	0
T139	0	2	0	0
T179	0	1	0	0
T223	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	75164	0	0
T9	4783	332	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	166	0	0
T37	0	39	0	0
T38	0	203	0	0
T39	0	25	0	0
T40	687	0	0	0
T44	0	36	0	0
T65	503	0	0	0
T77	0	60	0	0
T98	450	0	0	0
T99	442	0	0	0
T139	0	100	0	0
T179	0	38	0	0
T223	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6257	0	0
T1	10715	36	0	0
T2	8283	17	0	0
T3	2437	0	0	0
T4	0	9	0	0
T5	526	4	0	0
T6	8487	0	0	0
T7	503	5	0	0
T9	0	13	0	0
T14	25334	32	0	0
T15	424	2	0	0
T16	422	0	0	0
T18	0	5	0	0
T20	451	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	22	0	0
T9	4783	1	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T37	0	2	0	0
T39	0	1	0	0
T40	687	0	0	0
T65	503	0	0	0
T97	0	3	0	0
T98	450	0	0	0
T99	442	0	0	0
T118	0	2	0	0
T128	0	2	0	0
T129	0	1	0	0
T139	0	2	0	0
T140	0	1	0	0
T158	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T7,T20

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T7,T20
1	1	Covered	T5,T7,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T9,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T2,T9,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T2,T9,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T5,T7,T20
1	1	Covered	T2,T9,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T36
0	1	Covered	T37,T38,T140
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T36
0	1	Covered	T2,T9,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T9,T36
1	-	Covered	T2,T9,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T36
DetectSt	168	Covered	T2,T9,T36
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T2,T9,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T36
DebounceSt->IdleSt	163	Covered	T53,T37,T78
DetectSt->IdleSt	186	Covered	T37,T38,T140
DetectSt->StableSt	191	Covered	T2,T9,T36
IdleSt->DebounceSt	148	Covered	T2,T9,T36
StableSt->IdleSt	206	Covered	T2,T9,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T36
0	1	Covered	T2,T9,T36
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T36
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T36
IdleSt	0	-	-	-	-	-	-	Covered	T5,T7,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T78,T201,T224
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T36
DetectSt	-	-	-	-	1	-	-	Covered	T37,T38,T140
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T36
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	132	0	0
CntIncr_A	7194251	87846	0	0
CntNoWrap_A	7194251	6507640	0	0
DetectStDropOut_A	7194251	5	0	0
DetectedOut_A	7194251	26241	0	0
DetectedPulseOut_A	7194251	58	0	0
DisabledIdleSt_A	7194251	6324644	0	0
DisabledNoDetection_A	7194251	6327077	0	0
EnterDebounceSt_A	7194251	70	0	0
EnterDetectSt_A	7194251	63	0	0
EnterStableSt_A	7194251	58	0	0
PulseIsPulse_A	7194251	58	0	0
StayInStableSt	7194251	26154	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	29	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	132	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	4	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	4	0	0
T36	0	4	0	0
T37	0	4	0	0
T44	0	2	0	0
T53	0	1	0	0
T75	0	2	0	0
T78	0	3	0	0
T176	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	87846	0	0
T2	8283	89	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	154	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	84	0	0
T36	0	104	0	0
T37	0	41767	0	0
T44	0	95	0	0
T53	0	17	0	0
T75	0	83	0	0
T78	0	124	0	0
T176	0	60	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507640	0	0
T1	10715	2574	0	0
T2	8283	3696	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	5	0	0
T37	98633	1	0	0
T38	0	1	0	0
T96	0	1	0	0
T140	0	1	0	0
T174	524	0	0	0
T175	422	0	0	0
T176	63033	0	0	0
T177	9930	0	0	0
T178	503	0	0	0
T189	0	1	0	0
T234	523	0	0	0
T235	403	0	0	0
T236	405	0	0	0
T237	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	26241	0	0
T2	8283	231	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	123	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	201	0	0
T36	0	310	0	0
T37	0	2	0	0
T44	0	145	0	0
T75	0	44	0	0
T77	0	94	0	0
T78	0	85	0	0
T176	0	125	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	58	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T44	0	1	0	0
T75	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6324644	0	0
T1	10715	2497	0	0
T2	8283	3237	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6327077	0	0
T1	10715	2520	0	0
T2	8283	3249	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	70	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	3	0	0
T44	0	1	0	0
T53	0	1	0	0
T75	0	1	0	0
T78	0	2	0	0
T176	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	63	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T44	0	1	0	0
T75	0	1	0	0
T78	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	58	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T44	0	1	0	0
T75	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	58	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	2	0	0
T36	0	2	0	0
T37	0	1	0	0
T44	0	1	0	0
T75	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	26154	0	0
T2	8283	230	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	121	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	198	0	0
T36	0	307	0	0
T37	0	1	0	0
T44	0	143	0	0
T75	0	43	0	0
T77	0	91	0	0
T78	0	83	0	0
T176	0	123	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	29	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T9	4783	2	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T116	0	1	0	0
T128	0	1	0	0
T140	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T7,T20
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T36,T53,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T36,T53,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T36,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T41,T36
1	0	Covered	T5,T6,T7
1	1	Covered	T36,T53,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T172
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T36,T37,T38
0	1	Covered	T36,T37,T139
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T36,T37,T38
1	-	Covered	T36,T37,T139

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T36,T53,T43
DetectSt	168	Covered	T36,T37,T38
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T36,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T36,T37,T38
DebounceSt->IdleSt	163	Covered	T53,T43,T77
DetectSt->IdleSt	186	Covered	T172
DetectSt->StableSt	191	Covered	T36,T37,T38
IdleSt->DebounceSt	148	Covered	T36,T53,T43
StableSt->IdleSt	206	Covered	T36,T37,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T36,T53,T43
0	1	Covered	T36,T53,T43
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T36,T37,T38
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T36,T53,T43
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T36,T37,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T43,T77,T172
DebounceSt	-	0	0	-	-	-	-	Covered	T36,T53,T43
DetectSt	-	-	-	-	1	-	-	Covered	T172
DetectSt	-	-	-	-	0	1	-	Covered	T36,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T37,T139
StableSt	-	-	-	-	-	-	0	Covered	T36,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	75	0	0
CntIncr_A	7194251	97102	0	0
CntNoWrap_A	7194251	6507697	0	0
DetectStDropOut_A	7194251	1	0	0
DetectedOut_A	7194251	3023	0	0
DetectedPulseOut_A	7194251	34	0	0
DisabledIdleSt_A	7194251	6154859	0	0
DisabledNoDetection_A	7194251	6157296	0	0
EnterDebounceSt_A	7194251	40	0	0
EnterDetectSt_A	7194251	35	0	0
EnterStableSt_A	7194251	34	0	0
PulseIsPulse_A	7194251	34	0	0
StayInStableSt	7194251	2969	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7194251	6310	0	0
gen_low_level_sva.LowLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	75	0	0
T34	862	0	0	0
T36	920	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T43	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T53	0	1	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T77	0	1	0	0
T82	424	0	0	0
T83	502	0	0	0
T116	0	4	0	0
T128	0	2	0	0
T139	0	4	0	0
T189	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	97102	0	0
T34	862	0	0	0
T36	920	52	0	0
T37	0	41185	0	0
T38	0	63	0	0
T43	0	88	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T53	0	17	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T77	0	22	0	0
T82	424	0	0	0
T83	502	0	0	0
T116	0	76	0	0
T128	0	19	0	0
T139	0	106	0	0
T189	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507697	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1	0	0
T172	9650	1	0	0
T238	670	0	0	0
T239	21136	0	0	0
T240	416	0	0	0
T241	426	0	0	0
T242	33596	0	0	0
T243	518	0	0	0
T244	2338	0	0	0
T245	502	0	0	0
T246	1295	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	3023	0	0
T34	862	0	0	0
T36	920	43	0	0
T37	0	43	0	0
T38	0	38	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T88	0	234	0	0
T116	0	83	0	0
T117	0	190	0	0
T128	0	100	0	0
T129	0	65	0	0
T139	0	50	0	0
T189	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	34	0	0
T34	862	0	0	0
T36	920	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T88	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0
T128	0	1	0	0
T129	0	2	0	0
T139	0	2	0	0
T189	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6154859	0	0
T1	10715	2497	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6157296	0	0
T1	10715	2520	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	40	0	0
T34	862	0	0	0
T36	920	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T43	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T53	0	1	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T77	0	1	0	0
T82	424	0	0	0
T83	502	0	0	0
T116	0	2	0	0
T128	0	1	0	0
T139	0	2	0	0
T189	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	35	0	0
T34	862	0	0	0
T36	920	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T88	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0
T128	0	1	0	0
T129	0	2	0	0
T139	0	2	0	0
T189	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	34	0	0
T34	862	0	0	0
T36	920	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T88	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0
T128	0	1	0	0
T129	0	2	0	0
T139	0	2	0	0
T189	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	34	0	0
T34	862	0	0	0
T36	920	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T88	0	1	0	0
T116	0	2	0	0
T117	0	1	0	0
T128	0	1	0	0
T129	0	2	0	0
T139	0	2	0	0
T189	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	2969	0	0
T34	862	0	0	0
T36	920	42	0	0
T37	0	42	0	0
T38	0	36	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T88	0	232	0	0
T116	0	80	0	0
T117	0	188	0	0
T128	0	98	0	0
T129	0	62	0	0
T139	0	48	0	0
T189	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6310	0	0
T1	10715	38	0	0
T2	8283	15	0	0
T3	2437	0	0	0
T4	0	9	0	0
T5	526	5	0	0
T6	8487	0	0	0
T7	503	4	0	0
T14	25334	31	0	0
T15	424	2	0	0
T16	422	1	0	0
T18	0	4	0	0
T20	451	7	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	14	0	0
T34	862	0	0	0
T36	920	1	0	0
T37	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T97	0	1	0	0
T116	0	1	0	0
T118	0	2	0	0
T129	0	1	0	0
T137	0	1	0	0
T139	0	2	0	0
T196	0	1	0	0
T247	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T5,T7,T20

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T7,T20
1	1	Covered	T5,T7,T20

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T41,T36,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T41,T36,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T41,T36,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T40,T41
1	0	Covered	T5,T7,T20
1	1	Covered	T41,T36,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T41,T36,T42
0	1	Covered	T128,T201
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T36,T42
0	1	Covered	T36,T42,T44
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T36,T42
1	-	Covered	T36,T42,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T41,T36,T35
DetectSt	168	Covered	T41,T36,T42
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T41,T36,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T41,T36,T42
DebounceSt->IdleSt	163	Covered	T35,T53,T77
DetectSt->IdleSt	186	Covered	T128,T201
DetectSt->StableSt	191	Covered	T41,T36,T42
IdleSt->DebounceSt	148	Covered	T41,T36,T35
StableSt->IdleSt	206	Covered	T41,T36,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T41,T36,T35
0	1	Covered	T41,T36,T35
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T41,T36,T42
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T41,T36,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T7,T20
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T41,T36,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T77,T221
DebounceSt	-	0	0	-	-	-	-	Covered	T41,T36,T35
DetectSt	-	-	-	-	1	-	-	Covered	T128,T201
DetectSt	-	-	-	-	0	1	-	Covered	T41,T36,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T42,T44
StableSt	-	-	-	-	-	-	0	Covered	T41,T36,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	115	0	0
CntIncr_A	7194251	88162	0	0
CntNoWrap_A	7194251	6507657	0	0
DetectStDropOut_A	7194251	2	0	0
DetectedOut_A	7194251	48246	0	0
DetectedPulseOut_A	7194251	53	0	0
DisabledIdleSt_A	7194251	6173722	0	0
DisabledNoDetection_A	7194251	6176163	0	0
EnterDebounceSt_A	7194251	60	0	0
EnterDetectSt_A	7194251	55	0	0
EnterStableSt_A	7194251	53	0	0
PulseIsPulse_A	7194251	53	0	0
StayInStableSt	7194251	48173	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	33	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	115	0	0
T34	862	0	0	0
T35	0	1	0	0
T36	920	4	0	0
T37	0	2	0	0
T38	0	6	0	0
T41	7493	2	0	0
T42	0	4	0	0
T44	0	4	0	0
T47	657	0	0	0
T48	19222	0	0	0
T53	0	1	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T77	0	1	0	0
T82	424	0	0	0
T83	502	0	0	0
T128	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	88162	0	0
T34	862	0	0	0
T35	0	93	0	0
T36	920	104	0	0
T37	0	39	0	0
T38	0	189	0	0
T41	7493	41	0	0
T42	0	182	0	0
T44	0	162	0	0
T47	657	0	0	0
T48	19222	0	0	0
T53	0	17	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T77	0	22	0	0
T82	424	0	0	0
T83	502	0	0	0
T128	0	25049	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507657	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	2	0	0
T85	587	0	0	0
T101	716	0	0	0
T102	527	0	0	0
T103	728	0	0	0
T104	503	0	0	0
T105	423	0	0	0
T106	420	0	0	0
T107	408	0	0	0
T108	491	0	0	0
T128	83732	1	0	0
T201	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	48246	0	0
T34	862	0	0	0
T36	920	125	0	0
T37	0	87	0	0
T38	0	118	0	0
T41	7493	67	0	0
T42	0	306	0	0
T44	0	169	0	0
T47	657	0	0	0
T48	19222	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T101	0	189	0	0
T128	0	14507	0	0
T129	0	186	0	0
T150	0	21455	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	53	0	0
T34	862	0	0	0
T36	920	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T41	7493	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T47	657	0	0	0
T48	19222	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T101	0	2	0	0
T128	0	2	0	0
T129	0	2	0	0
T150	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6173722	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6176163	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	60	0	0
T34	862	0	0	0
T35	0	1	0	0
T36	920	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T41	7493	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T47	657	0	0	0
T48	19222	0	0	0
T53	0	1	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T77	0	1	0	0
T82	424	0	0	0
T83	502	0	0	0
T128	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	55	0	0
T34	862	0	0	0
T36	920	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T41	7493	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T47	657	0	0	0
T48	19222	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T101	0	2	0	0
T128	0	3	0	0
T129	0	2	0	0
T150	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	53	0	0
T34	862	0	0	0
T36	920	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T41	7493	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T47	657	0	0	0
T48	19222	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T101	0	2	0	0
T128	0	2	0	0
T129	0	2	0	0
T150	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	53	0	0
T34	862	0	0	0
T36	920	2	0	0
T37	0	1	0	0
T38	0	3	0	0
T41	7493	1	0	0
T42	0	2	0	0
T44	0	2	0	0
T47	657	0	0	0
T48	19222	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T101	0	2	0	0
T128	0	2	0	0
T129	0	2	0	0
T150	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	48173	0	0
T34	862	0	0	0
T36	920	122	0	0
T37	0	85	0	0
T38	0	114	0	0
T41	7493	65	0	0
T42	0	303	0	0
T44	0	166	0	0
T47	657	0	0	0
T48	19222	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T101	0	186	0	0
T128	0	14503	0	0
T129	0	184	0	0
T150	0	21454	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	33	0	0
T34	862	0	0	0
T36	920	1	0	0
T38	0	2	0	0
T42	0	1	0	0
T44	0	1	0	0
T47	657	0	0	0
T48	19222	0	0	0
T49	788	0	0	0
T56	1040	0	0	0
T59	488	0	0	0
T60	497	0	0	0
T82	424	0	0	0
T83	502	0	0	0
T88	0	1	0	0
T101	0	1	0	0
T129	0	2	0	0
T130	0	1	0	0
T150	0	1	0	0
T158	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T7,T20
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T20
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T9,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T9,T34,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T9
1	0	Covered	T5,T6,T7
1	1	Covered	T9,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T34,T35
0	1	Covered	T38,T97,T248
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T34,T35
0	1	Covered	T9,T34,T43
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T34,T35
1	-	Covered	T9,T34,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T34,T35
DetectSt	168	Covered	T9,T34,T35
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T9,T34,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T34,T35
DebounceSt->IdleSt	163	Covered	T53,T88,T74
DetectSt->IdleSt	186	Covered	T38,T97,T248
DetectSt->StableSt	191	Covered	T9,T34,T35
IdleSt->DebounceSt	148	Covered	T9,T34,T35
StableSt->IdleSt	206	Covered	T9,T34,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T34,T35
0	1	Covered	T9,T34,T35
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T34,T35
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T34,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T88,T143
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T38,T97,T248
DetectSt	-	-	-	-	0	1	-	Covered	T9,T34,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T34,T43
StableSt	-	-	-	-	-	-	0	Covered	T9,T34,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	88	0	0
CntIncr_A	7194251	23703	0	0
CntNoWrap_A	7194251	6507684	0	0
DetectStDropOut_A	7194251	3	0	0
DetectedOut_A	7194251	44496	0	0
DetectedPulseOut_A	7194251	39	0	0
DisabledIdleSt_A	7194251	6237130	0	0
DisabledNoDetection_A	7194251	6239555	0	0
EnterDebounceSt_A	7194251	46	0	0
EnterDetectSt_A	7194251	42	0	0
EnterStableSt_A	7194251	39	0	0
PulseIsPulse_A	7194251	39	0	0
StayInStableSt	7194251	44435	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7194251	6983	0	0
gen_low_level_sva.LowLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	88	0	0
T9	4783	4	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T38	0	6	0	0
T39	0	2	0	0
T40	687	0	0	0
T42	0	2	0	0
T43	0	2	0	0
T53	0	1	0	0
T65	503	0	0	0
T98	450	0	0	0
T99	442	0	0	0
T128	0	4	0	0
T179	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	23703	0	0
T9	4783	154	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	84	0	0
T35	0	93	0	0
T38	0	191	0	0
T39	0	29	0	0
T40	687	0	0	0
T42	0	91	0	0
T43	0	88	0	0
T53	0	17	0	0
T65	503	0	0	0
T98	450	0	0	0
T99	442	0	0	0
T128	0	79	0	0
T179	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6507684	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	3	0	0
T38	7590	1	0	0
T77	19253	0	0	0
T97	0	1	0	0
T248	0	1	0	0
T249	524	0	0	0
T250	426	0	0	0
T251	1791	0	0	0
T252	48453	0	0	0
T253	35537	0	0	0
T254	21424	0	0	0
T255	406	0	0	0
T256	409	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	44496	0	0
T9	4783	250	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	34	0	0
T35	0	43	0	0
T38	0	80	0	0
T39	0	93	0	0
T40	687	0	0	0
T42	0	88	0	0
T43	0	42	0	0
T65	503	0	0	0
T98	450	0	0	0
T99	442	0	0	0
T128	0	84	0	0
T150	0	41541	0	0
T179	0	160	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	39	0	0
T9	4783	2	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	687	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T65	503	0	0	0
T98	450	0	0	0
T99	442	0	0	0
T128	0	2	0	0
T150	0	1	0	0
T179	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6237130	0	0
T1	10715	2497	0	0
T2	8283	3237	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24888	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6239555	0	0
T1	10715	2520	0	0
T2	8283	3249	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	46	0	0
T9	4783	2	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	687	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T53	0	1	0	0
T65	503	0	0	0
T98	450	0	0	0
T99	442	0	0	0
T128	0	2	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	42	0	0
T9	4783	2	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	3	0	0
T39	0	1	0	0
T40	687	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T65	503	0	0	0
T98	450	0	0	0
T99	442	0	0	0
T128	0	2	0	0
T150	0	1	0	0
T179	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	39	0	0
T9	4783	2	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	687	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T65	503	0	0	0
T98	450	0	0	0
T99	442	0	0	0
T128	0	2	0	0
T150	0	1	0	0
T179	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	39	0	0
T9	4783	2	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	687	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T65	503	0	0	0
T98	450	0	0	0
T99	442	0	0	0
T128	0	2	0	0
T150	0	1	0	0
T179	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	44435	0	0
T9	4783	247	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	32	0	0
T35	0	41	0	0
T38	0	77	0	0
T39	0	91	0	0
T40	687	0	0	0
T42	0	87	0	0
T43	0	41	0	0
T65	503	0	0	0
T98	450	0	0	0
T99	442	0	0	0
T128	0	81	0	0
T150	0	41539	0	0
T179	0	158	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6983	0	0
T1	10715	43	0	0
T2	8283	26	0	0
T3	2437	10	0	0
T4	0	14	0	0
T5	526	4	0	0
T6	8487	0	0	0
T7	503	5	0	0
T14	25334	35	0	0
T15	424	4	0	0
T16	422	0	0	0
T18	0	4	0	0
T20	451	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	17	0	0
T9	4783	1	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	0	0	0
T13	603	0	0	0
T26	17743	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T40	687	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T65	503	0	0	0
T98	450	0	0	0
T99	442	0	0	0
T116	0	1	0	0
T128	0	1	0	0
T142	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0