Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T26,T27
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T26,T27
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T26,T27
0	1	Covered	T27,T68,T53
1	0	Covered	T27,T53,T70

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T26,T45
0	1	Covered	T14,T26,T45
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T26,T45
1	-	Covered	T14,T26,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T26,T27
DetectSt	168	Covered	T14,T26,T27
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T14,T26,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T26,T27
DebounceSt->IdleSt	163	Covered	T53,T69,T257
DetectSt->IdleSt	186	Covered	T27,T68,T53
DetectSt->StableSt	191	Covered	T14,T26,T45
IdleSt->DebounceSt	148	Covered	T14,T26,T27
StableSt->IdleSt	206	Covered	T14,T26,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T26,T27
0	1	Covered	T14,T26,T27
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T26,T27
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T14,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T69,T257
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T27,T68,T53
DetectSt	-	-	-	-	0	1	-	Covered	T14,T26,T45
DetectSt	-	-	-	-	0	0	-	Covered	T14,T26,T27
StableSt	-	-	-	-	-	-	1	Covered	T14,T26,T45
StableSt	-	-	-	-	-	-	0	Covered	T14,T26,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	3049	0	0
CntIncr_A	7194251	101022	0	0
CntNoWrap_A	7194251	6504723	0	0
DetectStDropOut_A	7194251	290	0	0
DetectedOut_A	7194251	87564	0	0
DetectedPulseOut_A	7194251	993	0	0
DisabledIdleSt_A	7194251	6028087	0	0
DisabledNoDetection_A	7194251	6030365	0	0
EnterDebounceSt_A	7194251	1535	0	0
EnterDetectSt_A	7194251	1516	0	0
EnterStableSt_A	7194251	993	0	0
PulseIsPulse_A	7194251	993	0	0
StayInStableSt	7194251	86451	0	0
gen_high_event_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	870	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	3049	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	52	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	32	0	0
T27	0	48	0	0
T45	0	30	0	0
T46	0	54	0	0
T51	0	28	0	0
T53	0	16	0	0
T68	0	58	0	0
T69	0	5	0	0
T70	0	30	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	101022	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	2444	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1280	0	0
T27	0	1686	0	0
T45	0	750	0	0
T46	0	2457	0	0
T51	0	840	0	0
T53	0	461	0	0
T68	0	1127	0	0
T69	0	1740	0	0
T70	0	1247	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6504723	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24836	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	290	0	0
T27	22498	15	0	0
T30	23627	0	0	0
T31	37784	0	0	0
T32	34195	0	0	0
T45	6346	0	0	0
T50	746	0	0	0
T53	0	1	0	0
T57	740	0	0	0
T58	807	0	0	0
T68	0	29	0	0
T70	0	8	0	0
T74	0	1	0	0
T76	0	7	0	0
T84	0	13	0	0
T121	405	0	0	0
T122	521	0	0	0
T258	0	3	0	0
T259	0	1	0	0
T260	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	87564	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	2028	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1235	0	0
T45	0	599	0	0
T46	0	2866	0	0
T51	0	1702	0	0
T53	0	342	0	0
T110	0	76	0	0
T177	0	1297	0	0
T185	0	1608	0	0
T261	0	1155	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	993	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	26	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	16	0	0
T45	0	15	0	0
T46	0	27	0	0
T51	0	14	0	0
T53	0	5	0	0
T110	0	1	0	0
T177	0	17	0	0
T185	0	32	0	0
T261	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6028087	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	17279	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6030365	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	17282	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1535	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	26	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	16	0	0
T27	0	24	0	0
T45	0	15	0	0
T46	0	27	0	0
T51	0	14	0	0
T53	0	9	0	0
T68	0	29	0	0
T69	0	6	0	0
T70	0	15	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1516	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	26	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	16	0	0
T27	0	24	0	0
T45	0	15	0	0
T46	0	27	0	0
T51	0	14	0	0
T53	0	7	0	0
T68	0	29	0	0
T70	0	15	0	0
T110	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	993	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	26	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	16	0	0
T45	0	15	0	0
T46	0	27	0	0
T51	0	14	0	0
T53	0	5	0	0
T110	0	1	0	0
T177	0	17	0	0
T185	0	32	0	0
T261	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	993	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	26	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	16	0	0
T45	0	15	0	0
T46	0	27	0	0
T51	0	14	0	0
T53	0	5	0	0
T110	0	1	0	0
T177	0	17	0	0
T185	0	32	0	0
T261	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	86451	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	1998	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1216	0	0
T45	0	584	0	0
T46	0	2839	0	0
T51	0	1685	0	0
T53	0	337	0	0
T110	0	74	0	0
T177	0	1280	0	0
T185	0	1574	0	0
T261	0	1147	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	870	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	22	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	13	0	0
T45	0	15	0	0
T46	0	27	0	0
T51	0	11	0	0
T53	0	5	0	0
T177	0	17	0	0
T185	0	30	0	0
T261	0	6	0	0
T262	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T2
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T1,T14,T2

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T1,T14,T2

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T2
1	0	Covered	T6,T1,T14
1	1	Covered	T1,T14,T2

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T4
0	1	Covered	T12,T63,T86
1	0	Covered	T53,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T4
0	1	Covered	T2,T4,T9
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T2,T4
1	-	Covered	T2,T4,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T2
DetectSt	168	Covered	T14,T2,T4
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T14,T2,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T4
DebounceSt->IdleSt	163	Covered	T1,T9,T31
DetectSt->IdleSt	186	Covered	T12,T63,T53
DetectSt->StableSt	191	Covered	T14,T2,T4
IdleSt->DebounceSt	148	Covered	T1,T14,T2
StableSt->IdleSt	206	Covered	T14,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T14,T2
0	1	Covered	T1,T14,T2
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T4
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T2
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T9,T31
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T2
DetectSt	-	-	-	-	1	-	-	Covered	T12,T63,T53
DetectSt	-	-	-	-	0	1	-	Covered	T14,T2,T4
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T4
StableSt	-	-	-	-	-	-	1	Covered	T2,T4,T9
StableSt	-	-	-	-	-	-	0	Covered	T14,T2,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	1035	0	0
CntIncr_A	7194251	56042	0	0
CntNoWrap_A	7194251	6506737	0	0
DetectStDropOut_A	7194251	70	0	0
DetectedOut_A	7194251	14937	0	0
DetectedPulseOut_A	7194251	407	0	0
DisabledIdleSt_A	7194251	6133992	0	0
DisabledNoDetection_A	7194251	6135695	0	0
EnterDebounceSt_A	7194251	558	0	0
EnterDetectSt_A	7194251	482	0	0
EnterStableSt_A	7194251	407	0	0
PulseIsPulse_A	7194251	407	0	0
StayInStableSt	7194251	14498	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	373	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1035	0	0
T1	10715	1	0	0
T2	8283	4	0	0
T3	2437	0	0	0
T4	21648	2	0	0
T9	0	4	0	0
T12	0	2	0	0
T14	25334	8	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	4	0	0
T30	0	8	0	0
T32	0	4	0	0
T48	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	56042	0	0
T1	10715	20	0	0
T2	8283	266	0	0
T3	2437	0	0	0
T4	21648	147	0	0
T9	0	65	0	0
T12	0	242	0	0
T14	25334	256	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	120	0	0
T30	0	476	0	0
T32	0	400	0	0
T48	0	369	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6506737	0	0
T1	10715	2573	0	0
T2	8283	3694	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24880	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	70	0	0
T12	28453	1	0	0
T13	603	0	0	0
T26	17743	0	0	0
T40	687	0	0	0
T63	0	11	0	0
T65	503	0	0	0
T66	531	0	0	0
T67	524	0	0	0
T86	0	1	0	0
T87	0	4	0	0
T88	0	1	0	0
T91	0	1	0	0
T93	0	5	0	0
T94	0	13	0	0
T95	0	10	0	0
T96	0	2	0	0
T98	450	0	0	0
T99	442	0	0	0
T100	421	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	14937	0	0
T2	8283	169	0	0
T3	2437	0	0	0
T4	21648	37	0	0
T8	1409	0	0	0
T9	0	3	0	0
T14	25334	289	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	192	0	0
T30	0	222	0	0
T31	0	59	0	0
T32	0	14	0	0
T48	0	177	0	0
T51	0	174	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	407	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	1	0	0
T8	1409	0	0	0
T9	0	1	0	0
T14	25334	4	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	2	0	0
T30	0	4	0	0
T31	0	8	0	0
T32	0	2	0	0
T48	0	3	0	0
T51	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6133992	0	0
T1	10715	2549	0	0
T2	8283	3221	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	22864	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6135695	0	0
T1	10715	2572	0	0
T2	8283	3233	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	22868	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	558	0	0
T1	10715	1	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	1	0	0
T9	0	3	0	0
T12	0	1	0	0
T14	25334	4	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	2	0	0
T30	0	4	0	0
T32	0	2	0	0
T48	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	482	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	1	0	0
T8	1409	0	0	0
T9	0	1	0	0
T12	0	1	0	0
T14	25334	4	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	2	0	0
T30	0	4	0	0
T31	0	8	0	0
T32	0	2	0	0
T48	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	407	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	1	0	0
T8	1409	0	0	0
T9	0	1	0	0
T14	25334	4	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	2	0	0
T30	0	4	0	0
T31	0	8	0	0
T32	0	2	0	0
T48	0	3	0	0
T51	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	407	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	1	0	0
T8	1409	0	0	0
T9	0	1	0	0
T14	25334	4	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	2	0	0
T30	0	4	0	0
T31	0	8	0	0
T32	0	2	0	0
T48	0	3	0	0
T51	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	14498	0	0
T2	8283	167	0	0
T3	2437	0	0	0
T4	21648	36	0	0
T8	1409	0	0	0
T9	0	2	0	0
T14	25334	281	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	188	0	0
T30	0	218	0	0
T31	0	51	0	0
T32	0	12	0	0
T48	0	174	0	0
T51	0	171	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	373	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	1	0	0
T8	1409	0	0	0
T9	4783	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T30	0	4	0	0
T31	0	8	0	0
T32	0	2	0	0
T46	0	5	0	0
T48	0	3	0	0
T51	0	3	0	0
T111	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T26,T27
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T26,T27
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T26,T27
0	1	Covered	T26,T51,T68
1	0	Covered	T26,T45,T51

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T27,T46
0	1	Covered	T14,T27,T46
1	0	Covered	T53,T109

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T27,T46
1	-	Covered	T14,T27,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T26,T27
DetectSt	168	Covered	T14,T26,T27
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T14,T27,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T26,T27
DebounceSt->IdleSt	163	Covered	T53,T257,T74
DetectSt->IdleSt	186	Covered	T26,T45,T51
DetectSt->StableSt	191	Covered	T14,T27,T46
IdleSt->DebounceSt	148	Covered	T14,T26,T27
StableSt->IdleSt	206	Covered	T14,T27,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T26,T27
0	1	Covered	T14,T26,T27
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T26,T27
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T14,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T257,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T26,T45,T51
DetectSt	-	-	-	-	0	1	-	Covered	T14,T27,T46
DetectSt	-	-	-	-	0	0	-	Covered	T14,T26,T27
StableSt	-	-	-	-	-	-	1	Covered	T14,T27,T46
StableSt	-	-	-	-	-	-	0	Covered	T14,T27,T46
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	2580	0	0
CntIncr_A	7194251	88952	0	0
CntNoWrap_A	7194251	6505192	0	0
DetectStDropOut_A	7194251	236	0	0
DetectedOut_A	7194251	71822	0	0
DetectedPulseOut_A	7194251	876	0	0
DisabledIdleSt_A	7194251	6042360	0	0
DisabledNoDetection_A	7194251	6044641	0	0
EnterDebounceSt_A	7194251	1296	0	0
EnterDetectSt_A	7194251	1285	0	0
EnterStableSt_A	7194251	876	0	0
PulseIsPulse_A	7194251	876	0	0
StayInStableSt	7194251	70829	0	0
gen_high_event_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	742	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	2580	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	64	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	58	0	0
T27	0	18	0	0
T45	0	12	0	0
T46	0	20	0	0
T51	0	24	0	0
T53	0	16	0	0
T68	0	24	0	0
T70	0	16	0	0
T261	0	16	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	88952	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	2624	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	2742	0	0
T27	0	540	0	0
T45	0	315	0	0
T46	0	870	0	0
T51	0	938	0	0
T53	0	364	0	0
T68	0	465	0	0
T70	0	616	0	0
T261	0	584	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6505192	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24824	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	236	0	0
T25	497	0	0	0
T26	17743	13	0	0
T34	862	0	0	0
T36	920	0	0	0
T40	687	0	0	0
T41	7493	0	0	0
T47	657	0	0	0
T51	0	5	0	0
T53	0	1	0	0
T66	531	0	0	0
T67	524	0	0	0
T68	0	12	0	0
T74	0	1	0	0
T84	0	14	0	0
T100	421	0	0	0
T259	0	4	0	0
T263	0	6	0	0
T264	0	3	0	0
T265	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	71822	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	3574	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	2288	0	0
T46	0	624	0	0
T53	0	330	0	0
T70	0	946	0	0
T76	0	380	0	0
T177	0	2425	0	0
T183	0	457	0	0
T185	0	168	0	0
T261	0	767	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	876	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	32	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	9	0	0
T46	0	10	0	0
T53	0	5	0	0
T70	0	8	0	0
T76	0	19	0	0
T177	0	27	0	0
T183	0	13	0	0
T185	0	6	0	0
T261	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6042360	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	16289	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6044641	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	16290	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1296	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	32	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	29	0	0
T27	0	9	0	0
T45	0	6	0	0
T46	0	10	0	0
T51	0	12	0	0
T53	0	9	0	0
T68	0	12	0	0
T70	0	8	0	0
T261	0	8	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1285	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	32	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	29	0	0
T27	0	9	0	0
T45	0	6	0	0
T46	0	10	0	0
T51	0	12	0	0
T53	0	7	0	0
T68	0	12	0	0
T70	0	8	0	0
T261	0	8	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	876	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	32	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	9	0	0
T46	0	10	0	0
T53	0	5	0	0
T70	0	8	0	0
T76	0	19	0	0
T177	0	27	0	0
T183	0	13	0	0
T185	0	6	0	0
T261	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	876	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	32	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	9	0	0
T46	0	10	0	0
T53	0	5	0	0
T70	0	8	0	0
T76	0	19	0	0
T177	0	27	0	0
T183	0	13	0	0
T185	0	6	0	0
T261	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	70829	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	3536	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	2272	0	0
T46	0	614	0	0
T53	0	325	0	0
T70	0	938	0	0
T76	0	361	0	0
T177	0	2398	0	0
T183	0	441	0	0
T185	0	162	0	0
T261	0	757	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	742	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	26	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	2	0	0
T46	0	10	0	0
T53	0	4	0	0
T70	0	8	0	0
T76	0	19	0	0
T177	0	27	0	0
T183	0	10	0	0
T185	0	6	0	0
T261	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T4
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T4
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T4,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T14,T4,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T4,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T4
1	0	Covered	T6,T1,T14
1	1	Covered	T14,T4,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T4,T12
0	1	Covered	T63,T73,T266
1	0	Covered	T53,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T4,T12
0	1	Covered	T14,T4,T12
1	0	Covered	T74,T267

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T4,T12
1	-	Covered	T14,T4,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T4,T12
DetectSt	168	Covered	T14,T4,T12
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T14,T4,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T4,T12
DebounceSt->IdleSt	163	Covered	T4,T12,T33
DetectSt->IdleSt	186	Covered	T63,T53,T73
DetectSt->StableSt	191	Covered	T14,T4,T12
IdleSt->DebounceSt	148	Covered	T14,T4,T12
StableSt->IdleSt	206	Covered	T14,T4,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T4,T12
0	1	Covered	T14,T4,T12
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T4,T12
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T4,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T4,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T12,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T4,T12
DetectSt	-	-	-	-	1	-	-	Covered	T63,T53,T73
DetectSt	-	-	-	-	0	1	-	Covered	T14,T4,T12
DetectSt	-	-	-	-	0	0	-	Covered	T14,T4,T12
StableSt	-	-	-	-	-	-	1	Covered	T14,T4,T12
StableSt	-	-	-	-	-	-	0	Covered	T14,T4,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	798	0	0
CntIncr_A	7194251	42910	0	0
CntNoWrap_A	7194251	6506974	0	0
DetectStDropOut_A	7194251	70	0	0
DetectedOut_A	7194251	13570	0	0
DetectedPulseOut_A	7194251	303	0	0
DisabledIdleSt_A	7194251	6148989	0	0
DisabledNoDetection_A	7194251	6150765	0	0
EnterDebounceSt_A	7194251	422	0	0
EnterDetectSt_A	7194251	377	0	0
EnterStableSt_A	7194251	303	0	0
PulseIsPulse_A	7194251	303	0	0
StayInStableSt	7194251	13236	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	266	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	798	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	7	0	0
T8	1409	0	0	0
T12	0	21	0	0
T14	25334	10	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	6	0	0
T30	0	18	0	0
T31	0	5	0	0
T32	0	5	0	0
T33	0	13	0	0
T48	0	2	0	0
T63	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	42910	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	497	0	0
T8	1409	0	0	0
T12	0	2458	0	0
T14	25334	420	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	255	0	0
T30	0	1122	0	0
T31	0	322	0	0
T32	0	452	0	0
T33	0	289	0	0
T48	0	97	0	0
T63	0	261	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6506974	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24878	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	70	0	0
T53	6684	0	0	0
T63	18279	2	0	0
T68	4570	0	0	0
T71	2395	0	0	0
T73	33216	1	0	0
T86	0	4	0	0
T87	0	11	0	0
T89	0	1	0	0
T91	0	14	0	0
T266	0	5	0	0
T268	0	3	0	0
T269	0	7	0	0
T270	0	2	0	0
T271	22930	0	0	0
T272	635	0	0	0
T273	1225	0	0	0
T274	661	0	0	0
T275	773	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	13570	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	126	0	0
T8	1409	0	0	0
T12	0	166	0	0
T14	25334	263	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	133	0	0
T30	0	423	0	0
T31	0	107	0	0
T32	0	62	0	0
T33	0	109	0	0
T48	0	85	0	0
T271	0	13	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	303	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	3	0	0
T8	1409	0	0	0
T12	0	10	0	0
T14	25334	5	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	3	0	0
T30	0	8	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	6	0	0
T48	0	1	0	0
T271	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6148989	0	0
T1	10715	2574	0	0
T2	8283	3221	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	21320	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6150765	0	0
T1	10715	2598	0	0
T2	8283	3233	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	21322	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	422	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	4	0	0
T8	1409	0	0	0
T12	0	11	0	0
T14	25334	5	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	3	0	0
T30	0	10	0	0
T31	0	3	0	0
T32	0	3	0	0
T33	0	7	0	0
T48	0	1	0	0
T63	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	377	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	3	0	0
T8	1409	0	0	0
T12	0	10	0	0
T14	25334	5	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	3	0	0
T30	0	8	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	6	0	0
T48	0	1	0	0
T63	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	303	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	3	0	0
T8	1409	0	0	0
T12	0	10	0	0
T14	25334	5	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	3	0	0
T30	0	8	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	6	0	0
T48	0	1	0	0
T271	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	303	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	3	0	0
T8	1409	0	0	0
T12	0	10	0	0
T14	25334	5	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	3	0	0
T30	0	8	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	6	0	0
T48	0	1	0	0
T271	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	13236	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	123	0	0
T8	1409	0	0	0
T12	0	156	0	0
T14	25334	254	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	130	0	0
T30	0	415	0	0
T31	0	105	0	0
T32	0	60	0	0
T33	0	103	0	0
T48	0	84	0	0
T271	0	12	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	266	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	3	0	0
T8	1409	0	0	0
T12	0	10	0	0
T14	25334	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T27	0	3	0	0
T30	0	8	0	0
T31	0	2	0	0
T32	0	2	0	0
T33	0	6	0	0
T48	0	1	0	0
T271	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T26,T27
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T26,T27
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T26,T27
0	1	Covered	T68,T53,T70
1	0	Covered	T53,T70,T76

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T26,T27
0	1	Covered	T14,T26,T27
1	0	Covered	T70,T76,T276

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T26,T27
1	-	Covered	T14,T26,T27

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T26,T27
DetectSt	168	Covered	T14,T26,T27
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T14,T26,T27

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T26,T27
DebounceSt->IdleSt	163	Covered	T53,T69,T257
DetectSt->IdleSt	186	Covered	T68,T53,T70
DetectSt->StableSt	191	Covered	T14,T26,T27
IdleSt->DebounceSt	148	Covered	T14,T26,T27
StableSt->IdleSt	206	Covered	T14,T26,T27

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T26,T27
0	1	Covered	T14,T26,T27
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T26,T27
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T14,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T69,T257
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T68,T53,T70
DetectSt	-	-	-	-	0	1	-	Covered	T14,T26,T27
DetectSt	-	-	-	-	0	0	-	Covered	T14,T26,T27
StableSt	-	-	-	-	-	-	1	Covered	T14,T26,T27
StableSt	-	-	-	-	-	-	0	Covered	T14,T26,T27
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	2713	0	0
CntIncr_A	7194251	99312	0	0
CntNoWrap_A	7194251	6505059	0	0
DetectStDropOut_A	7194251	195	0	0
DetectedOut_A	7194251	86814	0	0
DetectedPulseOut_A	7194251	940	0	0
DisabledIdleSt_A	7194251	6031307	0	0
DisabledNoDetection_A	7194251	6033577	0	0
EnterDebounceSt_A	7194251	1366	0	0
EnterDetectSt_A	7194251	1348	0	0
EnterStableSt_A	7194251	940	0	0
PulseIsPulse_A	7194251	940	0	0
StayInStableSt	7194251	85745	0	0
gen_high_event_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	798	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	2713	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	64	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	14	0	0
T27	0	18	0	0
T45	0	20	0	0
T46	0	10	0	0
T51	0	20	0	0
T53	0	16	0	0
T68	0	20	0	0
T69	0	23	0	0
T70	0	18	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	99312	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	2240	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	637	0	0
T27	0	432	0	0
T45	0	310	0	0
T46	0	405	0	0
T51	0	640	0	0
T53	0	496	0	0
T68	0	385	0	0
T69	0	4837	0	0
T70	0	748	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6505059	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24824	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	195	0	0
T53	6684	1	0	0
T68	4570	10	0	0
T70	0	4	0	0
T71	2395	0	0	0
T73	33216	0	0	0
T74	0	1	0	0
T76	0	4	0	0
T84	0	13	0	0
T263	0	14	0	0
T271	22930	0	0	0
T272	635	0	0	0
T273	1225	0	0	0
T274	661	0	0	0
T275	773	0	0	0
T277	0	10	0	0
T278	0	3	0	0
T279	0	7	0	0
T280	2902	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	86814	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	3958	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1332	0	0
T27	0	2396	0	0
T45	0	767	0	0
T46	0	340	0	0
T51	0	794	0	0
T53	0	289	0	0
T69	0	1238	0	0
T70	0	1	0	0
T261	0	2108	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	940	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	32	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	7	0	0
T27	0	9	0	0
T45	0	10	0	0
T46	0	5	0	0
T51	0	10	0	0
T53	0	5	0	0
T69	0	9	0	0
T70	0	1	0	0
T261	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6031307	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	16289	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6033577	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	16290	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1366	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	32	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	7	0	0
T27	0	9	0	0
T45	0	10	0	0
T46	0	5	0	0
T51	0	10	0	0
T53	0	9	0	0
T68	0	10	0	0
T69	0	15	0	0
T70	0	9	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1348	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	32	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	7	0	0
T27	0	9	0	0
T45	0	10	0	0
T46	0	5	0	0
T51	0	10	0	0
T53	0	7	0	0
T68	0	10	0	0
T69	0	9	0	0
T70	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	940	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	32	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	7	0	0
T27	0	9	0	0
T45	0	10	0	0
T46	0	5	0	0
T51	0	10	0	0
T53	0	5	0	0
T69	0	9	0	0
T70	0	1	0	0
T261	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	940	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	32	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	7	0	0
T27	0	9	0	0
T45	0	10	0	0
T46	0	5	0	0
T51	0	10	0	0
T53	0	5	0	0
T69	0	9	0	0
T70	0	1	0	0
T261	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	85745	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	3920	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1324	0	0
T27	0	2380	0	0
T45	0	757	0	0
T46	0	335	0	0
T51	0	782	0	0
T53	0	284	0	0
T69	0	1229	0	0
T177	0	337	0	0
T261	0	2082	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	798	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	26	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	6	0	0
T27	0	2	0	0
T45	0	10	0	0
T46	0	5	0	0
T51	0	8	0	0
T53	0	5	0	0
T69	0	9	0	0
T177	0	7	0	0
T261	0	22	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T4
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T4
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T4,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T14,T4,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T4,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T4
1	0	Covered	T6,T1,T14
1	1	Covered	T14,T4,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T4,T12
0	1	Covered	T270,T211,T281
1	0	Covered	T53,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T4,T12
0	1	Covered	T4,T12,T26
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T4,T12
1	-	Covered	T4,T12,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T4,T12
DetectSt	168	Covered	T14,T4,T12
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T14,T4,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T4,T12
DebounceSt->IdleSt	163	Covered	T12,T48,T33
DetectSt->IdleSt	186	Covered	T53,T282,T270
DetectSt->StableSt	191	Covered	T14,T4,T12
IdleSt->DebounceSt	148	Covered	T14,T4,T12
StableSt->IdleSt	206	Covered	T14,T4,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T4,T12
0	1	Covered	T14,T4,T12
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T4,T12
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T4,T12
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T4,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T12,T48,T33
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T4,T12
DetectSt	-	-	-	-	1	-	-	Covered	T53,T270,T211
DetectSt	-	-	-	-	0	1	-	Covered	T14,T4,T12
DetectSt	-	-	-	-	0	0	-	Covered	T14,T4,T12
StableSt	-	-	-	-	-	-	1	Covered	T4,T12,T26
StableSt	-	-	-	-	-	-	0	Covered	T14,T4,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	858	0	0
CntIncr_A	7194251	45143	0	0
CntNoWrap_A	7194251	6506914	0	0
DetectStDropOut_A	7194251	42	0	0
DetectedOut_A	7194251	20923	0	0
DetectedPulseOut_A	7194251	353	0	0
DisabledIdleSt_A	7194251	6155955	0	0
DisabledNoDetection_A	7194251	6157770	0	0
EnterDebounceSt_A	7194251	461	0	0
EnterDetectSt_A	7194251	400	0	0
EnterStableSt_A	7194251	353	0	0
PulseIsPulse_A	7194251	353	0	0
StayInStableSt	7194251	20523	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	302	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	858	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	12	0	0
T8	1409	0	0	0
T12	0	4	0	0
T14	25334	6	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	2	0	0
T27	0	14	0	0
T30	0	6	0	0
T31	0	5	0	0
T32	0	22	0	0
T33	0	5	0	0
T48	0	13	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	45143	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	672	0	0
T8	1409	0	0	0
T12	0	618	0	0
T14	25334	216	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	104	0	0
T27	0	553	0	0
T30	0	501	0	0
T31	0	330	0	0
T32	0	1380	0	0
T33	0	139	0	0
T48	0	684	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6506914	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24882	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	42	0	0
T145	520	0	0	0
T158	707	0	0	0
T211	0	5	0	0
T260	25437	0	0	0
T270	6451	1	0	0
T281	0	9	0	0
T283	0	6	0	0
T284	0	1	0	0
T285	0	2	0	0
T286	0	5	0	0
T287	0	1	0	0
T288	0	6	0	0
T289	0	1	0	0
T290	36708	0	0	0
T291	504	0	0	0
T292	490	0	0	0
T293	712	0	0	0
T294	523	0	0	0
T295	426	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	20923	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	437	0	0
T8	1409	0	0	0
T12	0	21	0	0
T14	25334	193	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	54	0	0
T27	0	358	0	0
T30	0	23	0	0
T31	0	116	0	0
T32	0	904	0	0
T33	0	10	0	0
T48	0	483	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	353	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	6	0	0
T8	1409	0	0	0
T12	0	1	0	0
T14	25334	3	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1	0	0
T27	0	7	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	10	0	0
T33	0	2	0	0
T48	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6155955	0	0
T1	10715	2574	0	0
T2	8283	3221	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	20936	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6157770	0	0
T1	10715	2598	0	0
T2	8283	3233	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	20938	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	461	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	6	0	0
T8	1409	0	0	0
T12	0	3	0	0
T14	25334	3	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1	0	0
T27	0	7	0	0
T30	0	3	0	0
T31	0	3	0	0
T32	0	12	0	0
T33	0	3	0	0
T48	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	400	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	6	0	0
T8	1409	0	0	0
T12	0	1	0	0
T14	25334	3	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1	0	0
T27	0	7	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	10	0	0
T33	0	2	0	0
T48	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	353	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	6	0	0
T8	1409	0	0	0
T12	0	1	0	0
T14	25334	3	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1	0	0
T27	0	7	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	10	0	0
T33	0	2	0	0
T48	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	353	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	6	0	0
T8	1409	0	0	0
T12	0	1	0	0
T14	25334	3	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1	0	0
T27	0	7	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	10	0	0
T33	0	2	0	0
T48	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	20523	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	431	0	0
T8	1409	0	0	0
T12	0	20	0	0
T14	25334	187	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	53	0	0
T27	0	351	0	0
T30	0	20	0	0
T31	0	114	0	0
T32	0	894	0	0
T33	0	8	0	0
T48	0	477	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	302	0	0
T4	21648	6	0	0
T8	1409	0	0	0
T9	4783	0	0	0
T10	1525	0	0	0
T11	1039	0	0	0
T12	28453	1	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1	0	0
T27	0	7	0	0
T30	0	3	0	0
T31	0	2	0	0
T32	0	10	0	0
T33	0	2	0	0
T48	0	6	0	0
T98	450	0	0	0
T271	0	1	0	0