Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T26,T27
1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T26,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T26,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T26,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T26,T27
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T26,T27
0	1	Covered	T27,T45,T51
1	0	Covered	T27,T45,T51

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T26,T46
0	1	Covered	T14,T26,T46
1	0	Covered	T296,T297

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T26,T46
1	-	Covered	T14,T26,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T26,T27
DetectSt	168	Covered	T14,T26,T27
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T14,T26,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T26,T27
DebounceSt->IdleSt	163	Covered	T53,T69,T257
DetectSt->IdleSt	186	Covered	T27,T45,T51
DetectSt->StableSt	191	Covered	T14,T26,T46
IdleSt->DebounceSt	148	Covered	T14,T26,T27
StableSt->IdleSt	206	Covered	T14,T26,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T26,T27
0	1	Covered	T14,T26,T27
0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T26,T27
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T26,T27
IdleSt	0	-	-	-	-	-	-	Covered	T14,T26,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T26,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T53,T69,T257
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T26,T27
DetectSt	-	-	-	-	1	-	-	Covered	T27,T45,T51
DetectSt	-	-	-	-	0	1	-	Covered	T14,T26,T46
DetectSt	-	-	-	-	0	0	-	Covered	T14,T26,T27
StableSt	-	-	-	-	-	-	1	Covered	T14,T26,T46
StableSt	-	-	-	-	-	-	0	Covered	T14,T26,T46
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	2859	0	0
CntIncr_A	7194251	96525	0	0
CntNoWrap_A	7194251	6504913	0	0
DetectStDropOut_A	7194251	247	0	0
DetectedOut_A	7194251	85292	0	0
DetectedPulseOut_A	7194251	986	0	0
DisabledIdleSt_A	7194251	6033913	0	0
DisabledNoDetection_A	7194251	6036206	0	0
EnterDebounceSt_A	7194251	1441	0	0
EnterDetectSt_A	7194251	1420	0	0
EnterStableSt_A	7194251	986	0	0
PulseIsPulse_A	7194251	986	0	0
StayInStableSt	7194251	84200	0	0
gen_high_event_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	876	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	2859	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	40	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	22	0	0
T27	0	48	0	0
T45	0	14	0	0
T46	0	30	0	0
T51	0	54	0	0
T53	0	16	0	0
T68	0	58	0	0
T69	0	23	0	0
T70	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	96525	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	1540	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	935	0	0
T27	0	1688	0	0
T45	0	364	0	0
T46	0	1485	0	0
T51	0	2130	0	0
T53	0	482	0	0
T68	0	1127	0	0
T69	0	4522	0	0
T70	0	553	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6504913	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24848	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	247	0	0
T27	22498	15	0	0
T30	23627	0	0	0
T31	37784	0	0	0
T32	34195	0	0	0
T45	6346	3	0	0
T50	746	0	0	0
T51	0	12	0	0
T53	0	1	0	0
T57	740	0	0	0
T58	807	0	0	0
T68	0	29	0	0
T74	0	1	0	0
T84	0	12	0	0
T121	405	0	0	0
T122	521	0	0	0
T277	0	3	0	0
T278	0	12	0	0
T298	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	85292	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	1767	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	614	0	0
T46	0	2029	0	0
T53	0	351	0	0
T69	0	1553	0	0
T70	0	894	0	0
T76	0	1239	0	0
T177	0	726	0	0
T183	0	464	0	0
T261	0	2971	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	986	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	20	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	11	0	0
T46	0	15	0	0
T53	0	5	0	0
T69	0	9	0	0
T70	0	7	0	0
T76	0	27	0	0
T177	0	16	0	0
T183	0	9	0	0
T261	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6033913	0	0
T1	10715	2574	0	0
T2	8283	3698	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	17713	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6036206	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	17718	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1441	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	20	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	11	0	0
T27	0	24	0	0
T45	0	7	0	0
T46	0	15	0	0
T51	0	27	0	0
T53	0	9	0	0
T68	0	29	0	0
T69	0	15	0	0
T70	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	1420	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	20	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	11	0	0
T27	0	24	0	0
T45	0	7	0	0
T46	0	15	0	0
T51	0	27	0	0
T53	0	7	0	0
T68	0	29	0	0
T69	0	9	0	0
T70	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	986	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	20	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	11	0	0
T46	0	15	0	0
T53	0	5	0	0
T69	0	9	0	0
T70	0	7	0	0
T76	0	27	0	0
T177	0	16	0	0
T183	0	9	0	0
T261	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	986	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	20	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	11	0	0
T46	0	15	0	0
T53	0	5	0	0
T69	0	9	0	0
T70	0	7	0	0
T76	0	27	0	0
T177	0	16	0	0
T183	0	9	0	0
T261	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	84200	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	1745	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	602	0	0
T46	0	2014	0	0
T53	0	346	0	0
T69	0	1544	0	0
T70	0	887	0	0
T76	0	1212	0	0
T177	0	710	0	0
T183	0	453	0	0
T261	0	2942	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	876	0	0
T2	8283	0	0	0
T3	2437	0	0	0
T4	21648	0	0	0
T8	1409	0	0	0
T14	25334	18	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	10	0	0
T46	0	15	0	0
T53	0	5	0	0
T69	0	9	0	0
T70	0	7	0	0
T76	0	27	0	0
T177	0	16	0	0
T183	0	7	0	0
T261	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T14,T2,T4
1	Covered	T5,T6,T7

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T4
1	0	Covered	T5,T6,T7
1	1	Covered	T5,T6,T7

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T4

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T5,T6,T7	VC_COV_UNR
1	Covered	T14,T2,T4

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T5,T6,T7
1	Covered	T14,T2,T4

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T4
1	0	Covered	T6,T1,T14
1	1	Covered	T14,T2,T4

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T4
0	1	Covered	T299,T93,T94
1	0	Covered	T53,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T4
0	1	Covered	T14,T2,T4
1	0	Covered	T70,T300,T301

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T2,T4
1	-	Covered	T14,T2,T4

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T4
DetectSt	168	Covered	T14,T2,T4
IdleSt	163	Covered	T5,T6,T7
StableSt	191	Covered	T14,T2,T4

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T4
DebounceSt->IdleSt	163	Covered	T48,T32,T30
DetectSt->IdleSt	186	Covered	T53,T74,T299
DetectSt->StableSt	191	Covered	T14,T2,T4
IdleSt->DebounceSt	148	Covered	T14,T2,T4
StableSt->IdleSt	206	Covered	T14,T2,T4

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T2,T4
0	1	Covered	T14,T2,T4
0	0	Excluded	T5,T6,T7	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T4
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T4
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T7
DebounceSt	-	1	-	-	-	-	-	Covered	T53,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T4
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T32,T30
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T4
DetectSt	-	-	-	-	1	-	-	Covered	T53,T74,T299
DetectSt	-	-	-	-	0	1	-	Covered	T14,T2,T4
DetectSt	-	-	-	-	0	0	-	Covered	T14,T2,T4
StableSt	-	-	-	-	-	-	1	Covered	T14,T2,T4
StableSt	-	-	-	-	-	-	0	Covered	T14,T2,T4
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T5,T6,T7
0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7194251	839	0	0
CntIncr_A	7194251	47784	0	0
CntNoWrap_A	7194251	6506933	0	0
DetectStDropOut_A	7194251	60	0	0
DetectedOut_A	7194251	15930	0	0
DetectedPulseOut_A	7194251	336	0	0
DisabledIdleSt_A	7194251	6133923	0	0
DisabledNoDetection_A	7194251	6135713	0	0
EnterDebounceSt_A	7194251	439	0	0
EnterDetectSt_A	7194251	400	0	0
EnterStableSt_A	7194251	336	0	0
PulseIsPulse_A	7194251	336	0	0
StayInStableSt	7194251	15570	0	0
gen_high_level_sva.HighLevelEvent_A	7194251	6510260	0	0
gen_not_sticky_sva.StableStDropOut_A	7194251	303	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	839	0	0
T2	8283	2	0	0
T3	2437	0	0	0
T4	21648	8	0	0
T8	1409	0	0	0
T12	0	16	0	0
T14	25334	6	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	2	0	0
T30	0	13	0	0
T31	0	2	0	0
T32	0	9	0	0
T33	0	4	0	0
T48	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	47784	0	0
T2	8283	157	0	0
T3	2437	0	0	0
T4	21648	612	0	0
T8	1409	0	0	0
T12	0	1872	0	0
T14	25334	171	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	74	0	0
T30	0	1033	0	0
T31	0	138	0	0
T32	0	876	0	0
T33	0	92	0	0
T48	0	249	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6506933	0	0
T1	10715	2574	0	0
T2	8283	3696	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	24882	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	60	0	0
T92	719	0	0	0
T93	0	10	0	0
T94	0	6	0	0
T287	0	9	0	0
T299	18283	5	0	0
T302	0	11	0	0
T303	0	4	0	0
T304	0	1	0	0
T305	0	7	0	0
T306	0	4	0	0
T307	0	1	0	0
T308	402	0	0	0
T309	7807	0	0	0
T310	49518	0	0	0
T311	574	0	0	0
T312	491	0	0	0
T313	499	0	0	0
T314	495	0	0	0
T315	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	15930	0	0
T2	8283	60	0	0
T3	2437	0	0	0
T4	21648	124	0	0
T8	1409	0	0	0
T12	0	74	0	0
T14	25334	240	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	84	0	0
T30	0	87	0	0
T31	0	35	0	0
T32	0	56	0	0
T33	0	33	0	0
T48	0	5	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	336	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	4	0	0
T8	1409	0	0	0
T12	0	8	0	0
T14	25334	3	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1	0	0
T30	0	6	0	0
T31	0	1	0	0
T32	0	4	0	0
T33	0	2	0	0
T48	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6133923	0	0
T1	10715	2574	0	0
T2	8283	3221	0	0
T3	2437	2036	0	0
T5	526	125	0	0
T6	8487	66	0	0
T7	503	102	0	0
T14	25334	23123	0	0
T15	424	23	0	0
T16	422	21	0	0
T20	451	50	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6135713	0	0
T1	10715	2598	0	0
T2	8283	3233	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	23129	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	439	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	4	0	0
T8	1409	0	0	0
T12	0	8	0	0
T14	25334	3	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1	0	0
T30	0	7	0	0
T31	0	1	0	0
T32	0	5	0	0
T33	0	2	0	0
T48	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	400	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	4	0	0
T8	1409	0	0	0
T12	0	8	0	0
T14	25334	3	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1	0	0
T30	0	6	0	0
T31	0	1	0	0
T32	0	4	0	0
T33	0	2	0	0
T48	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	336	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	4	0	0
T8	1409	0	0	0
T12	0	8	0	0
T14	25334	3	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1	0	0
T30	0	6	0	0
T31	0	1	0	0
T32	0	4	0	0
T33	0	2	0	0
T48	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	336	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	4	0	0
T8	1409	0	0	0
T12	0	8	0	0
T14	25334	3	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1	0	0
T30	0	6	0	0
T31	0	1	0	0
T32	0	4	0	0
T33	0	2	0	0
T48	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	15570	0	0
T2	8283	59	0	0
T3	2437	0	0	0
T4	21648	120	0	0
T8	1409	0	0	0
T12	0	66	0	0
T14	25334	235	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	83	0	0
T30	0	81	0	0
T31	0	34	0	0
T32	0	52	0	0
T33	0	31	0	0
T48	0	4	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	6510260	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7194251	303	0	0
T2	8283	1	0	0
T3	2437	0	0	0
T4	21648	4	0	0
T8	1409	0	0	0
T12	0	8	0	0
T14	25334	1	0	0
T15	424	0	0	0
T16	422	0	0	0
T17	402	0	0	0
T18	502	0	0	0
T19	797	0	0	0
T26	0	1	0	0
T30	0	6	0	0
T31	0	1	0	0
T32	0	4	0	0
T33	0	2	0	0
T48	0	1	0	0