Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1196858631	9639	0	0
auto_block_debounce_ctl_rd_A	1196858631	1546	0	0
auto_block_out_ctl_rd_A	1196858631	2287	0	0
com_det_ctl_0_rd_A	1196858631	4038	0	0
com_det_ctl_1_rd_A	1196858631	4183	0	0
com_det_ctl_2_rd_A	1196858631	4188	0	0
com_det_ctl_3_rd_A	1196858631	4194	0	0
com_out_ctl_0_rd_A	1196858631	4774	0	0
com_out_ctl_1_rd_A	1196858631	4668	0	0
com_out_ctl_2_rd_A	1196858631	4483	0	0
com_out_ctl_3_rd_A	1196858631	4518	0	0
com_pre_det_ctl_0_rd_A	1196858631	1031	0	0
com_pre_det_ctl_1_rd_A	1196858631	1123	0	0
com_pre_det_ctl_2_rd_A	1196858631	1036	0	0
com_pre_det_ctl_3_rd_A	1196858631	973	0	0
com_pre_sel_ctl_0_rd_A	1196858631	4773	0	0
com_pre_sel_ctl_1_rd_A	1196858631	4829	0	0
com_pre_sel_ctl_2_rd_A	1196858631	5008	0	0
com_pre_sel_ctl_3_rd_A	1196858631	4559	0	0
com_sel_ctl_0_rd_A	1196858631	4818	0	0
com_sel_ctl_1_rd_A	1196858631	4483	0	0
com_sel_ctl_2_rd_A	1196858631	4800	0	0
com_sel_ctl_3_rd_A	1196858631	4733	0	0
ec_rst_ctl_rd_A	1196858631	2456	0	0
intr_enable_rd_A	1196858631	1393	0	0
key_intr_ctl_rd_A	1196858631	2951	0	0
key_intr_debounce_ctl_rd_A	1196858631	1074	0	0
key_invert_ctl_rd_A	1196858631	4742	0	0
pin_allowed_ctl_rd_A	1196858631	4896	0	0
pin_out_ctl_rd_A	1196858631	3824	0	0
pin_out_value_rd_A	1196858631	3872	0	0
regwen_rd_A	1196858631	1103	0	0
ulp_ac_debounce_ctl_rd_A	1196858631	1283	0	0
ulp_ctl_rd_A	1196858631	1314	0	0
ulp_lid_debounce_ctl_rd_A	1196858631	1145	0	0
ulp_pwrb_debounce_ctl_rd_A	1196858631	1130	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	9639	0	0
T1	535765	11	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T9	0	1	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	10	0	0
T37	0	23	0	0
T38	0	5	0	0
T41	0	6	0	0
T44	0	3	0	0
T77	0	1	0	0
T80	0	15	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1546	0	0
T1	535765	33	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	16	0	0
T41	0	36	0	0
T44	0	18	0	0
T50	0	9	0	0
T52	0	7	0	0
T77	0	26	0	0
T80	0	47	0	0
T176	0	10	0	0
T337	0	5	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	2287	0	0
T1	535765	36	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	19	0	0
T41	0	33	0	0
T44	0	12	0	0
T50	0	16	0	0
T52	0	9	0	0
T77	0	26	0	0
T80	0	35	0	0
T176	0	1	0	0
T337	0	6	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4038	0	0
T1	535765	14	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	38	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	55	0	0
T41	0	20	0	0
T44	0	15	0	0
T51	0	57	0	0
T80	0	22	0	0
T177	0	35	0	0
T183	0	91	0	0
T185	0	43	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4183	0	0
T1	535765	34	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	26	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	74	0	0
T41	0	32	0	0
T44	0	19	0	0
T51	0	48	0	0
T80	0	19	0	0
T177	0	37	0	0
T183	0	66	0	0
T185	0	35	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4188	0	0
T1	535765	30	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	31	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	57	0	0
T41	0	32	0	0
T44	0	2	0	0
T51	0	87	0	0
T80	0	18	0	0
T177	0	43	0	0
T183	0	103	0	0
T185	0	25	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4194	0	0
T1	535765	31	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	38	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	62	0	0
T41	0	33	0	0
T44	0	27	0	0
T51	0	48	0	0
T80	0	31	0	0
T177	0	51	0	0
T183	0	82	0	0
T185	0	27	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4774	0	0
T1	535765	27	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	23	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	80	0	0
T41	0	28	0	0
T44	0	12	0	0
T51	0	72	0	0
T80	0	38	0	0
T177	0	41	0	0
T183	0	93	0	0
T185	0	39	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4668	0	0
T1	535765	18	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	42	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	62	0	0
T41	0	32	0	0
T44	0	3	0	0
T51	0	56	0	0
T80	0	21	0	0
T177	0	44	0	0
T183	0	92	0	0
T185	0	55	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4483	0	0
T1	535765	28	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	29	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	102	0	0
T41	0	39	0	0
T44	0	21	0	0
T51	0	57	0	0
T80	0	11	0	0
T177	0	59	0	0
T183	0	68	0	0
T185	0	65	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4518	0	0
T1	535765	24	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	54	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	72	0	0
T41	0	38	0	0
T44	0	12	0	0
T51	0	43	0	0
T80	0	29	0	0
T177	0	59	0	0
T183	0	74	0	0
T185	0	24	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1031	0	0
T1	535765	18	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	15	0	0
T41	0	33	0	0
T44	0	13	0	0
T77	0	5	0	0
T80	0	29	0	0
T128	0	23	0	0
T135	0	8	0	0
T210	0	11	0	0
T338	0	31	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1123	0	0
T1	535765	30	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	27	0	0
T41	0	38	0	0
T44	0	24	0	0
T77	0	17	0	0
T80	0	31	0	0
T116	0	8	0	0
T128	0	31	0	0
T135	0	1	0	0
T210	0	11	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1036	0	0
T1	535765	26	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	6	0	0
T41	0	36	0	0
T44	0	2	0	0
T77	0	14	0	0
T80	0	12	0	0
T116	0	2	0	0
T128	0	30	0	0
T135	0	7	0	0
T210	0	8	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	973	0	0
T1	535765	31	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	15	0	0
T41	0	31	0	0
T44	0	16	0	0
T77	0	13	0	0
T80	0	34	0	0
T116	0	9	0	0
T128	0	41	0	0
T135	0	5	0	0
T210	0	19	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4773	0	0
T1	535765	26	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	48	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	66	0	0
T41	0	49	0	0
T44	0	16	0	0
T51	0	53	0	0
T80	0	17	0	0
T177	0	50	0	0
T183	0	79	0	0
T185	0	45	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4829	0	0
T1	535765	45	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	51	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	66	0	0
T41	0	51	0	0
T44	0	6	0	0
T51	0	43	0	0
T80	0	18	0	0
T177	0	26	0	0
T183	0	68	0	0
T185	0	18	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	5008	0	0
T1	535765	41	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	64	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	80	0	0
T41	0	27	0	0
T44	0	24	0	0
T51	0	45	0	0
T80	0	20	0	0
T177	0	46	0	0
T183	0	128	0	0
T185	0	54	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4559	0	0
T1	535765	27	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	37	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	63	0	0
T41	0	32	0	0
T44	0	1	0	0
T51	0	54	0	0
T80	0	15	0	0
T177	0	38	0	0
T183	0	95	0	0
T185	0	24	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4818	0	0
T1	535765	32	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	39	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	74	0	0
T41	0	32	0	0
T44	0	25	0	0
T51	0	46	0	0
T80	0	20	0	0
T177	0	39	0	0
T183	0	109	0	0
T185	0	48	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4483	0	0
T1	535765	20	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	48	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	76	0	0
T41	0	29	0	0
T44	0	26	0	0
T51	0	63	0	0
T80	0	11	0	0
T177	0	70	0	0
T183	0	109	0	0
T185	0	33	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4800	0	0
T1	535765	28	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	44	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	75	0	0
T41	0	39	0	0
T44	0	9	0	0
T51	0	65	0	0
T80	0	22	0	0
T177	0	48	0	0
T183	0	86	0	0
T185	0	31	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4733	0	0
T1	535765	23	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	69	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	69	0	0
T41	0	40	0	0
T44	0	18	0	0
T51	0	74	0	0
T80	0	17	0	0
T177	0	39	0	0
T183	0	98	0	0
T185	0	42	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	2456	0	0
T1	535765	52	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T12	0	44	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T30	0	23	0	0
T41	0	50	0	0
T51	0	11	0	0
T53	0	2	0	0
T68	0	3	0	0
T80	0	44	0	0
T212	0	4	0	0
T274	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1393	0	0
T1	535765	60	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	11	0	0
T41	0	32	0	0
T44	0	27	0	0
T77	0	13	0	0
T80	0	16	0	0
T116	0	9	0	0
T128	0	35	0	0
T135	0	19	0	0
T339	0	27	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	2951	0	0
T1	535765	22	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T13	0	2	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T34	0	2	0	0
T36	0	3	0	0
T40	0	5	0	0
T41	0	34	0	0
T44	0	22	0	0
T53	0	76	0	0
T80	0	9	0	0
T176	0	4	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1074	0	0
T1	535765	13	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	17	0	0
T41	0	22	0	0
T44	0	13	0	0
T77	0	12	0	0
T80	0	12	0	0
T116	0	9	0	0
T128	0	32	0	0
T135	0	1	0	0
T210	0	19	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4742	0	0
T1	535765	169	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T25	0	35	0	0
T38	0	70	0	0
T41	0	95	0	0
T44	0	44	0	0
T61	0	36	0	0
T77	0	9	0	0
T80	0	59	0	0
T128	0	154	0	0
T187	0	67	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	4896	0	0
T1	535765	12	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	74	0	0
T41	0	206	0	0
T44	0	90	0	0
T80	0	91	0	0
T178	0	45	0	0
T181	0	79	0	0
T216	0	53	0	0
T340	0	87	0	0
T341	0	76	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	3824	0	0
T1	535765	23	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	31	0	0
T41	0	247	0	0
T44	0	76	0	0
T80	0	81	0	0
T178	0	24	0	0
T181	0	85	0	0
T216	0	71	0	0
T340	0	80	0	0
T341	0	50	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	3872	0	0
T1	535765	40	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	36	0	0
T41	0	220	0	0
T44	0	20	0	0
T80	0	99	0	0
T178	0	33	0	0
T181	0	78	0	0
T216	0	42	0	0
T340	0	84	0	0
T341	0	83	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1103	0	0
T1	535765	29	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	7	0	0
T41	0	33	0	0
T44	0	5	0	0
T77	0	8	0	0
T80	0	21	0	0
T116	0	2	0	0
T128	0	36	0	0
T135	0	9	0	0
T210	0	20	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1283	0	0
T1	535765	25	0	0
T2	947422	0	0	0
T3	244805	3	0	0
T4	541209	0	0	0
T10	0	10	0	0
T11	0	10	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	21	0	0
T41	0	46	0	0
T44	0	24	0	0
T58	0	8	0	0
T77	0	28	0	0
T80	0	18	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1314	0	0
T1	535765	19	0	0
T2	947422	0	0	0
T3	244805	12	0	0
T4	541209	0	0	0
T10	0	5	0	0
T11	0	15	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	26	0	0
T41	0	53	0	0
T44	0	28	0	0
T58	0	1	0	0
T72	0	1	0	0
T80	0	25	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1145	0	0
T1	535765	37	0	0
T2	947422	0	0	0
T3	244805	14	0	0
T4	541209	0	0	0
T10	0	8	0	0
T11	0	7	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	29	0	0
T41	0	29	0	0
T44	0	18	0	0
T58	0	5	0	0
T72	0	3	0	0
T80	0	16	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1130	0	0
T1	535765	17	0	0
T2	947422	0	0	0
T3	244805	13	0	0
T4	541209	0	0	0
T10	0	12	0	0
T11	0	8	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T38	0	16	0	0
T41	0	28	0	0
T44	0	17	0	0
T58	0	3	0	0
T72	0	11	0	0
T80	0	25	0	0