Unified Coverage Report :: Module :: prim_reg_cdc

Module : prim_reg_cdc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.30	100.00	89.20			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wkup_status_cdc	96.88	100.00	87.50			100.00	100.00
tb.dut.u_reg.u_ec_rst_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_invert_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_allowed_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_pin_out_value_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_key_intr_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_debounce_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_auto_block_out_ctl_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_pre_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_sel_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_det_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_0_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_1_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_2_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_com_out_ctl_3_cdc	97.73	100.00	90.91			100.00	100.00
tb.dut.u_reg.u_ulp_ctl_cdc	98.08	100.00	92.31			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_wkup_status_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.88	100.00	87.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.79	96.99	84.93			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_pin_out_value_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.33	100.00	93.33			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	97.73	100.00	90.91			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg.u_ulp_ctl_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.60	100.00	94.40			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ec_rst_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_allowed_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_invert_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_pin_out_value_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_key_intr_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_auto_block_out_ctl_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_sel_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_det_ctl_3_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_0_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_1_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_2_cdc

SCORE	COND
97.73	90.91

tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T7,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T7,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T7,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T7,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Cond Coverage for Module : prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )
Cond Coverage for Module self-instances :

SCORE	COND
98.08	92.31

tb.dut.u_reg.u_ulp_ctl_cdc

SCORE	COND
96.88	87.50

tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T10
1	-	Covered	T2,T3,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_reg_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T14,T2
0	0	1	Covered	T1,T14,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T14,T2
0	0	1	Covered	T1,T14,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Module : prim_reg_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	2147483647	107797077	0	0
DstReqKnown_A	253585124	223957626	0	0
SrcAckBusyChk_A	2147483647	120189	0	0
SrcBusyKnown_A	2147483647	2147483647	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	107797077	0	0
T1	6429180	11880	0	0
T2	28422660	9721	0	0
T3	8323370	0	0	0
T4	16777479	55072	0	0
T5	197274	0	0	0
T6	891171	0	0	0
T7	370215	0	0	0
T8	2511652	0	0	0
T9	1110000	25226	0	0
T10	943300	0	0	0
T11	558644	0	0	0
T12	1081212	23659	0	0
T14	3673488	120103	0	0
T15	1528590	0	0	0
T16	6207090	0	0	0
T17	6243338	0	0	0
T18	3818673	0	0	0
T19	1111753	0	0	0
T20	162639	0	0	0
T26	0	19424	0	0
T27	0	28607	0	0
T30	0	19219	0	0
T31	0	5777	0	0
T32	0	12103	0	0
T33	0	49192	0	0
T39	0	14483	0	0
T45	0	1438	0	0
T47	0	1189	0	0
T48	0	88792	0	0
T49	0	690	0	0
T50	0	10473	0	0
T51	0	976	0	0
T52	0	10430	0	0
T53	0	4015	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253585124	223957626	0	0
T1	364310	88332	0	0
T2	281622	126174	0	0
T3	82858	69258	0	0
T5	17884	4284	0	0
T6	288558	2958	0	0
T7	17102	3502	0	0
T14	861356	846464	0	0
T15	14416	816	0	0
T16	14348	748	0	0
T20	15334	1734	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	120189	0	0
T1	6429180	6	0	0
T2	28422660	23	0	0
T3	8323370	0	0	0
T4	16777479	64	0	0
T5	197274	0	0	0
T6	891171	0	0	0
T7	370215	0	0	0
T8	2511652	0	0	0
T9	1110000	14	0	0
T10	943300	0	0	0
T11	558644	0	0	0
T12	1081212	88	0	0
T14	3673488	72	0	0
T15	1528590	0	0	0
T16	6207090	0	0	0
T17	6243338	0	0	0
T18	3818673	0	0	0
T19	1111753	0	0	0
T20	162639	0	0	0
T26	0	45	0	0
T27	0	72	0	0
T30	0	54	0	0
T31	0	15	0	0
T32	0	84	0	0
T33	0	56	0	0
T39	0	8	0	0
T45	0	1	0	0
T47	0	7	0	0
T48	0	56	0	0
T49	0	8	0	0
T50	0	9	0	0
T51	0	6	0	0
T52	0	7	0	0
T53	0	12	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	18216010	18131554	0	0
T2	32212348	32113034	0	0
T3	8323370	8320174	0	0
T5	2235772	2232372	0	0
T6	10099938	10044926	0	0
T7	4195770	4192404	0	0
T14	4306848	4300354	0	0
T15	1732402	1729104	0	0
T16	7034702	7031710	0	0
T20	1843242	1840760	0	0

Line Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Covered	Percent
Conditions	16	14	87.50
Logical	16	14	87.50
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T2,T3,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T21,T54,T55
1	-	Covered	T2,T3,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T2,T3,T4
1	1	Covered	T2,T3,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Not Covered
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T2,T3,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T2,T3,T4
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_wkup_status_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	966431	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1189	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	966431	0	0
T2	947422	462	0	0
T3	244805	3718	0	0
T4	541209	9966	0	0
T8	114166	742	0	0
T9	222000	0	0	0
T10	0	1444	0	0
T11	0	2626	0	0
T12	0	2955	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	1059	0	0
T48	0	1487	0	0
T56	0	704	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1189	0	0
T2	947422	1	0	0
T3	244805	2	0	0
T4	541209	11	0	0
T8	114166	1	0	0
T9	222000	0	0	0
T10	0	1	0	0
T11	0	3	0	0
T12	0	10	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	2	0	0
T48	0	1	0	0
T56	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T14,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T14,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T14,T2
0	0	1	Covered	T1,T14,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T14,T2
0	0	1	Covered	T1,T14,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ec_rst_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1836788	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	2188	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1836788	0	0
T1	535765	7382	0	0
T2	947422	411	0	0
T3	244805	0	0	0
T4	541209	6812	0	0
T9	0	5361	0	0
T12	0	3161	0	0
T14	126672	13183	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	106	0	0
T26	0	2356	0	0
T41	0	2851	0	0
T48	0	10879	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	2188	0	0
T1	535765	4	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T9	0	3	0	0
T12	0	11	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	1	0	0
T26	0	5	0	0
T41	0	2	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T3,T8,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T3,T8,T10
1	1	Covered	T3,T8,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T3,T8,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T8,T10
1	1	Covered	T3,T8,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T3,T8,T10
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T3,T8,T10
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ac_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1043069	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1150	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1043069	0	0
T3	244805	5727	0	0
T4	541209	0	0	0
T8	114166	1497	0	0
T9	222000	0	0	0
T10	235825	5410	0	0
T11	139661	2699	0	0
T12	270303	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	694	0	0
T41	0	1436	0	0
T53	0	339	0	0
T56	0	715	0	0
T57	0	2000	0	0
T58	0	1941	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1150	0	0
T3	244805	3	0	0
T4	541209	0	0	0
T8	114166	2	0	0
T9	222000	0	0	0
T10	235825	3	0	0
T11	139661	3	0	0
T12	270303	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	2	0	0
T41	0	1	0	0
T53	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T3,T8,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T3,T8,T10
1	1	Covered	T3,T8,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T3,T8,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T8,T10
1	1	Covered	T3,T8,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T3,T8,T10
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T3,T8,T10
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_lid_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1054665	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1159	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1054665	0	0
T3	244805	5696	0	0
T4	541209	0	0	0
T8	114166	1493	0	0
T9	222000	0	0	0
T10	235825	5380	0	0
T11	139661	2666	0	0
T12	270303	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	678	0	0
T41	0	1426	0	0
T53	0	328	0	0
T56	0	711	0	0
T57	0	1998	0	0
T58	0	1932	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1159	0	0
T3	244805	3	0	0
T4	541209	0	0	0
T8	114166	2	0	0
T9	222000	0	0	0
T10	235825	3	0	0
T11	139661	3	0	0
T12	270303	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	2	0	0
T41	0	1	0	0
T53	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T3,T8,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T3,T8,T10
1	1	Covered	T3,T8,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T3,T8,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T8,T10
1	1	Covered	T3,T8,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T3,T8,T10
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T3,T8,T10
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_pwrb_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1014305	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1126	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1014305	0	0
T3	244805	5658	0	0
T4	541209	0	0	0
T8	114166	1489	0	0
T9	222000	0	0	0
T10	235825	5337	0	0
T11	139661	2630	0	0
T12	270303	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	668	0	0
T41	0	1414	0	0
T53	0	323	0	0
T56	0	707	0	0
T57	0	1996	0	0
T58	0	1923	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1126	0	0
T3	244805	3	0	0
T4	541209	0	0	0
T8	114166	2	0	0
T9	222000	0	0	0
T10	235825	3	0	0
T11	139661	3	0	0
T12	270303	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	2	0	0
T41	0	1	0	0
T53	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T25

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T25
1	1	Covered	T1,T2,T25

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T25

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T25
1	1	Covered	T1,T2,T25

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T25
0	0	1	Covered	T1,T2,T25
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T25
0	0	1	Covered	T1,T2,T25
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_invert_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	3258969	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	3335	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	3258969	0	0
T1	535765	69746	0	0
T2	947422	8306	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T25	0	17424	0	0
T41	0	32997	0	0
T59	0	31557	0	0
T60	0	8523	0	0
T61	0	27789	0	0
T62	0	36647	0	0
T63	0	16789	0	0
T64	0	8644	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	3335	0	0
T1	535765	40	0	0
T2	947422	20	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T25	0	20	0	0
T41	0	20	0	0
T59	0	20	0	0
T60	0	20	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T7,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T7,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T7,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T7,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T7,T1
0	0	1	Covered	T5,T7,T1
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T7,T1
0	0	1	Covered	T5,T7,T1
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_allowed_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	5941403	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	6544	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	5941403	0	0
T1	535765	72918	0	0
T2	947422	8454	0	0
T3	244805	0	0	0
T5	65758	8118	0	0
T6	297057	0	0	0
T7	123405	16763	0	0
T9	0	35116	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T18	0	17326	0	0
T20	54213	0	0	0
T25	0	930	0	0
T65	0	17571	0	0
T66	0	3821	0	0
T67	0	8010	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	6544	0	0
T1	535765	42	0	0
T2	947422	21	0	0
T3	244805	0	0	0
T5	65758	20	0	0
T6	297057	0	0	0
T7	123405	20	0	0
T9	0	20	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T18	0	20	0	0
T20	54213	0	0	0
T25	0	1	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T7,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T7,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T7,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T7,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T7,T1
0	0	1	Covered	T5,T7,T1
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T7,T1
0	0	1	Covered	T5,T7,T1
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	7026949	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	7758	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	7026949	0	0
T1	535765	82758	0	0
T2	947422	9593	0	0
T3	244805	0	0	0
T4	0	6979	0	0
T5	65758	8558	0	0
T6	297057	0	0	0
T7	123405	17052	0	0
T9	0	40347	0	0
T12	0	3392	0	0
T14	126672	13453	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T18	0	17406	0	0
T19	0	121	0	0
T20	54213	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	7758	0	0
T1	535765	46	0	0
T2	947422	23	0	0
T3	244805	0	0	0
T4	0	8	0	0
T5	65758	20	0	0
T6	297057	0	0	0
T7	123405	20	0	0
T9	0	23	0	0
T12	0	11	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T18	0	20	0	0
T19	0	1	0	0
T20	54213	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T7,T1

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T7,T1

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T5,T7,T1

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T5,T7,T1
1	1	Covered	T5,T7,T1

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T7,T1
0	0	1	Covered	T5,T7,T1
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T5,T7,T1
0	0	1	Covered	T5,T7,T1
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_pin_out_value_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	5863290	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	6414	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	5863290	0	0
T1	535765	69392	0	0
T2	947422	8135	0	0
T3	244805	0	0	0
T5	65758	8342	0	0
T6	297057	0	0	0
T7	123405	16915	0	0
T9	0	35262	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T18	0	17366	0	0
T20	54213	0	0	0
T41	0	156919	0	0
T65	0	17611	0	0
T66	0	3861	0	0
T67	0	8189	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	6414	0	0
T1	535765	40	0	0
T2	947422	20	0	0
T3	244805	0	0	0
T5	65758	20	0	0
T6	297057	0	0	0
T7	123405	20	0	0
T9	0	20	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T18	0	20	0	0
T20	54213	0	0	0
T41	0	97	0	0
T65	0	20	0	0
T66	0	20	0	0
T67	0	20	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T9
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T9
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1033493	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1168	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1033493	0	0
T1	535765	1973	0	0
T2	947422	477	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T9	0	1496	0	0
T13	0	722	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	353	0	0
T34	0	1411	0	0
T35	0	500	0	0
T36	0	787	0	0
T40	0	761	0	0
T41	0	1439	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1168	0	0
T1	535765	1	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T9	0	1	0	0
T13	0	1	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	1	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T14,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T14,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T14,T2
0	0	1	Covered	T1,T14,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T14,T2
0	0	1	Covered	T1,T14,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_key_intr_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1802663	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	2161	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1802663	0	0
T1	535765	3393	0	0
T2	947422	749	0	0
T3	244805	0	0	0
T4	541209	6796	0	0
T9	0	7336	0	0
T12	0	3158	0	0
T13	0	716	0	0
T14	126672	13167	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	2321	0	0
T40	0	753	0	0
T41	0	1430	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	2161	0	0
T1	535765	2	0	0
T2	947422	2	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T9	0	4	0	0
T12	0	11	0	0
T13	0	1	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T40	0	1	0	0
T41	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T9
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T9
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_debounce_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1396924	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1500	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1396924	0	0
T1	535765	3990	0	0
T2	947422	3797	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T9	0	8971	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	3438	0	0
T39	0	8993	0	0
T47	0	696	0	0
T49	0	422	0	0
T50	0	6784	0	0
T52	0	5980	0	0
T53	0	683	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1500	0	0
T1	535765	2	0	0
T2	947422	9	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T9	0	5	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	9	0	0
T39	0	5	0	0
T47	0	4	0	0
T49	0	5	0	0
T50	0	6	0	0
T52	0	4	0	0
T53	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T9

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T9

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T2,T9

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T9
1	1	Covered	T1,T2,T9

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T9
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T2,T9
0	0	1	Covered	T1,T2,T9
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_auto_block_out_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1202246	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1313	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1202246	0	0
T1	535765	3963	0	0
T2	947422	2464	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T9	0	5464	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	2339	0	0
T39	0	5490	0	0
T47	0	493	0	0
T49	0	268	0	0
T50	0	3689	0	0
T52	0	4450	0	0
T53	0	342	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1313	0	0
T1	535765	2	0	0
T2	947422	6	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T9	0	3	0	0
T14	126672	0	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	6	0	0
T39	0	3	0	0
T47	0	3	0	0
T49	0	3	0	0
T50	0	3	0	0
T52	0	3	0	0
T53	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	6666172	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	7209	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	6666172	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	128730	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	27925	0	0
T27	0	29300	0	0
T45	0	93910	0	0
T46	0	22288	0	0
T51	0	10143	0	0
T53	0	3866	0	0
T68	0	20753	0	0
T69	0	6922	0	0
T70	0	12837	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	7209	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	74	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	60	0	0
T27	0	67	0	0
T45	0	55	0	0
T46	0	52	0	0
T51	0	61	0	0
T53	0	11	0	0
T68	0	51	0	0
T69	0	51	0	0
T70	0	62	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	6745704	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	7327	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	6745704	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	118473	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	33810	0	0
T27	0	24535	0	0
T45	0	118631	0	0
T46	0	29813	0	0
T51	0	11386	0	0
T53	0	3855	0	0
T68	0	19737	0	0
T69	0	6712	0	0
T70	0	11069	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	7327	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	68	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	76	0	0
T27	0	58	0	0
T45	0	70	0	0
T46	0	69	0	0
T51	0	75	0	0
T53	0	11	0	0
T68	0	51	0	0
T69	0	51	0	0
T70	0	54	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	6572400	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	7269	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	6572400	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	118153	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	29641	0	0
T27	0	23600	0	0
T45	0	102103	0	0
T46	0	31688	0	0
T51	0	10563	0	0
T53	0	3867	0	0
T68	0	18745	0	0
T69	0	6502	0	0
T70	0	12361	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	7269	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	68	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	69	0	0
T27	0	58	0	0
T45	0	60	0	0
T46	0	74	0	0
T51	0	65	0	0
T53	0	11	0	0
T68	0	51	0	0
T69	0	51	0	0
T70	0	62	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	6510020	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	7175	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	6510020	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	137807	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	27183	0	0
T27	0	26517	0	0
T45	0	118104	0	0
T46	0	27236	0	0
T51	0	11629	0	0
T53	0	3864	0	0
T68	0	17907	0	0
T69	0	6292	0	0
T70	0	10807	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	7175	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	80	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	65	0	0
T27	0	67	0	0
T45	0	70	0	0
T46	0	64	0	0
T51	0	75	0	0
T53	0	11	0	0
T68	0	51	0	0
T69	0	51	0	0
T70	0	55	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1288660	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1395	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1288660	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	13487	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	2369	0	0
T27	0	3556	0	0
T45	0	1438	0	0
T46	0	499	0	0
T51	0	976	0	0
T53	0	2990	0	0
T68	0	346	0	0
T69	0	118	0	0
T70	0	178	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1395	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	0	6	0	0
T53	0	9	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1258636	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1374	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1258636	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	13407	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	2189	0	0
T27	0	3283	0	0
T45	0	1428	0	0
T46	0	489	0	0
T51	0	941	0	0
T53	0	2980	0	0
T68	0	300	0	0
T69	0	108	0	0
T70	0	168	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1374	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	0	6	0	0
T53	0	9	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1248442	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1387	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1248442	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	13327	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	2009	0	0
T27	0	2985	0	0
T45	0	1418	0	0
T46	0	479	0	0
T51	0	976	0	0
T53	0	2985	0	0
T68	0	360	0	0
T69	0	98	0	0
T70	0	158	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1387	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	0	6	0	0
T53	0	9	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T26,T27
1	1	Covered	T14,T26,T27

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T26,T27
0	0	1	Covered	T14,T26,T27
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_pre_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1228932	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1369	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1228932	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	13247	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	1954	0	0
T27	0	2976	0	0
T45	0	1408	0	0
T46	0	469	0	0
T51	0	973	0	0
T53	0	2978	0	0
T68	0	309	0	0
T69	0	88	0	0
T70	0	148	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1369	0	0
T2	947422	0	0	0
T3	244805	0	0	0
T4	541209	0	0	0
T8	114166	0	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T45	0	1	0	0
T46	0	1	0	0
T51	0	6	0	0
T53	0	9	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T14,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T14,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T14,T2
0	0	1	Covered	T1,T14,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T14,T2
0	0	1	Covered	T1,T14,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	7202035	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	7869	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	7202035	0	0
T1	535765	1978	0	0
T2	947422	478	0	0
T3	244805	0	0	0
T4	541209	7004	0	0
T9	0	5423	0	0
T12	0	3462	0	0
T14	126672	128830	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	28229	0	0
T27	0	29520	0	0
T33	0	6254	0	0
T48	0	11458	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	7869	0	0
T1	535765	1	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T9	0	3	0	0
T12	0	11	0	0
T14	126672	74	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	60	0	0
T27	0	67	0	0
T33	0	7	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	7182684	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	7903	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	7182684	0	0
T2	947422	467	0	0
T3	244805	0	0	0
T4	541209	6988	0	0
T8	114166	0	0	0
T12	0	3343	0	0
T14	126672	118561	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	34235	0	0
T27	0	24765	0	0
T30	0	3689	0	0
T32	0	2137	0	0
T33	0	6240	0	0
T48	0	11424	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	7903	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T8	114166	0	0	0
T12	0	11	0	0
T14	126672	68	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	76	0	0
T27	0	58	0	0
T30	0	9	0	0
T32	0	14	0	0
T33	0	7	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	6990929	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	7828	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	6990929	0	0
T2	947422	457	0	0
T3	244805	0	0	0
T4	541209	6972	0	0
T8	114166	0	0	0
T12	0	3239	0	0
T14	126672	118241	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	30071	0	0
T27	0	23781	0	0
T30	0	3588	0	0
T32	0	2056	0	0
T33	0	6226	0	0
T48	0	11382	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	7828	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T8	114166	0	0	0
T12	0	11	0	0
T14	126672	68	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	69	0	0
T27	0	58	0	0
T30	0	9	0	0
T32	0	14	0	0
T33	0	7	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_sel_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	6947470	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	7777	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	6947470	0	0
T2	947422	452	0	0
T3	244805	0	0	0
T4	541209	6956	0	0
T8	114166	0	0	0
T12	0	3149	0	0
T14	126672	137919	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	27655	0	0
T27	0	26952	0	0
T30	0	3480	0	0
T32	0	1970	0	0
T33	0	6212	0	0
T48	0	11319	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	7777	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T8	114166	0	0	0
T12	0	11	0	0
T14	126672	80	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	65	0	0
T27	0	67	0	0
T30	0	9	0	0
T32	0	14	0	0
T33	0	7	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T14,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T14,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T14,T2
0	0	1	Covered	T1,T14,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T14,T2
0	0	1	Covered	T1,T14,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1789414	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	2100	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1789414	0	0
T1	535765	1969	0	0
T2	947422	450	0	0
T3	244805	0	0	0
T4	541209	6940	0	0
T9	0	5404	0	0
T12	0	3061	0	0
T14	126672	13455	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	2298	0	0
T27	0	3426	0	0
T33	0	6198	0	0
T48	0	11275	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	2100	0	0
T1	535765	1	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T9	0	3	0	0
T12	0	11	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T33	0	7	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1661939	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1981	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1661939	0	0
T2	947422	446	0	0
T3	244805	0	0	0
T4	541209	6924	0	0
T8	114166	0	0	0
T12	0	2977	0	0
T14	126672	13375	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	2097	0	0
T27	0	3150	0	0
T30	0	3294	0	0
T32	0	2026	0	0
T33	0	6184	0	0
T48	0	11218	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1981	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T8	114166	0	0	0
T12	0	11	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T30	0	9	0	0
T32	0	14	0	0
T33	0	7	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1642731	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1962	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1642731	0	0
T2	947422	442	0	0
T3	244805	0	0	0
T4	541209	6908	0	0
T8	114166	0	0	0
T12	0	2845	0	0
T14	126672	13295	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	1935	0	0
T27	0	2859	0	0
T30	0	3205	0	0
T32	0	2009	0	0
T33	0	6170	0	0
T48	0	11168	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1962	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T8	114166	0	0	0
T12	0	11	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T30	0	9	0	0
T32	0	14	0	0
T33	0	7	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_det_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1631301	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1978	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1631301	0	0
T2	947422	437	0	0
T3	244805	0	0	0
T4	541209	6892	0	0
T8	114166	0	0	0
T12	0	2852	0	0
T14	126672	13215	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	2142	0	0
T27	0	3139	0	0
T30	0	3101	0	0
T32	0	2089	0	0
T33	0	6156	0	0
T48	0	11120	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1978	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T8	114166	0	0	0
T12	0	11	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T30	0	9	0	0
T32	0	14	0	0
T33	0	7	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T14,T2

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T1,T14,T2

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T14,T2
1	1	Covered	T1,T14,T2

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T14,T2
0	0	1	Covered	T1,T14,T2
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T1,T14,T2
0	0	1	Covered	T1,T14,T2
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1799105	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	2135	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1799105	0	0
T1	535765	1958	0	0
T2	947422	431	0	0
T3	244805	0	0	0
T4	541209	6876	0	0
T9	0	5387	0	0
T12	0	2836	0	0
T14	126672	13439	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	2264	0	0
T27	0	3373	0	0
T33	0	6142	0	0
T48	0	11081	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	2135	0	0
T1	535765	1	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T9	0	3	0	0
T12	0	11	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T33	0	7	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1646277	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1992	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1646277	0	0
T2	947422	421	0	0
T3	244805	0	0	0
T4	541209	6860	0	0
T8	114166	0	0	0
T12	0	2906	0	0
T14	126672	13359	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	2058	0	0
T27	0	3090	0	0
T30	0	2918	0	0
T32	0	1954	0	0
T33	0	6128	0	0
T48	0	11023	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1992	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T8	114166	0	0	0
T12	0	11	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T30	0	9	0	0
T32	0	14	0	0
T33	0	7	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1619501	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1965	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1619501	0	0
T2	947422	419	0	0
T3	244805	0	0	0
T4	541209	6844	0	0
T8	114166	0	0	0
T12	0	2999	0	0
T14	126672	13279	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	1886	0	0
T27	0	2802	0	0
T30	0	3167	0	0
T32	0	2024	0	0
T33	0	6114	0	0
T48	0	10980	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1965	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T8	114166	0	0	0
T12	0	11	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T30	0	9	0	0
T32	0	14	0	0
T33	0	7	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T14,T2,T4
1	1	Covered	T14,T2,T4

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T14,T2,T4
0	0	1	Covered	T14,T2,T4
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_com_out_ctl_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1673737	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	2011	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1673737	0	0
T2	947422	414	0	0
T3	244805	0	0	0
T4	541209	6828	0	0
T8	114166	0	0	0
T12	0	3183	0	0
T14	126672	13199	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	2375	0	0
T27	0	3212	0	0
T30	0	3534	0	0
T32	0	2001	0	0
T33	0	6100	0	0
T48	0	10927	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	2011	0	0
T2	947422	1	0	0
T3	244805	0	0	0
T4	541209	8	0	0
T8	114166	0	0	0
T12	0	11	0	0
T14	126672	8	0	0
T15	50953	0	0	0
T16	206903	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T26	0	5	0	0
T27	0	8	0	0
T30	0	9	0	0
T32	0	14	0	0
T33	0	7	0	0
T48	0	7	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0

Line Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	65	1	1	100.00
ALWAYS	71	6	6	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
ALWAYS	115	9	9	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	155	1	1	100.00
CONT_ASSIGN	156	1	1	100.00
CONT_ASSIGN	200	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
65	1	1
71	1	1
72	1	1
73	1	1
74	1	1
75	1	1
76	1	1
			MISSING_ELSE
85	1	1
109	1	1
115	1	1
116	1	1
117	1	1
118	1	1
123	1	1
124	1	1
125	1	1
134	1	1
135	1	1
			MISSING_ELSE
150	1	1
155	1	1
156	1	1
200	1	1

---

Cond Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       65
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T3,T8,T10

 LINE       109
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Covered	T3,T8,T10
1	1	Covered	T3,T8,T10

 LINE       123
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T10
1	-	Covered	T3,T8,T10

 LINE       125
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T6,T7
0	1	Unreachable
1	0	Covered	T3,T8,T10

 LINE       125
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T3,T8,T10
1	1	Covered	T3,T8,T10

 LINE       125
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	71	4	4	100.00
IF	115	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	71	if ((!rst_src_ni))
-2-:	73	if (src_req)
-3-:	75	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T3,T8,T10
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	115	if ((!rst_src_ni))
-2-:	118	if (src_req)
-3-:	125	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T5,T6,T7
0	1	-	Covered	T3,T8,T10
0	0	1	Covered	T3,T8,T10
0	0	0	Covered	T5,T6,T7

---

Assert Coverage for Instance : tb.dut.u_reg.u_ulp_ctl_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	1196858631	1049793	0	0
DstReqKnown_A	7458386	6586989	0	0
SrcAckBusyChk_A	1196858631	1178	0	0
SrcBusyKnown_A	1196858631	1195081651	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1049793	0	0
T3	244805	7087	0	0
T4	541209	0	0	0
T8	114166	1494	0	0
T9	222000	0	0	0
T10	235825	3433	0	0
T11	139661	5640	0	0
T12	270303	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	678	0	0
T53	0	1201	0	0
T56	0	1427	0	0
T58	0	3893	0	0
T71	0	798	0	0
T72	0	470	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7458386	6586989	0	0
T1	10715	2598	0	0
T2	8283	3711	0	0
T3	2437	2037	0	0
T5	526	126	0	0
T6	8487	87	0	0
T7	503	103	0	0
T14	25334	24896	0	0
T15	424	24	0	0
T16	422	22	0	0
T20	451	51	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1178	0	0
T3	244805	4	0	0
T4	541209	0	0	0
T8	114166	2	0	0
T9	222000	0	0	0
T10	235825	2	0	0
T11	139661	6	0	0
T12	270303	0	0	0
T17	201398	0	0	0
T18	123183	0	0	0
T19	35863	0	0	0
T31	0	2	0	0
T53	0	4	0	0
T56	0	4	0	0
T58	0	2	0	0
T71	0	2	0	0
T72	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1196858631	1195081651	0	0
T1	535765	533281	0	0
T2	947422	944501	0	0
T3	244805	244711	0	0
T5	65758	65658	0	0
T6	297057	295439	0	0
T7	123405	123306	0	0
T14	126672	126481	0	0
T15	50953	50856	0	0
T16	206903	206815	0	0
T20	54213	54140	0	0