Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
763 |
1 |
|
|
T2 |
9 |
|
T13 |
9 |
|
T22 |
7 |
| auto[1] |
837 |
1 |
|
|
T2 |
11 |
|
T13 |
11 |
|
T22 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
801 |
1 |
|
|
T2 |
14 |
|
T13 |
12 |
|
T22 |
7 |
| auto[1] |
799 |
1 |
|
|
T2 |
6 |
|
T13 |
8 |
|
T22 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
784 |
1 |
|
|
T2 |
9 |
|
T13 |
11 |
|
T22 |
11 |
| auto[1] |
816 |
1 |
|
|
T2 |
11 |
|
T13 |
9 |
|
T22 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
806 |
1 |
|
|
T2 |
10 |
|
T13 |
11 |
|
T22 |
10 |
| auto[1] |
794 |
1 |
|
|
T2 |
10 |
|
T13 |
9 |
|
T22 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
830 |
1 |
|
|
T2 |
8 |
|
T13 |
8 |
|
T22 |
10 |
| auto[1] |
770 |
1 |
|
|
T2 |
12 |
|
T13 |
12 |
|
T22 |
10 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T2 |
10 |
|
T13 |
11 |
|
T22 |
8 |
| auto[1] |
771 |
1 |
|
|
T2 |
10 |
|
T13 |
9 |
|
T22 |
12 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
781 |
1 |
|
|
T2 |
10 |
|
T13 |
8 |
|
T22 |
9 |
| auto[1] |
819 |
1 |
|
|
T2 |
10 |
|
T13 |
12 |
|
T22 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
793 |
1 |
|
|
T2 |
8 |
|
T13 |
12 |
|
T22 |
10 |
| auto[1] |
807 |
1 |
|
|
T2 |
12 |
|
T13 |
8 |
|
T22 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T2 |
12 |
|
T13 |
12 |
|
T22 |
12 |
| auto[1] |
768 |
1 |
|
|
T2 |
8 |
|
T13 |
8 |
|
T22 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
833 |
1 |
|
|
T2 |
13 |
|
T13 |
8 |
|
T22 |
14 |
| auto[1] |
767 |
1 |
|
|
T2 |
7 |
|
T13 |
12 |
|
T22 |
6 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
828 |
1 |
|
|
T2 |
12 |
|
T13 |
14 |
|
T22 |
12 |
| auto[1] |
772 |
1 |
|
|
T2 |
8 |
|
T13 |
6 |
|
T22 |
8 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
792 |
1 |
|
|
T2 |
12 |
|
T13 |
11 |
|
T22 |
10 |
| auto[1] |
808 |
1 |
|
|
T2 |
8 |
|
T13 |
9 |
|
T22 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
801 |
1 |
|
|
T2 |
9 |
|
T13 |
12 |
|
T22 |
10 |
| auto[1] |
799 |
1 |
|
|
T2 |
11 |
|
T13 |
8 |
|
T22 |
10 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
801 |
1 |
|
|
T2 |
14 |
|
T13 |
12 |
|
T22 |
7 |
| auto[1] |
799 |
1 |
|
|
T2 |
6 |
|
T13 |
8 |
|
T22 |
13 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
799 |
1 |
|
|
T2 |
9 |
|
T13 |
11 |
|
T22 |
9 |
| auto[1] |
801 |
1 |
|
|
T2 |
11 |
|
T13 |
9 |
|
T22 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
803 |
1 |
|
|
T2 |
10 |
|
T13 |
7 |
|
T22 |
10 |
| auto[1] |
797 |
1 |
|
|
T2 |
10 |
|
T13 |
13 |
|
T22 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
818 |
1 |
|
|
T2 |
12 |
|
T13 |
9 |
|
T22 |
8 |
| auto[1] |
782 |
1 |
|
|
T2 |
8 |
|
T13 |
11 |
|
T22 |
12 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
803 |
1 |
|
|
T2 |
8 |
|
T13 |
12 |
|
T22 |
8 |
| auto[1] |
797 |
1 |
|
|
T2 |
12 |
|
T13 |
8 |
|
T22 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
788 |
1 |
|
|
T2 |
9 |
|
T13 |
11 |
|
T22 |
9 |
| auto[1] |
812 |
1 |
|
|
T2 |
11 |
|
T13 |
9 |
|
T22 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
806 |
1 |
|
|
T2 |
9 |
|
T13 |
11 |
|
T22 |
12 |
| auto[1] |
794 |
1 |
|
|
T2 |
11 |
|
T13 |
9 |
|
T22 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
817 |
1 |
|
|
T2 |
9 |
|
T13 |
8 |
|
T22 |
9 |
| auto[1] |
783 |
1 |
|
|
T2 |
11 |
|
T13 |
12 |
|
T22 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
787 |
1 |
|
|
T2 |
12 |
|
T13 |
10 |
|
T22 |
11 |
| auto[1] |
813 |
1 |
|
|
T2 |
8 |
|
T13 |
10 |
|
T22 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
816 |
1 |
|
|
T2 |
9 |
|
T13 |
18 |
|
T22 |
11 |
| auto[1] |
784 |
1 |
|
|
T2 |
11 |
|
T13 |
2 |
|
T22 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
792 |
1 |
|
|
T2 |
12 |
|
T13 |
11 |
|
T22 |
10 |
| auto[1] |
808 |
1 |
|
|
T2 |
8 |
|
T13 |
9 |
|
T22 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
381 |
1 |
|
|
T2 |
4 |
|
T13 |
4 |
|
T22 |
6 |
| auto[0] |
auto[1] |
418 |
1 |
|
|
T2 |
5 |
|
T13 |
7 |
|
T22 |
3 |
| auto[1] |
auto[0] |
403 |
1 |
|
|
T2 |
5 |
|
T13 |
7 |
|
T22 |
5 |
| auto[1] |
auto[1] |
398 |
1 |
|
|
T2 |
6 |
|
T13 |
2 |
|
T22 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
394 |
1 |
|
|
T2 |
5 |
|
T13 |
2 |
|
T22 |
6 |
| auto[0] |
auto[1] |
409 |
1 |
|
|
T2 |
5 |
|
T13 |
5 |
|
T22 |
4 |
| auto[1] |
auto[0] |
412 |
1 |
|
|
T2 |
5 |
|
T13 |
9 |
|
T22 |
4 |
| auto[1] |
auto[1] |
385 |
1 |
|
|
T2 |
5 |
|
T13 |
4 |
|
T22 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
425 |
1 |
|
|
T2 |
4 |
|
T13 |
5 |
|
T22 |
5 |
| auto[0] |
auto[1] |
393 |
1 |
|
|
T2 |
8 |
|
T13 |
4 |
|
T22 |
3 |
| auto[1] |
auto[0] |
405 |
1 |
|
|
T2 |
4 |
|
T13 |
3 |
|
T22 |
5 |
| auto[1] |
auto[1] |
377 |
1 |
|
|
T2 |
4 |
|
T13 |
8 |
|
T22 |
7 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
417 |
1 |
|
|
T2 |
3 |
|
T13 |
8 |
|
T22 |
4 |
| auto[0] |
auto[1] |
386 |
1 |
|
|
T2 |
5 |
|
T13 |
4 |
|
T22 |
4 |
| auto[1] |
auto[0] |
412 |
1 |
|
|
T2 |
7 |
|
T13 |
3 |
|
T22 |
4 |
| auto[1] |
auto[1] |
385 |
1 |
|
|
T2 |
5 |
|
T13 |
5 |
|
T22 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
387 |
1 |
|
|
T2 |
5 |
|
T13 |
6 |
|
T22 |
4 |
| auto[0] |
auto[1] |
401 |
1 |
|
|
T2 |
4 |
|
T13 |
5 |
|
T22 |
5 |
| auto[1] |
auto[0] |
394 |
1 |
|
|
T2 |
5 |
|
T13 |
2 |
|
T22 |
5 |
| auto[1] |
auto[1] |
418 |
1 |
|
|
T2 |
6 |
|
T13 |
7 |
|
T22 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
402 |
1 |
|
|
T2 |
4 |
|
T13 |
8 |
|
T22 |
6 |
| auto[0] |
auto[1] |
404 |
1 |
|
|
T2 |
5 |
|
T13 |
3 |
|
T22 |
6 |
| auto[1] |
auto[0] |
391 |
1 |
|
|
T2 |
4 |
|
T13 |
4 |
|
T22 |
4 |
| auto[1] |
auto[1] |
403 |
1 |
|
|
T2 |
7 |
|
T13 |
5 |
|
T22 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
437 |
1 |
|
|
T2 |
9 |
|
T13 |
5 |
|
T22 |
9 |
| auto[0] |
auto[1] |
350 |
1 |
|
|
T2 |
3 |
|
T13 |
5 |
|
T22 |
2 |
| auto[1] |
auto[0] |
396 |
1 |
|
|
T2 |
4 |
|
T13 |
3 |
|
T22 |
5 |
| auto[1] |
auto[1] |
417 |
1 |
|
|
T2 |
4 |
|
T13 |
7 |
|
T22 |
4 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
449 |
1 |
|
|
T2 |
7 |
|
T13 |
12 |
|
T22 |
8 |
| auto[0] |
auto[1] |
367 |
1 |
|
|
T2 |
2 |
|
T13 |
6 |
|
T22 |
3 |
| auto[1] |
auto[0] |
379 |
1 |
|
|
T2 |
5 |
|
T13 |
2 |
|
T22 |
4 |
| auto[1] |
auto[1] |
405 |
1 |
|
|
T2 |
6 |
|
T22 |
5 |
|
T61 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
382 |
1 |
|
|
T2 |
5 |
|
T13 |
7 |
|
T22 |
4 |
| auto[0] |
auto[1] |
419 |
1 |
|
|
T2 |
4 |
|
T13 |
5 |
|
T22 |
6 |
| auto[1] |
auto[0] |
381 |
1 |
|
|
T2 |
4 |
|
T13 |
2 |
|
T22 |
3 |
| auto[1] |
auto[1] |
418 |
1 |
|
|
T2 |
7 |
|
T13 |
6 |
|
T22 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
801 |
1 |
|
|
T2 |
14 |
|
T13 |
12 |
|
T22 |
7 |
| auto[1] |
auto[1] |
799 |
1 |
|
|
T2 |
6 |
|
T13 |
8 |
|
T22 |
13 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
422 |
1 |
|
|
T2 |
7 |
|
T13 |
4 |
|
T22 |
5 |
| auto[0] |
auto[1] |
395 |
1 |
|
|
T2 |
2 |
|
T13 |
4 |
|
T22 |
4 |
| auto[1] |
auto[0] |
410 |
1 |
|
|
T2 |
5 |
|
T13 |
8 |
|
T22 |
7 |
| auto[1] |
auto[1] |
373 |
1 |
|
|
T2 |
6 |
|
T13 |
4 |
|
T22 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
792 |
1 |
|
|
T2 |
12 |
|
T13 |
11 |
|
T22 |
10 |
| auto[1] |
auto[1] |
808 |
1 |
|
|
T2 |
8 |
|
T13 |
9 |
|
T22 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
170 |
1 |
|
|
T2 |
10 |
|
T59 |
10 |
|
T45 |
10 |
| auto[1] |
130 |
1 |
|
|
T2 |
10 |
|
T59 |
10 |
|
T45 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T2 |
8 |
|
T59 |
8 |
|
T45 |
5 |
| auto[1] |
157 |
1 |
|
|
T2 |
12 |
|
T59 |
12 |
|
T45 |
15 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T2 |
4 |
|
T59 |
10 |
|
T45 |
12 |
| auto[1] |
151 |
1 |
|
|
T2 |
16 |
|
T59 |
10 |
|
T45 |
8 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T2 |
10 |
|
T59 |
16 |
|
T45 |
8 |
| auto[1] |
156 |
1 |
|
|
T2 |
10 |
|
T59 |
4 |
|
T45 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T2 |
7 |
|
T59 |
13 |
|
T45 |
13 |
| auto[1] |
147 |
1 |
|
|
T2 |
13 |
|
T59 |
7 |
|
T45 |
7 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
159 |
1 |
|
|
T2 |
11 |
|
T59 |
9 |
|
T45 |
7 |
| auto[1] |
141 |
1 |
|
|
T2 |
9 |
|
T59 |
11 |
|
T45 |
13 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
154 |
1 |
|
|
T2 |
10 |
|
T59 |
12 |
|
T45 |
5 |
| auto[1] |
146 |
1 |
|
|
T2 |
10 |
|
T59 |
8 |
|
T45 |
15 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
148 |
1 |
|
|
T2 |
9 |
|
T59 |
9 |
|
T45 |
11 |
| auto[1] |
152 |
1 |
|
|
T2 |
11 |
|
T59 |
11 |
|
T45 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T2 |
10 |
|
T59 |
10 |
|
T45 |
10 |
| auto[1] |
156 |
1 |
|
|
T2 |
10 |
|
T59 |
10 |
|
T45 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T2 |
13 |
|
T59 |
8 |
|
T45 |
8 |
| auto[1] |
150 |
1 |
|
|
T2 |
7 |
|
T59 |
12 |
|
T45 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
157 |
1 |
|
|
T2 |
10 |
|
T59 |
11 |
|
T45 |
6 |
| auto[1] |
143 |
1 |
|
|
T2 |
10 |
|
T59 |
9 |
|
T45 |
14 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T2 |
11 |
|
T59 |
9 |
|
T45 |
13 |
| auto[1] |
153 |
1 |
|
|
T2 |
9 |
|
T59 |
11 |
|
T45 |
7 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T2 |
7 |
|
T59 |
11 |
|
T45 |
6 |
| auto[1] |
151 |
1 |
|
|
T2 |
13 |
|
T59 |
9 |
|
T45 |
14 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T2 |
8 |
|
T59 |
8 |
|
T45 |
5 |
| auto[1] |
157 |
1 |
|
|
T2 |
12 |
|
T59 |
12 |
|
T45 |
15 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
128 |
1 |
|
|
T2 |
7 |
|
T59 |
7 |
|
T45 |
10 |
| auto[1] |
172 |
1 |
|
|
T2 |
13 |
|
T59 |
13 |
|
T45 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
135 |
1 |
|
|
T2 |
7 |
|
T59 |
11 |
|
T45 |
12 |
| auto[1] |
165 |
1 |
|
|
T2 |
13 |
|
T59 |
9 |
|
T45 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T2 |
10 |
|
T59 |
8 |
|
T45 |
7 |
| auto[1] |
156 |
1 |
|
|
T2 |
10 |
|
T59 |
12 |
|
T45 |
13 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T2 |
10 |
|
T59 |
4 |
|
T45 |
9 |
| auto[1] |
162 |
1 |
|
|
T2 |
10 |
|
T59 |
16 |
|
T45 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T2 |
7 |
|
T59 |
12 |
|
T45 |
5 |
| auto[1] |
158 |
1 |
|
|
T2 |
13 |
|
T59 |
8 |
|
T45 |
15 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T2 |
10 |
|
T59 |
9 |
|
T45 |
9 |
| auto[1] |
150 |
1 |
|
|
T2 |
10 |
|
T59 |
11 |
|
T45 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
118 |
1 |
|
|
T2 |
7 |
|
T59 |
6 |
|
T45 |
8 |
| auto[1] |
182 |
1 |
|
|
T2 |
13 |
|
T59 |
14 |
|
T45 |
12 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
134 |
1 |
|
|
T2 |
9 |
|
T59 |
12 |
|
T45 |
7 |
| auto[1] |
166 |
1 |
|
|
T2 |
11 |
|
T59 |
8 |
|
T45 |
13 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T2 |
8 |
|
T59 |
9 |
|
T45 |
9 |
| auto[1] |
157 |
1 |
|
|
T2 |
12 |
|
T59 |
11 |
|
T45 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T2 |
11 |
|
T59 |
9 |
|
T45 |
13 |
| auto[1] |
153 |
1 |
|
|
T2 |
9 |
|
T59 |
11 |
|
T45 |
7 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T2 |
1 |
|
T59 |
3 |
|
T45 |
6 |
| auto[0] |
auto[1] |
63 |
1 |
|
|
T2 |
6 |
|
T59 |
4 |
|
T45 |
4 |
| auto[1] |
auto[0] |
84 |
1 |
|
|
T2 |
3 |
|
T59 |
7 |
|
T45 |
6 |
| auto[1] |
auto[1] |
88 |
1 |
|
|
T2 |
10 |
|
T59 |
6 |
|
T45 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T2 |
4 |
|
T59 |
8 |
|
T45 |
5 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T2 |
3 |
|
T59 |
3 |
|
T45 |
7 |
| auto[1] |
auto[0] |
78 |
1 |
|
|
T2 |
6 |
|
T59 |
8 |
|
T45 |
3 |
| auto[1] |
auto[1] |
87 |
1 |
|
|
T2 |
7 |
|
T59 |
1 |
|
T45 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T2 |
5 |
|
T59 |
5 |
|
T45 |
5 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T2 |
5 |
|
T59 |
3 |
|
T45 |
2 |
| auto[1] |
auto[0] |
88 |
1 |
|
|
T2 |
2 |
|
T59 |
8 |
|
T45 |
8 |
| auto[1] |
auto[1] |
68 |
1 |
|
|
T2 |
8 |
|
T59 |
4 |
|
T45 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T2 |
7 |
|
T59 |
1 |
|
T45 |
3 |
| auto[0] |
auto[1] |
73 |
1 |
|
|
T2 |
3 |
|
T59 |
3 |
|
T45 |
6 |
| auto[1] |
auto[0] |
94 |
1 |
|
|
T2 |
4 |
|
T59 |
8 |
|
T45 |
4 |
| auto[1] |
auto[1] |
68 |
1 |
|
|
T2 |
6 |
|
T59 |
8 |
|
T45 |
7 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
70 |
1 |
|
|
T2 |
3 |
|
T59 |
7 |
|
T45 |
2 |
| auto[0] |
auto[1] |
72 |
1 |
|
|
T2 |
4 |
|
T59 |
5 |
|
T45 |
3 |
| auto[1] |
auto[0] |
84 |
1 |
|
|
T2 |
7 |
|
T59 |
5 |
|
T45 |
3 |
| auto[1] |
auto[1] |
74 |
1 |
|
|
T2 |
6 |
|
T59 |
3 |
|
T45 |
12 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
71 |
1 |
|
|
T2 |
4 |
|
T59 |
4 |
|
T45 |
7 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T2 |
6 |
|
T59 |
5 |
|
T45 |
2 |
| auto[1] |
auto[0] |
77 |
1 |
|
|
T2 |
5 |
|
T59 |
5 |
|
T45 |
4 |
| auto[1] |
auto[1] |
73 |
1 |
|
|
T2 |
5 |
|
T59 |
6 |
|
T45 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T2 |
6 |
|
T59 |
4 |
|
T45 |
2 |
| auto[0] |
auto[1] |
68 |
1 |
|
|
T2 |
3 |
|
T59 |
8 |
|
T45 |
5 |
| auto[1] |
auto[0] |
84 |
1 |
|
|
T2 |
7 |
|
T59 |
4 |
|
T45 |
6 |
| auto[1] |
auto[1] |
82 |
1 |
|
|
T2 |
4 |
|
T59 |
4 |
|
T45 |
7 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
74 |
1 |
|
|
T2 |
4 |
|
T59 |
4 |
|
T45 |
2 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T2 |
4 |
|
T59 |
5 |
|
T45 |
7 |
| auto[1] |
auto[0] |
83 |
1 |
|
|
T2 |
6 |
|
T59 |
7 |
|
T45 |
4 |
| auto[1] |
auto[1] |
74 |
1 |
|
|
T2 |
6 |
|
T59 |
4 |
|
T45 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
79 |
1 |
|
|
T2 |
3 |
|
T59 |
6 |
|
T45 |
2 |
| auto[0] |
auto[1] |
70 |
1 |
|
|
T2 |
4 |
|
T59 |
5 |
|
T45 |
4 |
| auto[1] |
auto[0] |
91 |
1 |
|
|
T2 |
7 |
|
T59 |
4 |
|
T45 |
8 |
| auto[1] |
auto[1] |
60 |
1 |
|
|
T2 |
6 |
|
T59 |
5 |
|
T45 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
143 |
1 |
|
|
T2 |
8 |
|
T59 |
8 |
|
T45 |
5 |
| auto[1] |
auto[1] |
157 |
1 |
|
|
T2 |
12 |
|
T59 |
12 |
|
T45 |
15 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T2 |
3 |
|
T59 |
3 |
|
T45 |
5 |
| auto[0] |
auto[1] |
52 |
1 |
|
|
T2 |
4 |
|
T59 |
3 |
|
T45 |
3 |
| auto[1] |
auto[0] |
78 |
1 |
|
|
T2 |
7 |
|
T59 |
7 |
|
T45 |
5 |
| auto[1] |
auto[1] |
104 |
1 |
|
|
T2 |
6 |
|
T59 |
7 |
|
T45 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
147 |
1 |
|
|
T2 |
11 |
|
T59 |
9 |
|
T45 |
13 |
| auto[1] |
auto[1] |
153 |
1 |
|
|
T2 |
9 |
|
T59 |
11 |
|
T45 |
7 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T34 |
4 |
|
T384 |
11 |
|
T162 |
10 |
| auto[1] |
58 |
1 |
|
|
T34 |
16 |
|
T384 |
9 |
|
T162 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
57 |
1 |
|
|
T34 |
10 |
|
T384 |
11 |
|
T162 |
13 |
| auto[1] |
43 |
1 |
|
|
T34 |
10 |
|
T384 |
9 |
|
T162 |
7 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
46 |
1 |
|
|
T34 |
13 |
|
T384 |
11 |
|
T162 |
11 |
| auto[1] |
54 |
1 |
|
|
T34 |
7 |
|
T384 |
9 |
|
T162 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
42 |
1 |
|
|
T34 |
8 |
|
T384 |
10 |
|
T162 |
7 |
| auto[1] |
58 |
1 |
|
|
T34 |
12 |
|
T384 |
10 |
|
T162 |
13 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
57 |
1 |
|
|
T34 |
14 |
|
T384 |
11 |
|
T162 |
14 |
| auto[1] |
43 |
1 |
|
|
T34 |
6 |
|
T384 |
9 |
|
T162 |
6 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
46 |
1 |
|
|
T34 |
9 |
|
T384 |
12 |
|
T162 |
10 |
| auto[1] |
54 |
1 |
|
|
T34 |
11 |
|
T384 |
8 |
|
T162 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
54 |
1 |
|
|
T34 |
8 |
|
T384 |
13 |
|
T162 |
9 |
| auto[1] |
46 |
1 |
|
|
T34 |
12 |
|
T384 |
7 |
|
T162 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
50 |
1 |
|
|
T34 |
13 |
|
T384 |
9 |
|
T162 |
9 |
| auto[1] |
50 |
1 |
|
|
T34 |
7 |
|
T384 |
11 |
|
T162 |
11 |