dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable cp_z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_z3_wakeup

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 120 1 T39 11 T28 12 T36 13
auto[1] 120 1 T39 9 T28 8 T36 7


Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_inXval

Bins
cp_key0_incfg.vif.key0_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 62 1 T39 8 T28 6 T36 5
auto[0] auto[1] 68 1 T39 6 T28 6 T36 4
auto[1] auto[0] 51 1 T39 3 T28 1 T36 4
auto[1] auto[1] 59 1 T39 3 T28 7 T36 7


Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_outXval

Bins
cp_key0_outcfg.vif.key0_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 54 1 T39 6 T28 3 T36 5
auto[0] auto[1] 55 1 T39 5 T28 3 T36 1
auto[1] auto[0] 64 1 T39 4 T28 4 T36 7
auto[1] auto[1] 67 1 T39 5 T28 10 T36 7


Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_inXval

Bins
cp_key1_incfg.vif.key1_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 56 1 T39 4 T28 4 T36 2
auto[0] auto[1] 60 1 T39 3 T28 9 T36 9
auto[1] auto[0] 59 1 T39 4 T28 5 T36 6
auto[1] auto[1] 65 1 T39 9 T28 2 T36 3


Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_outXval

Bins
cp_key1_outcfg.vif.key1_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 61 1 T39 8 T28 4 T36 3
auto[0] auto[1] 56 1 T39 6 T28 6 T36 7
auto[1] auto[0] 63 1 T39 1 T28 8 T36 8
auto[1] auto[1] 60 1 T39 5 T28 2 T36 2


Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_inXval

Bins
cp_key2_incfg.vif.key2_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 72 1 T39 5 T28 6 T36 8
auto[0] auto[1] 56 1 T39 2 T28 3 T36 5
auto[1] auto[0] 55 1 T39 7 T28 4 T36 3
auto[1] auto[1] 57 1 T39 6 T28 7 T36 4


Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_outXval

Bins
cp_key2_outcfg.vif.key2_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 72 1 T39 8 T28 7 T36 6
auto[0] auto[1] 61 1 T39 6 T28 5 T36 6
auto[1] auto[0] 50 1 T39 3 T28 2 T36 2
auto[1] auto[1] 57 1 T39 3 T28 6 T36 6


Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_inXval

Bins
cp_pwrb_incfg.vif.pwrb_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 59 1 T39 7 T28 6 T36 5
auto[0] auto[1] 66 1 T39 3 T28 4 T36 8
auto[1] auto[0] 56 1 T39 4 T28 3 T36 5
auto[1] auto[1] 59 1 T39 6 T28 7 T36 2


Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_outXval

Bins
cp_pwrb_outcfg.vif.pwrb_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 57 1 T39 6 T28 6 T36 2
auto[0] auto[1] 63 1 T39 2 T28 4 T36 8
auto[1] auto[0] 59 1 T39 5 T28 3 T36 5
auto[1] auto[1] 61 1 T39 7 T28 7 T36 5


Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for ac_presentXval

Bins
cp_ac_presentcfg.vif.ac_presentCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 58 1 T39 5 T28 7 T36 4
auto[0] auto[1] 59 1 T39 6 T28 3 T36 6
auto[1] auto[0] 59 1 T39 5 T28 4 T36 4
auto[1] auto[1] 64 1 T39 4 T28 6 T36 6


Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for bat_disableXval

Bins
cp_bat_disablecfg.vif.bat_disableCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 118 1 T39 9 T28 12 T36 6
auto[1] auto[1] 122 1 T39 11 T28 8 T36 14


User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded


Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for lid_openXval

Bins
cp_lid_opencfg.vif.lid_openCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 63 1 T39 3 T36 3 T218 6
auto[0] auto[1] 64 1 T39 7 T28 8 T36 6
auto[1] auto[0] 60 1 T39 5 T28 5 T36 5
auto[1] auto[1] 53 1 T39 5 T28 7 T36 6


Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for z3_wakeupXval

Bins
cp_z3_wakeupcfg.vif.z3_wakeupCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 120 1 T39 11 T28 12 T36 13
auto[1] auto[1] 120 1 T39 9 T28 8 T36 7


User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%