Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
781 |
1 |
|
|
T5 |
10 |
|
T25 |
11 |
|
T26 |
13 |
| auto[1] |
799 |
1 |
|
|
T5 |
10 |
|
T25 |
9 |
|
T26 |
7 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
795 |
1 |
|
|
T5 |
8 |
|
T25 |
12 |
|
T26 |
10 |
| auto[1] |
785 |
1 |
|
|
T5 |
12 |
|
T25 |
8 |
|
T26 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
808 |
1 |
|
|
T5 |
8 |
|
T25 |
10 |
|
T26 |
9 |
| auto[1] |
772 |
1 |
|
|
T5 |
12 |
|
T25 |
10 |
|
T26 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
789 |
1 |
|
|
T5 |
12 |
|
T25 |
9 |
|
T26 |
12 |
| auto[1] |
791 |
1 |
|
|
T5 |
8 |
|
T25 |
11 |
|
T26 |
8 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
788 |
1 |
|
|
T5 |
11 |
|
T25 |
13 |
|
T26 |
6 |
| auto[1] |
792 |
1 |
|
|
T5 |
9 |
|
T25 |
7 |
|
T26 |
14 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
841 |
1 |
|
|
T5 |
14 |
|
T25 |
11 |
|
T26 |
11 |
| auto[1] |
739 |
1 |
|
|
T5 |
6 |
|
T25 |
9 |
|
T26 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
802 |
1 |
|
|
T5 |
12 |
|
T25 |
10 |
|
T26 |
8 |
| auto[1] |
778 |
1 |
|
|
T5 |
8 |
|
T25 |
10 |
|
T26 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
787 |
1 |
|
|
T5 |
10 |
|
T25 |
8 |
|
T26 |
7 |
| auto[1] |
793 |
1 |
|
|
T5 |
10 |
|
T25 |
12 |
|
T26 |
13 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
761 |
1 |
|
|
T5 |
7 |
|
T25 |
13 |
|
T26 |
12 |
| auto[1] |
819 |
1 |
|
|
T5 |
13 |
|
T25 |
7 |
|
T26 |
8 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
772 |
1 |
|
|
T5 |
11 |
|
T25 |
9 |
|
T26 |
9 |
| auto[1] |
808 |
1 |
|
|
T5 |
9 |
|
T25 |
11 |
|
T26 |
11 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
772 |
1 |
|
|
T5 |
12 |
|
T25 |
13 |
|
T26 |
13 |
| auto[1] |
808 |
1 |
|
|
T5 |
8 |
|
T25 |
7 |
|
T26 |
7 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
762 |
1 |
|
|
T5 |
10 |
|
T25 |
12 |
|
T26 |
8 |
| auto[1] |
818 |
1 |
|
|
T5 |
10 |
|
T25 |
8 |
|
T26 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
806 |
1 |
|
|
T5 |
11 |
|
T25 |
10 |
|
T26 |
9 |
| auto[1] |
774 |
1 |
|
|
T5 |
9 |
|
T25 |
10 |
|
T26 |
11 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
795 |
1 |
|
|
T5 |
8 |
|
T25 |
12 |
|
T26 |
10 |
| auto[1] |
785 |
1 |
|
|
T5 |
12 |
|
T25 |
8 |
|
T26 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
779 |
1 |
|
|
T5 |
10 |
|
T25 |
12 |
|
T26 |
12 |
| auto[1] |
801 |
1 |
|
|
T5 |
10 |
|
T25 |
8 |
|
T26 |
8 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
800 |
1 |
|
|
T5 |
10 |
|
T25 |
11 |
|
T26 |
9 |
| auto[1] |
780 |
1 |
|
|
T5 |
10 |
|
T25 |
9 |
|
T26 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
815 |
1 |
|
|
T5 |
9 |
|
T25 |
11 |
|
T26 |
13 |
| auto[1] |
765 |
1 |
|
|
T5 |
11 |
|
T25 |
9 |
|
T26 |
7 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
784 |
1 |
|
|
T5 |
8 |
|
T25 |
9 |
|
T26 |
14 |
| auto[1] |
796 |
1 |
|
|
T5 |
12 |
|
T25 |
11 |
|
T26 |
6 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
815 |
1 |
|
|
T5 |
13 |
|
T25 |
13 |
|
T26 |
9 |
| auto[1] |
765 |
1 |
|
|
T5 |
7 |
|
T25 |
7 |
|
T26 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
792 |
1 |
|
|
T5 |
13 |
|
T25 |
11 |
|
T26 |
10 |
| auto[1] |
788 |
1 |
|
|
T5 |
7 |
|
T25 |
9 |
|
T26 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
806 |
1 |
|
|
T5 |
10 |
|
T25 |
9 |
|
T26 |
10 |
| auto[1] |
774 |
1 |
|
|
T5 |
10 |
|
T25 |
11 |
|
T26 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
783 |
1 |
|
|
T5 |
10 |
|
T25 |
9 |
|
T26 |
7 |
| auto[1] |
797 |
1 |
|
|
T5 |
10 |
|
T25 |
11 |
|
T26 |
13 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
783 |
1 |
|
|
T5 |
9 |
|
T25 |
9 |
|
T26 |
11 |
| auto[1] |
797 |
1 |
|
|
T5 |
11 |
|
T25 |
11 |
|
T26 |
9 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
762 |
1 |
|
|
T5 |
10 |
|
T25 |
12 |
|
T26 |
8 |
| auto[1] |
818 |
1 |
|
|
T5 |
10 |
|
T25 |
8 |
|
T26 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
408 |
1 |
|
|
T5 |
5 |
|
T25 |
7 |
|
T26 |
5 |
| auto[0] |
auto[1] |
371 |
1 |
|
|
T5 |
5 |
|
T25 |
5 |
|
T26 |
7 |
| auto[1] |
auto[0] |
400 |
1 |
|
|
T5 |
3 |
|
T25 |
3 |
|
T26 |
4 |
| auto[1] |
auto[1] |
401 |
1 |
|
|
T5 |
7 |
|
T25 |
5 |
|
T26 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
409 |
1 |
|
|
T5 |
7 |
|
T25 |
6 |
|
T26 |
5 |
| auto[0] |
auto[1] |
391 |
1 |
|
|
T5 |
3 |
|
T25 |
5 |
|
T26 |
4 |
| auto[1] |
auto[0] |
380 |
1 |
|
|
T5 |
5 |
|
T25 |
3 |
|
T26 |
7 |
| auto[1] |
auto[1] |
400 |
1 |
|
|
T5 |
5 |
|
T25 |
6 |
|
T26 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
413 |
1 |
|
|
T5 |
5 |
|
T25 |
8 |
|
T26 |
4 |
| auto[0] |
auto[1] |
402 |
1 |
|
|
T5 |
4 |
|
T25 |
3 |
|
T26 |
9 |
| auto[1] |
auto[0] |
375 |
1 |
|
|
T5 |
6 |
|
T25 |
5 |
|
T26 |
2 |
| auto[1] |
auto[1] |
390 |
1 |
|
|
T5 |
5 |
|
T25 |
4 |
|
T26 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
424 |
1 |
|
|
T5 |
6 |
|
T25 |
6 |
|
T26 |
7 |
| auto[0] |
auto[1] |
360 |
1 |
|
|
T5 |
2 |
|
T25 |
3 |
|
T26 |
7 |
| auto[1] |
auto[0] |
417 |
1 |
|
|
T5 |
8 |
|
T25 |
5 |
|
T26 |
4 |
| auto[1] |
auto[1] |
379 |
1 |
|
|
T5 |
4 |
|
T25 |
6 |
|
T26 |
2 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
413 |
1 |
|
|
T5 |
8 |
|
T25 |
6 |
|
T26 |
4 |
| auto[0] |
auto[1] |
402 |
1 |
|
|
T5 |
5 |
|
T25 |
7 |
|
T26 |
5 |
| auto[1] |
auto[0] |
389 |
1 |
|
|
T5 |
4 |
|
T25 |
4 |
|
T26 |
4 |
| auto[1] |
auto[1] |
376 |
1 |
|
|
T5 |
3 |
|
T25 |
3 |
|
T26 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
394 |
1 |
|
|
T5 |
7 |
|
T25 |
4 |
|
T26 |
4 |
| auto[0] |
auto[1] |
398 |
1 |
|
|
T5 |
6 |
|
T25 |
7 |
|
T26 |
6 |
| auto[1] |
auto[0] |
393 |
1 |
|
|
T5 |
3 |
|
T25 |
4 |
|
T26 |
3 |
| auto[1] |
auto[1] |
395 |
1 |
|
|
T5 |
4 |
|
T25 |
5 |
|
T26 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
374 |
1 |
|
|
T5 |
7 |
|
T25 |
5 |
|
T26 |
4 |
| auto[0] |
auto[1] |
409 |
1 |
|
|
T5 |
3 |
|
T25 |
4 |
|
T26 |
3 |
| auto[1] |
auto[0] |
398 |
1 |
|
|
T5 |
4 |
|
T25 |
4 |
|
T26 |
5 |
| auto[1] |
auto[1] |
399 |
1 |
|
|
T5 |
6 |
|
T25 |
7 |
|
T26 |
8 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
374 |
1 |
|
|
T5 |
7 |
|
T25 |
7 |
|
T26 |
8 |
| auto[0] |
auto[1] |
409 |
1 |
|
|
T5 |
2 |
|
T25 |
2 |
|
T26 |
3 |
| auto[1] |
auto[0] |
398 |
1 |
|
|
T5 |
5 |
|
T25 |
6 |
|
T26 |
5 |
| auto[1] |
auto[1] |
399 |
1 |
|
|
T5 |
6 |
|
T25 |
5 |
|
T26 |
4 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
407 |
1 |
|
|
T5 |
5 |
|
T25 |
7 |
|
T26 |
5 |
| auto[0] |
auto[1] |
399 |
1 |
|
|
T5 |
6 |
|
T25 |
3 |
|
T26 |
4 |
| auto[1] |
auto[0] |
374 |
1 |
|
|
T5 |
5 |
|
T25 |
4 |
|
T26 |
8 |
| auto[1] |
auto[1] |
400 |
1 |
|
|
T5 |
4 |
|
T25 |
6 |
|
T26 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
795 |
1 |
|
|
T5 |
8 |
|
T25 |
12 |
|
T26 |
10 |
| auto[1] |
auto[1] |
785 |
1 |
|
|
T5 |
12 |
|
T25 |
8 |
|
T26 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
380 |
1 |
|
|
T5 |
3 |
|
T25 |
6 |
|
T26 |
6 |
| auto[0] |
auto[1] |
426 |
1 |
|
|
T5 |
7 |
|
T25 |
3 |
|
T26 |
4 |
| auto[1] |
auto[0] |
381 |
1 |
|
|
T5 |
4 |
|
T25 |
7 |
|
T26 |
6 |
| auto[1] |
auto[1] |
393 |
1 |
|
|
T5 |
6 |
|
T25 |
4 |
|
T26 |
4 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
762 |
1 |
|
|
T5 |
10 |
|
T25 |
12 |
|
T26 |
8 |
| auto[1] |
auto[1] |
818 |
1 |
|
|
T5 |
10 |
|
T25 |
8 |
|
T26 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
81 |
1 |
|
|
T50 |
9 |
|
T70 |
10 |
|
T192 |
11 |
| auto[1] |
99 |
1 |
|
|
T50 |
11 |
|
T70 |
10 |
|
T192 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
86 |
1 |
|
|
T50 |
10 |
|
T70 |
9 |
|
T192 |
12 |
| auto[1] |
94 |
1 |
|
|
T50 |
10 |
|
T70 |
11 |
|
T192 |
8 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
95 |
1 |
|
|
T50 |
8 |
|
T70 |
11 |
|
T192 |
9 |
| auto[1] |
85 |
1 |
|
|
T50 |
12 |
|
T70 |
9 |
|
T192 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
95 |
1 |
|
|
T50 |
10 |
|
T70 |
11 |
|
T192 |
6 |
| auto[1] |
85 |
1 |
|
|
T50 |
10 |
|
T70 |
9 |
|
T192 |
14 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
85 |
1 |
|
|
T50 |
11 |
|
T70 |
10 |
|
T192 |
9 |
| auto[1] |
95 |
1 |
|
|
T50 |
9 |
|
T70 |
10 |
|
T192 |
11 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
93 |
1 |
|
|
T50 |
10 |
|
T70 |
12 |
|
T192 |
10 |
| auto[1] |
87 |
1 |
|
|
T50 |
10 |
|
T70 |
8 |
|
T192 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
100 |
1 |
|
|
T50 |
13 |
|
T70 |
10 |
|
T192 |
13 |
| auto[1] |
80 |
1 |
|
|
T50 |
7 |
|
T70 |
10 |
|
T192 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
90 |
1 |
|
|
T50 |
8 |
|
T70 |
12 |
|
T192 |
10 |
| auto[1] |
90 |
1 |
|
|
T50 |
12 |
|
T70 |
8 |
|
T192 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
90 |
1 |
|
|
T50 |
12 |
|
T70 |
8 |
|
T192 |
13 |
| auto[1] |
90 |
1 |
|
|
T50 |
8 |
|
T70 |
12 |
|
T192 |
7 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
99 |
1 |
|
|
T50 |
9 |
|
T70 |
14 |
|
T192 |
14 |
| auto[1] |
81 |
1 |
|
|
T50 |
11 |
|
T70 |
6 |
|
T192 |
6 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T50 |
8 |
|
T70 |
13 |
|
T192 |
11 |
| auto[1] |
96 |
1 |
|
|
T50 |
12 |
|
T70 |
7 |
|
T192 |
9 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
92 |
1 |
|
|
T50 |
7 |
|
T70 |
9 |
|
T192 |
13 |
| auto[1] |
88 |
1 |
|
|
T50 |
13 |
|
T70 |
11 |
|
T192 |
7 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
88 |
1 |
|
|
T50 |
9 |
|
T70 |
9 |
|
T192 |
11 |
| auto[1] |
92 |
1 |
|
|
T50 |
11 |
|
T70 |
11 |
|
T192 |
9 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
86 |
1 |
|
|
T50 |
10 |
|
T70 |
9 |
|
T192 |
12 |
| auto[1] |
94 |
1 |
|
|
T50 |
10 |
|
T70 |
11 |
|
T192 |
8 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
88 |
1 |
|
|
T50 |
10 |
|
T70 |
9 |
|
T192 |
11 |
| auto[1] |
92 |
1 |
|
|
T50 |
10 |
|
T70 |
11 |
|
T192 |
9 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
84 |
1 |
|
|
T50 |
8 |
|
T70 |
7 |
|
T192 |
8 |
| auto[1] |
96 |
1 |
|
|
T50 |
12 |
|
T70 |
13 |
|
T192 |
12 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T50 |
9 |
|
T70 |
8 |
|
T192 |
10 |
| auto[1] |
97 |
1 |
|
|
T50 |
11 |
|
T70 |
12 |
|
T192 |
10 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T50 |
12 |
|
T70 |
14 |
|
T192 |
11 |
| auto[1] |
89 |
1 |
|
|
T50 |
8 |
|
T70 |
6 |
|
T192 |
9 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
83 |
1 |
|
|
T50 |
10 |
|
T70 |
10 |
|
T192 |
8 |
| auto[1] |
97 |
1 |
|
|
T50 |
10 |
|
T70 |
10 |
|
T192 |
12 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
89 |
1 |
|
|
T50 |
9 |
|
T70 |
10 |
|
T192 |
11 |
| auto[1] |
91 |
1 |
|
|
T50 |
11 |
|
T70 |
10 |
|
T192 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
91 |
1 |
|
|
T50 |
12 |
|
T70 |
8 |
|
T192 |
15 |
| auto[1] |
89 |
1 |
|
|
T50 |
8 |
|
T70 |
12 |
|
T192 |
5 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
87 |
1 |
|
|
T50 |
9 |
|
T70 |
10 |
|
T192 |
10 |
| auto[1] |
93 |
1 |
|
|
T50 |
11 |
|
T70 |
10 |
|
T192 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
94 |
1 |
|
|
T50 |
10 |
|
T70 |
11 |
|
T192 |
9 |
| auto[1] |
86 |
1 |
|
|
T50 |
10 |
|
T70 |
9 |
|
T192 |
11 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
92 |
1 |
|
|
T50 |
7 |
|
T70 |
9 |
|
T192 |
13 |
| auto[1] |
88 |
1 |
|
|
T50 |
13 |
|
T70 |
11 |
|
T192 |
7 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
52 |
1 |
|
|
T50 |
5 |
|
T70 |
5 |
|
T192 |
7 |
| auto[0] |
auto[1] |
36 |
1 |
|
|
T50 |
5 |
|
T70 |
4 |
|
T192 |
4 |
| auto[1] |
auto[0] |
43 |
1 |
|
|
T50 |
3 |
|
T70 |
6 |
|
T192 |
2 |
| auto[1] |
auto[1] |
49 |
1 |
|
|
T50 |
7 |
|
T70 |
5 |
|
T192 |
7 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
50 |
1 |
|
|
T50 |
5 |
|
T70 |
4 |
|
T192 |
4 |
| auto[0] |
auto[1] |
34 |
1 |
|
|
T50 |
3 |
|
T70 |
3 |
|
T192 |
4 |
| auto[1] |
auto[0] |
45 |
1 |
|
|
T50 |
5 |
|
T70 |
7 |
|
T192 |
2 |
| auto[1] |
auto[1] |
51 |
1 |
|
|
T50 |
7 |
|
T70 |
6 |
|
T192 |
10 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
37 |
1 |
|
|
T50 |
4 |
|
T70 |
5 |
|
T192 |
4 |
| auto[0] |
auto[1] |
46 |
1 |
|
|
T50 |
5 |
|
T70 |
3 |
|
T192 |
6 |
| auto[1] |
auto[0] |
48 |
1 |
|
|
T50 |
7 |
|
T70 |
5 |
|
T192 |
5 |
| auto[1] |
auto[1] |
49 |
1 |
|
|
T50 |
4 |
|
T70 |
7 |
|
T192 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
45 |
1 |
|
|
T50 |
5 |
|
T70 |
9 |
|
T192 |
5 |
| auto[0] |
auto[1] |
46 |
1 |
|
|
T50 |
7 |
|
T70 |
5 |
|
T192 |
6 |
| auto[1] |
auto[0] |
48 |
1 |
|
|
T50 |
5 |
|
T70 |
3 |
|
T192 |
5 |
| auto[1] |
auto[1] |
41 |
1 |
|
|
T50 |
3 |
|
T70 |
3 |
|
T192 |
4 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
44 |
1 |
|
|
T50 |
5 |
|
T70 |
5 |
|
T192 |
4 |
| auto[0] |
auto[1] |
39 |
1 |
|
|
T50 |
5 |
|
T70 |
5 |
|
T192 |
4 |
| auto[1] |
auto[0] |
56 |
1 |
|
|
T50 |
8 |
|
T70 |
5 |
|
T192 |
9 |
| auto[1] |
auto[1] |
41 |
1 |
|
|
T50 |
2 |
|
T70 |
5 |
|
T192 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
42 |
1 |
|
|
T50 |
2 |
|
T70 |
6 |
|
T192 |
4 |
| auto[0] |
auto[1] |
47 |
1 |
|
|
T50 |
7 |
|
T70 |
4 |
|
T192 |
7 |
| auto[1] |
auto[0] |
48 |
1 |
|
|
T50 |
6 |
|
T70 |
6 |
|
T192 |
6 |
| auto[1] |
auto[1] |
43 |
1 |
|
|
T50 |
5 |
|
T70 |
4 |
|
T192 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
50 |
1 |
|
|
T50 |
4 |
|
T70 |
9 |
|
T192 |
7 |
| auto[0] |
auto[1] |
37 |
1 |
|
|
T50 |
5 |
|
T70 |
1 |
|
T192 |
3 |
| auto[1] |
auto[0] |
49 |
1 |
|
|
T50 |
5 |
|
T70 |
5 |
|
T192 |
7 |
| auto[1] |
auto[1] |
44 |
1 |
|
|
T50 |
6 |
|
T70 |
5 |
|
T192 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
46 |
1 |
|
|
T50 |
4 |
|
T70 |
9 |
|
T192 |
5 |
| auto[0] |
auto[1] |
48 |
1 |
|
|
T50 |
6 |
|
T70 |
2 |
|
T192 |
4 |
| auto[1] |
auto[0] |
38 |
1 |
|
|
T50 |
4 |
|
T70 |
4 |
|
T192 |
6 |
| auto[1] |
auto[1] |
48 |
1 |
|
|
T50 |
6 |
|
T70 |
5 |
|
T192 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
37 |
1 |
|
|
T50 |
5 |
|
T70 |
4 |
|
T192 |
4 |
| auto[0] |
auto[1] |
51 |
1 |
|
|
T50 |
4 |
|
T70 |
5 |
|
T192 |
7 |
| auto[1] |
auto[0] |
44 |
1 |
|
|
T50 |
4 |
|
T70 |
6 |
|
T192 |
7 |
| auto[1] |
auto[1] |
48 |
1 |
|
|
T50 |
7 |
|
T70 |
5 |
|
T192 |
2 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
86 |
1 |
|
|
T50 |
10 |
|
T70 |
9 |
|
T192 |
12 |
| auto[1] |
auto[1] |
94 |
1 |
|
|
T50 |
10 |
|
T70 |
11 |
|
T192 |
8 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
43 |
1 |
|
|
T50 |
7 |
|
T70 |
1 |
|
T192 |
9 |
| auto[0] |
auto[1] |
48 |
1 |
|
|
T50 |
5 |
|
T70 |
7 |
|
T192 |
6 |
| auto[1] |
auto[0] |
47 |
1 |
|
|
T50 |
5 |
|
T70 |
7 |
|
T192 |
4 |
| auto[1] |
auto[1] |
42 |
1 |
|
|
T50 |
3 |
|
T70 |
5 |
|
T192 |
1 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
92 |
1 |
|
|
T50 |
7 |
|
T70 |
9 |
|
T192 |
13 |
| auto[1] |
auto[1] |
88 |
1 |
|
|
T50 |
13 |
|
T70 |
11 |
|
T192 |
7 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
60 |
1 |
|
|
T50 |
9 |
|
T70 |
12 |
|
T192 |
11 |
| auto[1] |
60 |
1 |
|
|
T50 |
11 |
|
T70 |
8 |
|
T192 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
67 |
1 |
|
|
T50 |
10 |
|
T70 |
11 |
|
T192 |
11 |
| auto[1] |
53 |
1 |
|
|
T50 |
10 |
|
T70 |
9 |
|
T192 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
65 |
1 |
|
|
T50 |
11 |
|
T70 |
14 |
|
T192 |
9 |
| auto[1] |
55 |
1 |
|
|
T50 |
9 |
|
T70 |
6 |
|
T192 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
48 |
1 |
|
|
T50 |
7 |
|
T70 |
8 |
|
T192 |
9 |
| auto[1] |
72 |
1 |
|
|
T50 |
13 |
|
T70 |
12 |
|
T192 |
11 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
52 |
1 |
|
|
T50 |
8 |
|
T70 |
6 |
|
T192 |
8 |
| auto[1] |
68 |
1 |
|
|
T50 |
12 |
|
T70 |
14 |
|
T192 |
12 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
44 |
1 |
|
|
T50 |
11 |
|
T70 |
7 |
|
T192 |
11 |
| auto[1] |
76 |
1 |
|
|
T50 |
9 |
|
T70 |
13 |
|
T192 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
64 |
1 |
|
|
T50 |
9 |
|
T70 |
10 |
|
T192 |
13 |
| auto[1] |
56 |
1 |
|
|
T50 |
11 |
|
T70 |
10 |
|
T192 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
62 |
1 |
|
|
T50 |
10 |
|
T70 |
9 |
|
T192 |
11 |
| auto[1] |
58 |
1 |
|
|
T50 |
10 |
|
T70 |
11 |
|
T192 |
9 |