Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.90 98.90 96.83 100.00 97.44 98.37 99.71 94.03


Total tests in report: 912
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
51.37 51.37 75.84 75.84 62.06 62.06 61.30 61.30 10.90 10.90 76.67 76.67 63.87 63.87 8.95 8.95 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2278102548
68.54 17.17 85.05 9.22 72.22 10.16 63.36 2.05 53.85 42.95 84.58 7.91 80.92 17.05 39.78 30.83 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.727921286
75.59 7.05 89.10 4.05 77.53 5.31 91.10 27.74 57.69 3.85 88.98 4.40 83.43 2.50 41.27 1.49 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.4000121505
80.66 5.08 91.42 2.31 80.66 3.13 91.67 0.57 69.23 11.54 90.98 2.00 88.54 5.11 52.15 10.88 /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.657629124
84.09 3.42 94.79 3.38 87.44 6.77 94.86 3.20 69.23 0.00 94.45 3.48 89.98 1.45 57.85 5.69 /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.2589137875
86.54 2.45 96.64 1.85 89.74 2.30 95.78 0.91 75.00 5.77 96.08 1.63 92.77 2.79 59.78 1.93 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.4014598487
88.66 2.12 97.76 1.12 92.14 2.40 95.78 0.00 83.97 8.97 97.15 1.07 93.93 1.16 59.89 0.11 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2604870032
89.97 1.31 97.84 0.07 93.35 1.21 96.46 0.68 83.97 0.00 97.26 0.11 94.03 0.10 66.85 6.96 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.3153239217
90.99 1.02 97.84 0.00 93.40 0.05 96.46 0.00 84.62 0.64 97.30 0.04 94.03 0.00 73.26 6.41 /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3395452908
91.87 0.88 97.93 0.09 93.55 0.15 96.46 0.00 84.62 0.00 97.30 0.00 95.66 1.64 77.57 4.31 /workspace/coverage/default/48.sysrst_ctrl_combo_detect.245109638
92.47 0.60 98.00 0.07 93.68 0.13 97.72 1.26 84.62 0.00 97.34 0.04 95.66 0.00 80.28 2.71 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3678196757
92.92 0.45 98.08 0.07 93.76 0.08 97.72 0.00 85.90 1.28 97.45 0.11 95.86 0.19 81.66 1.38 /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2322323363
93.27 0.36 98.10 0.02 93.88 0.13 97.72 0.00 85.90 0.00 97.49 0.04 95.86 0.00 83.98 2.32 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.379042098
93.60 0.32 98.17 0.07 93.93 0.05 97.72 0.00 87.18 1.28 97.56 0.07 96.63 0.77 83.98 0.00 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.3527336630
93.91 0.32 98.25 0.07 93.96 0.03 97.72 0.00 89.10 1.92 97.67 0.11 96.72 0.10 83.98 0.00 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3731961903
94.21 0.30 98.30 0.06 93.96 0.00 97.72 0.00 91.03 1.92 97.78 0.11 96.72 0.00 83.98 0.00 /workspace/coverage/default/27.sysrst_ctrl_stress_all.3367583365
94.50 0.29 98.30 0.00 93.98 0.03 99.32 1.60 91.03 0.00 97.78 0.00 96.82 0.10 84.25 0.28 /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3582937702
94.74 0.25 98.38 0.07 94.03 0.05 99.32 0.00 92.31 1.28 97.86 0.07 97.01 0.19 84.31 0.06 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.1120072899
94.99 0.25 98.38 0.00 94.89 0.86 99.32 0.00 92.31 0.00 97.86 0.00 97.21 0.19 84.97 0.66 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2480597313
95.22 0.23 98.38 0.00 95.22 0.33 99.77 0.46 92.31 0.00 97.86 0.00 97.30 0.10 85.69 0.72 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.704278044
95.44 0.22 98.43 0.06 95.25 0.03 99.77 0.00 93.59 1.28 97.93 0.07 97.40 0.10 85.69 0.00 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.4122447768
95.62 0.18 98.51 0.07 95.30 0.05 99.77 0.00 93.59 0.00 97.93 0.00 97.40 0.00 86.85 1.16 /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1243685544
95.80 0.18 98.54 0.04 95.35 0.05 99.77 0.00 94.23 0.64 97.97 0.04 97.59 0.19 87.13 0.28 /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3762566281
95.95 0.15 98.58 0.04 95.40 0.05 99.77 0.00 94.87 0.64 98.00 0.04 97.88 0.29 87.13 0.00 /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.494242866
96.10 0.15 98.58 0.00 95.40 0.00 99.77 0.00 94.87 0.00 98.00 0.00 97.88 0.00 88.18 1.05 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3451133090
96.24 0.14 98.62 0.04 95.48 0.08 99.77 0.00 95.51 0.64 98.04 0.04 98.07 0.19 88.18 0.00 /workspace/coverage/default/3.sysrst_ctrl_edge_detect.391747484
96.37 0.13 98.62 0.00 95.58 0.10 99.77 0.00 95.51 0.00 98.04 0.00 98.55 0.48 88.51 0.33 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.3969520930
96.49 0.12 98.66 0.04 95.60 0.03 99.77 0.00 96.15 0.64 98.08 0.04 98.65 0.10 88.51 0.00 /workspace/coverage/default/17.sysrst_ctrl_edge_detect.2141203661
96.61 0.12 98.69 0.04 95.63 0.03 99.77 0.00 96.79 0.64 98.11 0.04 98.75 0.10 88.51 0.00 /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1618772875
96.72 0.12 98.73 0.04 95.63 0.00 99.77 0.00 97.44 0.64 98.19 0.07 98.75 0.00 88.56 0.06 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.35331095
96.84 0.11 98.73 0.00 95.63 0.00 99.77 0.00 97.44 0.00 98.19 0.00 99.42 0.67 88.67 0.11 /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.2799627286
96.94 0.11 98.75 0.02 95.63 0.00 99.77 0.00 97.44 0.00 98.19 0.00 99.42 0.00 89.39 0.72 /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.4042322639
97.04 0.10 98.79 0.04 95.90 0.28 99.77 0.00 97.44 0.00 98.26 0.07 99.42 0.00 89.67 0.28 /workspace/coverage/default/31.sysrst_ctrl_stress_all.3305057441
97.11 0.07 98.79 0.00 95.90 0.00 99.77 0.00 97.44 0.00 98.26 0.00 99.42 0.00 90.17 0.50 /workspace/coverage/default/0.sysrst_ctrl_combo_detect.3370075159
97.17 0.07 98.82 0.04 96.06 0.15 99.77 0.00 97.44 0.00 98.34 0.07 99.61 0.19 90.17 0.00 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2114227109
97.24 0.06 98.82 0.00 96.06 0.00 99.77 0.00 97.44 0.00 98.34 0.00 99.61 0.00 90.61 0.44 /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2550537144
97.29 0.06 98.84 0.02 96.06 0.00 99.77 0.00 97.44 0.00 98.37 0.04 99.61 0.00 90.94 0.33 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3401541871
97.35 0.06 98.84 0.00 96.06 0.00 99.77 0.00 97.44 0.00 98.37 0.00 99.61 0.00 91.33 0.39 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2563348554
97.40 0.05 98.90 0.06 96.13 0.08 100.00 0.23 97.44 0.00 98.37 0.00 99.61 0.00 91.33 0.00 /workspace/coverage/default/16.sysrst_ctrl_alert_test.3965259297
97.45 0.05 98.90 0.00 96.44 0.30 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 91.38 0.06 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1535798939
97.49 0.04 98.90 0.00 96.44 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 91.66 0.28 /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.3107176558
97.52 0.03 98.90 0.00 96.44 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 91.88 0.22 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.3986644050
97.55 0.03 98.90 0.00 96.44 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 92.10 0.22 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3315519312
97.58 0.03 98.90 0.00 96.61 0.18 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 92.10 0.00 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4144282025
97.60 0.02 98.90 0.00 96.61 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 92.27 0.17 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.3278762873
97.62 0.02 98.90 0.00 96.61 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 92.43 0.17 /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.1771839649
97.64 0.02 98.90 0.00 96.64 0.03 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 92.54 0.11 /workspace/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.2426355284
97.66 0.02 98.90 0.00 96.64 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 92.65 0.11 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.458614429
97.67 0.02 98.90 0.00 96.64 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 92.76 0.11 /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1437852438
97.69 0.02 98.90 0.00 96.64 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 92.87 0.11 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.81385877
97.71 0.02 98.90 0.00 96.64 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 92.98 0.11 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2708190189
97.72 0.02 98.90 0.00 96.64 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 93.09 0.11 /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2859533314
97.74 0.02 98.90 0.00 96.64 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 93.20 0.11 /workspace/coverage/default/39.sysrst_ctrl_stress_all.3943243906
97.75 0.02 98.90 0.00 96.64 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 93.31 0.11 /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3507253582
97.77 0.02 98.90 0.00 96.64 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 93.43 0.11 /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.3180444709
97.78 0.01 98.90 0.00 96.74 0.10 100.00 0.00 97.44 0.00 98.37 0.00 99.61 0.00 93.43 0.00 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.3776904249
97.80 0.01 98.90 0.00 96.74 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.10 93.43 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3335617858
97.81 0.01 98.90 0.00 96.76 0.03 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 93.48 0.06 /workspace/coverage/default/21.sysrst_ctrl_stress_all.284909625
97.82 0.01 98.90 0.00 96.76 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 93.54 0.06 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1554085055
97.82 0.01 98.90 0.00 96.76 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 93.59 0.06 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3863228729
97.83 0.01 98.90 0.00 96.76 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 93.65 0.06 /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1601118635
97.84 0.01 98.90 0.00 96.76 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 93.70 0.06 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1204681996
97.85 0.01 98.90 0.00 96.76 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 93.76 0.06 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.654095162
97.86 0.01 98.90 0.00 96.76 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 93.81 0.06 /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.677595385
97.86 0.01 98.90 0.00 96.76 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 93.87 0.06 /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.297834709
97.87 0.01 98.90 0.00 96.76 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 93.92 0.06 /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.3845593536
97.88 0.01 98.90 0.00 96.76 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 93.98 0.06 /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.2624968597
97.89 0.01 98.90 0.00 96.76 0.00 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 94.03 0.06 /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.894550214
97.89 0.01 98.90 0.00 96.79 0.03 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 94.03 0.00 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.3163003261
97.90 0.01 98.90 0.00 96.81 0.03 100.00 0.00 97.44 0.00 98.37 0.00 99.71 0.00 94.03 0.00 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.968545787

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2154736040
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.2996428081
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2593284986
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.896729434
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.2556593662
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.4244705607
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3921832487
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3004718322
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.1603753081
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3618026781
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2375413244
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.136830084
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2398203698
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.1372723770
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3568414576
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.1633043527
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.2674801141
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.1476243156
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2196429428
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.527476817
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.651293386
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1455037247
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.2745502645
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3696447145
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.395370530
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2959619297
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.988059191
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1640886719
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.132328554
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.3561168539
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.2268984146
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2803540614
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.762349790
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.384640886
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1121399680
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3992746723
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.843200447
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1956290432
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1420305195
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.2806032543
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1826066708
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.3863872698
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.286977766
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.1025202857
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.2012263417
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.4161257097
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1804423491
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3312665654
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.410564400
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.1309671976
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.4043686178
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.1235415018
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.885714914
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3938723156
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.812541714
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3438475987
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2929935072
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.1490779120
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1487145001
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.2985667264
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.3703026736
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.448805523
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2605848571
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.1919701042
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.1911618039
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.748663666
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1017770217
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1643762389
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1364382486
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3732832192
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.2905471270
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.1997689330
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.282294800
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3820747229
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3585985211
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/workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1989663944
/workspace/coverage/default/41.sysrst_ctrl_edge_detect.2488267394
/workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.3624231661
/workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.2017038226
/workspace/coverage/default/41.sysrst_ctrl_pin_access_test.112763687
/workspace/coverage/default/41.sysrst_ctrl_pin_override_test.2700744820
/workspace/coverage/default/41.sysrst_ctrl_smoke.3718650973
/workspace/coverage/default/41.sysrst_ctrl_stress_all.3020727817
/workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2004290989
/workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.2420486671
/workspace/coverage/default/42.sysrst_ctrl_alert_test.3604379076
/workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.3360638565
/workspace/coverage/default/42.sysrst_ctrl_combo_detect.3336833574
/workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.859266730
/workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3474433904
/workspace/coverage/default/42.sysrst_ctrl_edge_detect.2495722181
/workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3034717583
/workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.1718164245
/workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4278992262
/workspace/coverage/default/42.sysrst_ctrl_pin_override_test.251117048
/workspace/coverage/default/42.sysrst_ctrl_smoke.2573375228
/workspace/coverage/default/42.sysrst_ctrl_stress_all.510364506
/workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.2771951288
/workspace/coverage/default/43.sysrst_ctrl_alert_test.972871849
/workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.994791679
/workspace/coverage/default/43.sysrst_ctrl_combo_detect.3693245913
/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.233030835
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3440715785
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.3261157755
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.222717178
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.240097224
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3252247737
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.3728969319
/workspace/coverage/default/43.sysrst_ctrl_smoke.3940053315
/workspace/coverage/default/43.sysrst_ctrl_stress_all.3736168832
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.3554809046
/workspace/coverage/default/44.sysrst_ctrl_alert_test.2737704159
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.463667034
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1977156084
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2006366104
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.337871048
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.2627367774
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.1873818113
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3719190542
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.205034719
/workspace/coverage/default/44.sysrst_ctrl_smoke.3342590090
/workspace/coverage/default/44.sysrst_ctrl_stress_all.4039284604
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.4124419075
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1829904355
/workspace/coverage/default/45.sysrst_ctrl_alert_test.4209246892
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.978731521
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.1303355629
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.1445279430
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.2403858028
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.408331024
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2148964146
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.1341512044
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2050092993
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.2114685085
/workspace/coverage/default/45.sysrst_ctrl_smoke.2808830161
/workspace/coverage/default/45.sysrst_ctrl_stress_all.2546015686
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.763587658
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1602481032
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.697328001
/workspace/coverage/default/46.sysrst_ctrl_combo_detect.3004988615
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.2178306819
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.674651370
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.67391556
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.211178776
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.697039305
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.3418757340
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.1307749951
/workspace/coverage/default/46.sysrst_ctrl_smoke.3639203612
/workspace/coverage/default/46.sysrst_ctrl_stress_all.858702312
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3431583888
/workspace/coverage/default/47.sysrst_ctrl_alert_test.2410266427
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.622604767
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.1146000960
/workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.751851581
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1371845316
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.2886838721
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.742732524
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.2321927706
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.534745134
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.2293825612
/workspace/coverage/default/47.sysrst_ctrl_smoke.2105097331
/workspace/coverage/default/47.sysrst_ctrl_stress_all.719059372
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1746402821
/workspace/coverage/default/48.sysrst_ctrl_alert_test.276478553
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1607421980
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3813731817
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.27814590
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.1561732758
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2110607625
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.927744592
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.1863999854
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.1051021702
/workspace/coverage/default/48.sysrst_ctrl_smoke.3977220263
/workspace/coverage/default/48.sysrst_ctrl_stress_all.1322859418
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1986999817
/workspace/coverage/default/49.sysrst_ctrl_alert_test.4064103400
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.107801053
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.2356747159
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.550232934
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.359413064
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.3804282781
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3067715737
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.3636298063
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1838530345
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.3930280688
/workspace/coverage/default/49.sysrst_ctrl_smoke.4228734566
/workspace/coverage/default/49.sysrst_ctrl_stress_all.1441839692
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.2553628526
/workspace/coverage/default/5.sysrst_ctrl_alert_test.1683243817
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1276505830
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.92976288
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2956662504
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.2657760700
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.1837750065
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.2787769517
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.262907889
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.622953769
/workspace/coverage/default/5.sysrst_ctrl_smoke.3310875025
/workspace/coverage/default/5.sysrst_ctrl_stress_all.3785941213
/workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.430809140
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.382788650
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3580905905
/workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.1189703980
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2163048339
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2864278228
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2694176134
/workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.4028607449
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3619352773
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3922404858
/workspace/coverage/default/6.sysrst_ctrl_alert_test.1872153665
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1140593295
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.2097216270
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.2968155015
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.970712592
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3477238013
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.3269252974
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.3277337418
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.968016934
/workspace/coverage/default/6.sysrst_ctrl_smoke.2607165360
/workspace/coverage/default/6.sysrst_ctrl_stress_all.2114906227
/workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.3268882480
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1761618806
/workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.828354838
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.3677165898
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.2667174121
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.4169329519
/workspace/coverage/default/7.sysrst_ctrl_alert_test.266672855
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.565596116
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.798828173
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.1097614186
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.1415744922
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3789344913
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2233889716
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1453317704
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.3057811716
/workspace/coverage/default/7.sysrst_ctrl_smoke.1981054
/workspace/coverage/default/7.sysrst_ctrl_stress_all.2738997013
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.987940971
/workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2837647530
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2651152881
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2009942583
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2375258363
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.45436963
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1490573320
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.675585032
/workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.1883751418
/workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3404597632
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2133352495
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2802126051
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.1173841443
/workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.3728392298
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.1879830297
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.2118307169
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2407775032
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.3808365507
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.486981675
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.233783092
/workspace/coverage/default/8.sysrst_ctrl_smoke.3998519478
/workspace/coverage/default/8.sysrst_ctrl_stress_all.3550271528
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.4261635352
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.563407221
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.983670479
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3166648390
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1440981554
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3448079192
/workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.34904433
/workspace/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.834749936
/workspace/coverage/default/9.sysrst_ctrl_alert_test.744793979
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.1068299482
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.571013195
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1923229898
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2400809191
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.2212212165
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3510587651
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.3180799044
/workspace/coverage/default/9.sysrst_ctrl_smoke.1203913458
/workspace/coverage/default/9.sysrst_ctrl_stress_all.688498483
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1258516709
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1869504064
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.3366002360
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.2764398659
/workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.1158666460
/workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1523065304
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2343048175
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1490519724
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1814893989



Total test records in report: 912
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T5 /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.2493012944 Jul 15 07:39:40 PM PDT 24 Jul 15 07:39:42 PM PDT 24 2506113611 ps
T6 /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.3278762873 Jul 15 07:38:07 PM PDT 24 Jul 15 07:38:15 PM PDT 24 2511868805 ps
T7 /workspace/coverage/default/12.sysrst_ctrl_alert_test.3273554475 Jul 15 07:38:46 PM PDT 24 Jul 15 07:38:50 PM PDT 24 2021006075 ps
T1 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.460690909 Jul 15 07:38:12 PM PDT 24 Jul 15 07:38:21 PM PDT 24 2547726467 ps
T14 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.4058377062 Jul 15 07:39:01 PM PDT 24 Jul 15 07:39:06 PM PDT 24 4851224244 ps
T15 /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3412068747 Jul 15 07:38:54 PM PDT 24 Jul 15 07:38:58 PM PDT 24 3351016262 ps
T2 /workspace/coverage/default/20.sysrst_ctrl_edge_detect.4000121505 Jul 15 07:39:13 PM PDT 24 Jul 15 07:39:26 PM PDT 24 5565781019 ps
T16 /workspace/coverage/default/48.sysrst_ctrl_alert_test.276478553 Jul 15 07:40:35 PM PDT 24 Jul 15 07:40:43 PM PDT 24 2012535688 ps
T17 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2278102548 Jul 15 07:39:50 PM PDT 24 Jul 15 07:40:39 PM PDT 24 76560740931 ps
T18 /workspace/coverage/default/39.sysrst_ctrl_alert_test.2757930747 Jul 15 07:40:05 PM PDT 24 Jul 15 07:40:10 PM PDT 24 2038025113 ps
T19 /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.491165438 Jul 15 07:38:45 PM PDT 24 Jul 15 07:38:49 PM PDT 24 4085245135 ps
T20 /workspace/coverage/default/25.sysrst_ctrl_smoke.2509408839 Jul 15 07:39:20 PM PDT 24 Jul 15 07:39:28 PM PDT 24 2113050491 ps
T3 /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3678196757 Jul 15 07:39:12 PM PDT 24 Jul 15 07:41:29 PM PDT 24 99035021697 ps
T25 /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.313773815 Jul 15 07:39:01 PM PDT 24 Jul 15 07:39:05 PM PDT 24 2480653230 ps
T4 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.1989169806 Jul 15 07:38:04 PM PDT 24 Jul 15 07:38:09 PM PDT 24 3621737131 ps
T64 /workspace/coverage/default/41.sysrst_ctrl_alert_test.1574689919 Jul 15 07:40:02 PM PDT 24 Jul 15 07:40:04 PM PDT 24 2061908204 ps
T65 /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.1216295736 Jul 15 07:38:54 PM PDT 24 Jul 15 07:39:01 PM PDT 24 2033547147 ps
T27 /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1466667325 Jul 15 07:40:03 PM PDT 24 Jul 15 07:40:12 PM PDT 24 2510537796 ps
T8 /workspace/coverage/default/4.sysrst_ctrl_edge_detect.1044604719 Jul 15 07:38:18 PM PDT 24 Jul 15 07:38:22 PM PDT 24 2585113369 ps
T9 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1535798939 Jul 15 07:38:45 PM PDT 24 Jul 15 07:46:54 PM PDT 24 3554273426530 ps
T30 /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.697328001 Jul 15 07:40:17 PM PDT 24 Jul 15 07:40:26 PM PDT 24 2967249825 ps
T10 /workspace/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2837647530 Jul 15 07:40:35 PM PDT 24 Jul 15 07:44:25 PM PDT 24 86474924133 ps
T59 /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.239353727 Jul 15 07:39:18 PM PDT 24 Jul 15 07:39:27 PM PDT 24 2584898771 ps
T28 /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.3965220021 Jul 15 07:38:47 PM PDT 24 Jul 15 07:38:52 PM PDT 24 2612975776 ps
T11 /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.1761618806 Jul 15 07:38:27 PM PDT 24 Jul 15 07:38:36 PM PDT 24 7269222410 ps
T60 /workspace/coverage/default/18.sysrst_ctrl_smoke.236999532 Jul 15 07:39:02 PM PDT 24 Jul 15 07:39:05 PM PDT 24 2125613715 ps
T61 /workspace/coverage/default/8.sysrst_ctrl_smoke.3998519478 Jul 15 07:38:31 PM PDT 24 Jul 15 07:38:38 PM PDT 24 2113767823 ps
T31 /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1607421980 Jul 15 07:40:34 PM PDT 24 Jul 15 07:44:24 PM PDT 24 191026928555 ps
T12 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3824479286 Jul 15 07:38:22 PM PDT 24 Jul 15 07:38:31 PM PDT 24 2521421831 ps
T51 /workspace/coverage/default/18.sysrst_ctrl_combo_detect.704278044 Jul 15 07:39:06 PM PDT 24 Jul 15 07:42:12 PM PDT 24 134453667602 ps
T128 /workspace/coverage/default/16.sysrst_ctrl_alert_test.3965259297 Jul 15 07:38:58 PM PDT 24 Jul 15 07:39:02 PM PDT 24 2023511445 ps
T26 /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.927744592 Jul 15 07:40:18 PM PDT 24 Jul 15 07:40:27 PM PDT 24 2456103477 ps
T134 /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.811125377 Jul 15 07:39:10 PM PDT 24 Jul 15 07:39:13 PM PDT 24 2238412429 ps
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T13 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2865032949 Jul 15 07:38:14 PM PDT 24 Jul 15 07:38:18 PM PDT 24 2563061739 ps
T76 /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.2589137875 Jul 15 07:39:37 PM PDT 24 Jul 15 07:39:45 PM PDT 24 2509279199 ps
T77 /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.3518475632 Jul 15 07:38:22 PM PDT 24 Jul 15 07:38:30 PM PDT 24 2512856808 ps
T71 /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.573972118 Jul 15 07:39:54 PM PDT 24 Jul 15 07:39:58 PM PDT 24 2513947306 ps
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T52 /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1276505830 Jul 15 07:38:24 PM PDT 24 Jul 15 07:38:35 PM PDT 24 3330249532 ps
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T53 /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3555404403 Jul 15 07:39:18 PM PDT 24 Jul 15 07:39:21 PM PDT 24 3216354578 ps
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T37 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2563348554 Jul 15 07:40:38 PM PDT 24 Jul 15 07:45:36 PM PDT 24 111264245225 ps
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T66 /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1258516709 Jul 15 07:38:34 PM PDT 24 Jul 15 07:38:39 PM PDT 24 9481788620 ps
T73 /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.1402533991 Jul 15 07:39:37 PM PDT 24 Jul 15 07:39:42 PM PDT 24 2489870665 ps
T79 /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.446320073 Jul 15 07:39:27 PM PDT 24 Jul 15 07:39:35 PM PDT 24 2515462542 ps
T39 /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1243685544 Jul 15 07:40:25 PM PDT 24 Jul 15 07:43:24 PM PDT 24 74491981299 ps
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T67 /workspace/coverage/default/4.sysrst_ctrl_ultra_low_pwr.2219108759 Jul 15 07:38:19 PM PDT 24 Jul 15 07:38:23 PM PDT 24 7805479547 ps
T413 /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.894866807 Jul 15 07:38:58 PM PDT 24 Jul 15 07:39:01 PM PDT 24 2134388078 ps
T54 /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3909974867 Jul 15 07:39:14 PM PDT 24 Jul 15 07:39:24 PM PDT 24 3779107619 ps
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T80 /workspace/coverage/default/31.sysrst_ctrl_stress_all.3305057441 Jul 15 07:39:47 PM PDT 24 Jul 15 07:41:50 PM PDT 24 178138669978 ps
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T306 /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.4046351482 Jul 15 07:40:03 PM PDT 24 Jul 15 07:40:18 PM PDT 24 4799079320 ps
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T313 /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.3845229778 Jul 15 07:40:04 PM PDT 24 Jul 15 07:40:15 PM PDT 24 2514314901 ps
T418 /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1238424411 Jul 15 07:39:53 PM PDT 24 Jul 15 07:40:02 PM PDT 24 2612941537 ps
T419 /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.846848827 Jul 15 07:39:26 PM PDT 24 Jul 15 07:39:29 PM PDT 24 2621963989 ps
T420 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3328058426 Jul 15 07:38:13 PM PDT 24 Jul 15 07:38:21 PM PDT 24 2228395361 ps
T421 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3477238013 Jul 15 07:38:27 PM PDT 24 Jul 15 07:38:35 PM PDT 24 2610834084 ps
T422 /workspace/coverage/default/19.sysrst_ctrl_alert_test.1550044116 Jul 15 07:39:08 PM PDT 24 Jul 15 07:39:12 PM PDT 24 2015726397 ps
T275 /workspace/coverage/default/26.sysrst_ctrl_combo_detect.17107220 Jul 15 07:39:26 PM PDT 24 Jul 15 07:40:32 PM PDT 24 92724167707 ps
T423 /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1725382176 Jul 15 07:40:03 PM PDT 24 Jul 15 07:40:11 PM PDT 24 2613438050 ps
T424 /workspace/coverage/default/4.sysrst_ctrl_smoke.299382141 Jul 15 07:38:23 PM PDT 24 Jul 15 07:38:26 PM PDT 24 2127365572 ps
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T425 /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3252247737 Jul 15 07:40:11 PM PDT 24 Jul 15 07:40:15 PM PDT 24 2282444226 ps
T41 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3401541871 Jul 15 07:39:14 PM PDT 24 Jul 15 07:39:55 PM PDT 24 104654965307 ps
T112 /workspace/coverage/default/29.sysrst_ctrl_alert_test.1685816040 Jul 15 07:39:33 PM PDT 24 Jul 15 07:39:36 PM PDT 24 2040165583 ps
T55 /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.4046867007 Jul 15 07:38:38 PM PDT 24 Jul 15 07:43:16 PM PDT 24 115694623956 ps
T113 /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1545151583 Jul 15 07:39:18 PM PDT 24 Jul 15 07:39:22 PM PDT 24 2235101955 ps
T114 /workspace/coverage/default/48.sysrst_ctrl_combo_detect.245109638 Jul 15 07:40:32 PM PDT 24 Jul 15 07:46:01 PM PDT 24 138837321725 ps
T56 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.4014598487 Jul 15 07:40:04 PM PDT 24 Jul 15 07:40:48 PM PDT 24 70996718393 ps
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T116 /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.1815368378 Jul 15 07:39:00 PM PDT 24 Jul 15 07:39:04 PM PDT 24 2105838228 ps
T117 /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.494229734 Jul 15 07:38:13 PM PDT 24 Jul 15 07:38:17 PM PDT 24 2553489426 ps
T118 /workspace/coverage/default/6.sysrst_ctrl_edge_detect.970712592 Jul 15 07:38:29 PM PDT 24 Jul 15 07:38:40 PM PDT 24 3859700195 ps
T57 /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.107801053 Jul 15 07:40:35 PM PDT 24 Jul 15 07:40:46 PM PDT 24 3440289945 ps
T138 /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.770309983 Jul 15 07:38:18 PM PDT 24 Jul 15 07:38:22 PM PDT 24 3368263807 ps
T139 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.4177019398 Jul 15 07:39:33 PM PDT 24 Jul 15 07:39:36 PM PDT 24 2566927600 ps
T140 /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3193999542 Jul 15 07:38:40 PM PDT 24 Jul 15 07:38:48 PM PDT 24 2513521980 ps
T82 /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.3366002360 Jul 15 07:40:37 PM PDT 24 Jul 15 07:44:15 PM PDT 24 84450043065 ps
T58 /workspace/coverage/default/4.sysrst_ctrl_stress_all.2852076161 Jul 15 07:38:19 PM PDT 24 Jul 15 07:38:55 PM PDT 24 12680484014 ps
T267 /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.3315519312 Jul 15 07:40:36 PM PDT 24 Jul 15 07:50:45 PM PDT 24 235681077642 ps
T50 /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.727921286 Jul 15 07:38:34 PM PDT 24 Jul 15 07:40:05 PM PDT 24 902195062303 ps
T97 /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.2452125425 Jul 15 07:39:14 PM PDT 24 Jul 15 07:39:43 PM PDT 24 25842608635 ps
T147 /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.4090867523 Jul 15 07:40:00 PM PDT 24 Jul 15 07:40:02 PM PDT 24 2548740268 ps
T74 /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.4124419075 Jul 15 07:40:11 PM PDT 24 Jul 15 07:40:52 PM PDT 24 31770067330 ps
T148 /workspace/coverage/default/27.sysrst_ctrl_combo_detect.379042098 Jul 15 07:39:29 PM PDT 24 Jul 15 07:46:00 PM PDT 24 146359834747 ps
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T150 /workspace/coverage/default/26.sysrst_ctrl_edge_detect.1516904746 Jul 15 07:39:27 PM PDT 24 Jul 15 07:39:31 PM PDT 24 3660543302 ps
T151 /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1838530345 Jul 15 07:40:32 PM PDT 24 Jul 15 07:40:36 PM PDT 24 2131285681 ps
T152 /workspace/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.1523065304 Jul 15 07:40:36 PM PDT 24 Jul 15 07:41:44 PM PDT 24 105795994433 ps
T153 /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.3097433751 Jul 15 07:39:42 PM PDT 24 Jul 15 07:40:13 PM PDT 24 40423170795 ps
T68 /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1746402821 Jul 15 07:40:16 PM PDT 24 Jul 15 07:40:19 PM PDT 24 4560396909 ps
T155 /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.1763745567 Jul 15 07:40:01 PM PDT 24 Jul 15 07:40:06 PM PDT 24 2953205919 ps
T69 /workspace/coverage/default/24.sysrst_ctrl_stress_all.4115301084 Jul 15 07:39:22 PM PDT 24 Jul 15 07:46:54 PM PDT 24 183012321533 ps
T70 /workspace/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.81385877 Jul 15 07:38:58 PM PDT 24 Jul 15 07:39:48 PM PDT 24 72873231190 ps
T156 /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.2200368078 Jul 15 07:38:45 PM PDT 24 Jul 15 07:38:47 PM PDT 24 2177759324 ps
T157 /workspace/coverage/default/38.sysrst_ctrl_combo_detect.2795972558 Jul 15 07:39:55 PM PDT 24 Jul 15 07:40:52 PM PDT 24 79046051757 ps
T158 /workspace/coverage/default/40.sysrst_ctrl_combo_detect.2781870215 Jul 15 07:40:03 PM PDT 24 Jul 15 07:45:08 PM PDT 24 115248952124 ps
T62 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.2604870032 Jul 15 07:38:10 PM PDT 24 Jul 15 07:38:25 PM PDT 24 37403342041 ps
T159 /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2825218169 Jul 15 07:39:06 PM PDT 24 Jul 15 07:39:21 PM PDT 24 5196517429 ps
T160 /workspace/coverage/default/21.sysrst_ctrl_combo_detect.2418366898 Jul 15 07:39:18 PM PDT 24 Jul 15 07:42:21 PM PDT 24 152688678495 ps
T373 /workspace/coverage/default/14.sysrst_ctrl_combo_detect.4181210031 Jul 15 07:38:55 PM PDT 24 Jul 15 07:40:54 PM PDT 24 124818080760 ps
T426 /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1587478022 Jul 15 07:39:19 PM PDT 24 Jul 15 07:39:31 PM PDT 24 3943200881 ps
T87 /workspace/coverage/default/3.sysrst_ctrl_edge_detect.391747484 Jul 15 07:38:20 PM PDT 24 Jul 15 07:38:31 PM PDT 24 3347258160 ps
T219 /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.382788650 Jul 15 07:38:26 PM PDT 24 Jul 15 07:38:29 PM PDT 24 7877456192 ps
T220 /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3355006939 Jul 15 07:39:20 PM PDT 24 Jul 15 07:39:25 PM PDT 24 2623666581 ps
T221 /workspace/coverage/default/43.sysrst_ctrl_combo_detect.3693245913 Jul 15 07:40:11 PM PDT 24 Jul 15 07:47:04 PM PDT 24 157247978894 ps
T222 /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2859533314 Jul 15 07:39:43 PM PDT 24 Jul 15 07:40:20 PM PDT 24 203518205965 ps
T223 /workspace/coverage/default/42.sysrst_ctrl_stress_all.510364506 Jul 15 07:40:06 PM PDT 24 Jul 15 07:40:35 PM PDT 24 9723677405 ps
T224 /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.438370644 Jul 15 07:39:20 PM PDT 24 Jul 15 07:39:24 PM PDT 24 2640469705 ps
T225 /workspace/coverage/default/15.sysrst_ctrl_smoke.554840173 Jul 15 07:38:53 PM PDT 24 Jul 15 07:38:57 PM PDT 24 2122606838 ps
T226 /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.510283999 Jul 15 07:39:07 PM PDT 24 Jul 15 07:39:15 PM PDT 24 2477192341 ps
T227 /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.894550214 Jul 15 07:40:36 PM PDT 24 Jul 15 07:41:29 PM PDT 24 88378622329 ps
T269 /workspace/coverage/default/12.sysrst_ctrl_combo_detect.676682404 Jul 15 07:38:47 PM PDT 24 Jul 15 07:39:03 PM PDT 24 28103747648 ps
T207 /workspace/coverage/default/33.sysrst_ctrl_edge_detect.1827982840 Jul 15 07:39:46 PM PDT 24 Jul 15 07:39:50 PM PDT 24 3361211271 ps
T427 /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.994791679 Jul 15 07:40:11 PM PDT 24 Jul 15 07:40:15 PM PDT 24 3912710151 ps
T428 /workspace/coverage/default/22.sysrst_ctrl_stress_all.3138249113 Jul 15 07:39:18 PM PDT 24 Jul 15 07:39:50 PM PDT 24 11077641959 ps
T98 /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3166648390 Jul 15 07:40:34 PM PDT 24 Jul 15 07:42:09 PM PDT 24 38098175395 ps
T314 /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.2315639010 Jul 15 07:38:13 PM PDT 24 Jul 15 07:38:22 PM PDT 24 2514288994 ps
T429 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.1371845316 Jul 15 07:40:21 PM PDT 24 Jul 15 07:40:24 PM PDT 24 2917950433 ps
T375 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.3451133090 Jul 15 07:38:28 PM PDT 24 Jul 15 07:39:13 PM PDT 24 96558136941 ps
T374 /workspace/coverage/default/11.sysrst_ctrl_combo_detect.2832132744 Jul 15 07:38:47 PM PDT 24 Jul 15 07:39:59 PM PDT 24 107031505912 ps
T430 /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.3719190542 Jul 15 07:40:12 PM PDT 24 Jul 15 07:40:17 PM PDT 24 2094658911 ps
T299 /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2625834191 Jul 15 07:39:35 PM PDT 24 Jul 15 07:40:22 PM PDT 24 36899208244 ps
T382 /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.3986644050 Jul 15 07:39:14 PM PDT 24 Jul 15 07:42:18 PM PDT 24 145756725256 ps
T431 /workspace/coverage/default/43.sysrst_ctrl_alert_test.972871849 Jul 15 07:40:12 PM PDT 24 Jul 15 07:40:17 PM PDT 24 2018544107 ps
T392 /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3448079192 Jul 15 07:40:33 PM PDT 24 Jul 15 07:41:16 PM PDT 24 62245697231 ps
T177 /workspace/coverage/default/30.sysrst_ctrl_stress_all.2650581674 Jul 15 07:39:41 PM PDT 24 Jul 15 07:41:40 PM PDT 24 356695737261 ps
T432 /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.312804971 Jul 15 07:38:47 PM PDT 24 Jul 15 07:38:54 PM PDT 24 2615305864 ps
T218 /workspace/coverage/default/14.sysrst_ctrl_stress_all.670364350 Jul 15 07:38:52 PM PDT 24 Jul 15 07:39:12 PM PDT 24 14759476513 ps
T433 /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.884843194 Jul 15 07:39:15 PM PDT 24 Jul 15 07:39:23 PM PDT 24 2470677470 ps
T278 /workspace/coverage/default/8.sysrst_ctrl_combo_detect.1173841443 Jul 15 07:38:33 PM PDT 24 Jul 15 07:39:43 PM PDT 24 113204713015 ps
T395 /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3122803916 Jul 15 07:39:31 PM PDT 24 Jul 15 07:45:05 PM PDT 24 125094426210 ps
T178 /workspace/coverage/default/49.sysrst_ctrl_edge_detect.3804282781 Jul 15 07:40:39 PM PDT 24 Jul 15 07:40:43 PM PDT 24 5708459726 ps
T434 /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.172218337 Jul 15 07:39:48 PM PDT 24 Jul 15 07:39:57 PM PDT 24 2451209673 ps
T435 /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2050092993 Jul 15 07:40:11 PM PDT 24 Jul 15 07:40:18 PM PDT 24 2197999335 ps
T436 /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.3713337781 Jul 15 07:40:00 PM PDT 24 Jul 15 07:40:03 PM PDT 24 2479107576 ps
T257 /workspace/coverage/default/8.sysrst_ctrl_edge_detect.2118307169 Jul 15 07:38:32 PM PDT 24 Jul 15 07:38:38 PM PDT 24 3181189287 ps
T437 /workspace/coverage/default/13.sysrst_ctrl_edge_detect.2302859692 Jul 15 07:38:52 PM PDT 24 Jul 15 07:39:01 PM PDT 24 2631455030 ps
T438 /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.1509696662 Jul 15 07:38:13 PM PDT 24 Jul 15 07:38:18 PM PDT 24 2495771453 ps
T288 /workspace/coverage/default/3.sysrst_ctrl_sec_cm.2585489463 Jul 15 07:38:20 PM PDT 24 Jul 15 07:39:21 PM PDT 24 22015115809 ps
T439 /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.3510587651 Jul 15 07:38:34 PM PDT 24 Jul 15 07:38:37 PM PDT 24 2062473711 ps
T277 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3346665116 Jul 15 07:38:46 PM PDT 24 Jul 15 07:39:13 PM PDT 24 82326162870 ps
T440 /workspace/coverage/default/49.sysrst_ctrl_smoke.4228734566 Jul 15 07:40:25 PM PDT 24 Jul 15 07:40:28 PM PDT 24 2124274644 ps
T376 /workspace/coverage/default/29.sysrst_ctrl_combo_detect.1082212583 Jul 15 07:39:33 PM PDT 24 Jul 15 07:44:48 PM PDT 24 136016371976 ps
T380 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.3863228729 Jul 15 07:39:19 PM PDT 24 Jul 15 07:46:56 PM PDT 24 181125011523 ps
T441 /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1869625967 Jul 15 07:38:07 PM PDT 24 Jul 15 07:38:11 PM PDT 24 2119290123 ps
T442 /workspace/coverage/default/33.sysrst_ctrl_alert_test.1279243045 Jul 15 07:39:49 PM PDT 24 Jul 15 07:39:53 PM PDT 24 2036262856 ps
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T443 /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2764132824 Jul 15 07:39:49 PM PDT 24 Jul 15 07:39:53 PM PDT 24 4168436814 ps
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