Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
93.90	93.90	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	93.90	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.90	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	5	57	91.94

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	5	26	83.87	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1972

1

T1

8

T7

45

T45

20

auto[1]

825

1

T7

15

T10

16

T31

5

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2105

1

T1

6

T7

35

T45

12

auto[1]

692

1

T1

2

T7

25

T45

8

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2098

1

T1

6

T7

60

T45

15

auto[1]

699

1

T1

2

T45

5

T10

13

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2037

1

T1

8

T7

47

T45

7

auto[1]

760

1

T7

13

T45

13

T10

6

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2527

1

T1

6

T7

35

T45

7

auto[1]

270

1

T1

2

T7

25

T45

13

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2573

1

T1

8

T7

58

T45

15

auto[1]

224

1

T7

2

T45

5

T35

4

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2540

1

T1

8

T7

35

T45

17

auto[1]

257

1

T7

25

T45

3

T35

4

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2507

1

T1

6

T7

45

T45

20

auto[1]

290

1

T1

2

T7

15

T35

3

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2539

1

T1

8

T7

60

T45

17

auto[1]

258

1

T45

3

T35

1

T33

10

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2122

1

T1

8

T7

47

T45

10

auto[1]

675

1

T7

13

T45

10

T10

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	5	26	83.87	5
Automatically Generated Cross Bins	31	5	26	83.87	5
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	1056	1			T10	16		T31	17		T40	1
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	72	1			T45	5		T92	1		T93	2
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	90	1			T61	1		T357	2		T123	1
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	26	1			T298	2		T283	3		T360	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	114	1			T33	12		T61	1		T62	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	33	1			T1	2		T7	9		T356	14
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	31	1			T372	6		T241	7		T363	5
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	4	1			T356	4		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	74	1			T7	9		T285	2		T356	3
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	31	1			T7	8		T32	6		T305	5
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	15	1			T270	4		T373	2		T374	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	26	1			T45	3		T104	4		T126	1
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	33	1			T310	3		T375	3		T291	5
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	1	1			T284	1		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	55	1			T285	8		T376	9		T377	2
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	23	1			T45	5		T33	7		T361	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	16	1			T33	10		T378	1		T373	5
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	14	1			T362	14		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	17	1			T7	2		T379	2		T352	7
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	2	1			T272	2		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	6	1			T241	6		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	25	1			T285	2		T291	8		T115	9
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	4	1			T380	4		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T35	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	8	1			T35	3		T310	3		T381	1
auto[1]	auto[1]	auto[1]	auto[1]	auto[0]	2	1			T310	2		-	-		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

158

1

T7

2

T35

1

T34

22

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

135

1

T184

26

T354

10

T310

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

72

1

T35

3

T86

3

T294

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

107

1

T57

14

T221

8

T126

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

115

1

T308

6

T97

5

T179

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

71

1

T93

2

T285

2

T382

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

41

1

T7

9

T139

1

T291

8

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

104

1

T33

7

T354

11

T357

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

90

1

T10

7

T47

2

T34

4

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

43

1

T375

4

T379

2

T108

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

34

1

T285

4

T106

3

T376

9

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

90

1

T33

10

T139

4

T285

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

60

1

T10

6

T382

1

T106

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

27

1

T45

5

T31

6

T34

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

9

1

T139

1

T97

2

T359

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

147

1

T7

17

T86

7

T354

11

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

65

1

T31

4

T40

1

T57

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

64

1

T358

5

T298

8

T133

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

55

1

T10

3

T61

1

T62

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

73

1

T45

3

T31

6

T32

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

16

1

T266

1

T383

4

T117

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

19

1

T45

5

T379

3

T384

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

8

1

T304

3

T237

2

T385

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

81

1

T1

2

T33

12

T97

6

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T86

2

T353

3

T292

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

11

1

T184

1

T386

2

T116

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

1

1

T255

1

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

22

1

T387

1

T388

3

T272

3

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T61

1

T357

2

T379

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

30

1

T92

1

T266

1

T376

10

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T31

1

T268

1

T389

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded