Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1122

1

T3

18

T11

23

T40

21

auto[1]

1133

1

T3

22

T11

17

T40

19

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

541

1

T3

10

T11

11

T40

10

from_0to1

540

1

T3

10

T11

10

T40

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1105

1

T3

16

T11

17

T40

20

auto[1]

1150

1

T3

24

T11

23

T40

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088

1

T3

19

T11

22

T40

22

auto[1]

1167

1

T3

21

T11

18

T40

18

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T3

1

T11

2

T40

2

auto[0]

from_1to0

auto[0]

auto[1]

82

1

T3

2

T40

2

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T11

4

T47

1

T220

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T3

1

T11

2

T40

1

auto[0]

from_0to1

auto[0]

auto[0]

73

1

T3

2

T40

3

T47

1

auto[0]

from_0to1

auto[0]

auto[1]

77

1

T11

3

T40

1

T47

1

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T40

2

T400

1

T401

2

auto[0]

from_0to1

auto[1]

auto[1]

55

1

T3

2

T11

1

T40

1

auto[1]

from_1to0

auto[0]

auto[0]

72

1

T3

2

T11

1

T40

2

auto[1]

from_1to0

auto[0]

auto[1]

53

1

T40

2

T48

1

T400

2

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T3

1

T11

1

T40

1

auto[1]

from_1to0

auto[1]

auto[1]

75

1

T3

3

T11

1

T48

1

auto[1]

from_0to1

auto[0]

auto[0]

54

1

T11

1

T40

1

T49

2

auto[1]

from_0to1

auto[0]

auto[1]

74

1

T3

1

T11

3

T40

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T3

2

T11

1

T40

2

auto[1]

from_0to1

auto[1]

auto[1]

84

1

T3

3

T11

1

T47

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1089

1

T3

17

T11

20

T40

23

auto[1]

1166

1

T3

23

T11

20

T40

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

555

1

T3

11

T11

12

T40

11

from_0to1

556

1

T3

11

T11

11

T40

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1129

1

T3

22

T11

19

T40

16

auto[1]

1126

1

T3

18

T11

21

T40

24

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1115

1

T3

17

T11

20

T40

20

auto[1]

1140

1

T3

23

T11

20

T40

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

71

1

T11

3

T40

3

T220

1

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T3

3

T11

2

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T11

3

T40

1

T60

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T3

3

T40

1

T47

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T3

1

T11

1

T40

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T11

1

T40

1

T47

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T11

1

T40

3

T49

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T3

1

T11

3

T40

1

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T3

2

T40

1

T49

2

auto[1]

from_1to0

auto[0]

auto[1]

73

1

T3

2

T40

2

T47

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T3

1

T11

1

T40

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T11

3

T40

2

T47

1

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T3

2

T11

1

T47

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T3

2

T11

2

T40

1

auto[1]

from_0to1

auto[1]

auto[0]

92

1

T3

2

T11

1

T40

2

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T3

3

T11

1

T40

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T3

24

T11

21

T40

23

auto[1]

1102

1

T3

16

T11

19

T40

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

546

1

T3

11

T11

12

T40

8

from_0to1

542

1

T3

11

T11

11

T40

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1096

1

T3

15

T11

16

T40

19

auto[1]

1159

1

T3

25

T11

24

T40

21

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1124

1

T3

22

T11

21

T40

24

auto[1]

1131

1

T3

18

T11

19

T40

16

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

60

1

T3

2

T11

1

T40

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T3

2

T11

1

T40

3

auto[0]

from_1to0

auto[1]

auto[0]

58

1

T3

4

T11

3

T40

1

auto[0]

from_1to0

auto[1]

auto[1]

81

1

T3

1

T40

1

T47

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T3

1

T11

2

T47

1

auto[0]

from_0to1

auto[0]

auto[1]

69

1

T3

1

T11

3

T47

1

auto[0]

from_0to1

auto[1]

auto[0]

72

1

T3

2

T11

1

T40

1

auto[0]

from_0to1

auto[1]

auto[1]

72

1

T3

2

T11

2

T47

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T11

1

T48

1

T220

1

auto[1]

from_1to0

auto[0]

auto[1]

69

1

T3

1

T11

2

T47

1

auto[1]

from_1to0

auto[1]

auto[0]

80

1

T11

2

T40

2

T47

2

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T3

1

T11

2

T60

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T3

2

T11

1

T40

3

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T3

1

T11

1

T60

2

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T40

3

T48

2

T400

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T3

2

T11

1

T40

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1169

1

T3

18

T11

19

T40

23

auto[1]

1086

1

T3

22

T11

21

T40

17

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

552

1

T3

14

T11

11

T40

11

from_0to1

552

1

T3

13

T11

12

T40

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T3

18

T11

18

T40

14

auto[1]

1116

1

T3

22

T11

22

T40

26

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T3

23

T11

23

T40

15

auto[1]

1124

1

T3

17

T11

17

T40

25

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

73

1

T3

1

T11

1

T47

1

auto[0]

from_1to0

auto[0]

auto[1]

81

1

T3

1

T11

2

T47

2

auto[0]

from_1to0

auto[1]

auto[0]

53

1

T3

1

T11

2

T40

3

auto[0]

from_1to0

auto[1]

auto[1]

75

1

T3

2

T11

1

T40

5

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T11

1

T40

1

T60

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T3

1

T11

1

T40

5

auto[0]

from_0to1

auto[1]

auto[0]

79

1

T3

2

T11

3

T47

2

auto[0]

from_0to1

auto[1]

auto[1]

70

1

T3

3

T11

1

T40

2

auto[1]

from_1to0

auto[0]

auto[0]

73

1

T3

4

T11

2

T60

1

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T3

1

T40

2

T47

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T3

4

T11

3

T220

3

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T40

1

T47

1

T48

1

auto[1]

from_0to1

auto[0]

auto[0]

67

1

T3

3

T11

1

T40

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T11

2

T47

1

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T3

1

T11

3

T40

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T3

3

T48

1

T400

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1127

1

T3

21

T11

20

T40

24

auto[1]

1128

1

T3

19

T11

20

T40

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

524

1

T3

10

T11

9

T40

10

from_0to1

527

1

T3

9

T11

9

T40

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1105

1

T3

26

T11

17

T40

24

auto[1]

1150

1

T3

14

T11

23

T40

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1084

1

T3

21

T11

17

T40

18

auto[1]

1171

1

T3

19

T11

23

T40

22

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

77

1

T3

4

T11

2

T40

1

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T3

2

T11

1

T40

2

auto[0]

from_1to0

auto[1]

auto[0]

56

1

T3

1

T40

2

T48

1

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T11

2

T60

1

T48

1

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T3

2

T11

1

T40

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T3

1

T11

1

T40

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T47

1

T60

1

T48

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T40

3

T60

1

T49

1

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T3

2

T11

1

T40

2

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T40

2

T47

1

T60

2

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T3

1

T11

2

T40

1

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T11

1

T47

1

T60

3

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T3

2

T11

2

T40

2

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T3

1

T11

1

T40

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T11

3

T40

1

T47

1

auto[1]

from_0to1

auto[1]

auto[1]

63

1

T3

3

T11

1

T40

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1095

1

T3

19

T11

25

T40

20

auto[1]

1160

1

T3

21

T11

15

T40

20

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

518

1

T3

7

T11

8

T40

10

from_0to1

531

1

T3

7

T11

8

T40

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1110

1

T3

18

T11

20

T40

25

auto[1]

1145

1

T3

22

T11

20

T40

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T3

20

T11

26

T40

21

auto[1]

1100

1

T3

20

T11

14

T40

19

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

63

1

T11

1

T40

2

T48

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T3

1

T11

1

T40

3

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T3

1

T11

1

T49

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T3

2

T11

1

T40

2

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T3

1

T11

3

T40

1

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T3

1

T11

2

T60

1

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T3

2

T11

1

T40

2

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T11

1

T48

2

T220

1

auto[1]

from_1to0

auto[0]

auto[0]

83

1

T11

2

T47

1

T220

2

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T3

1

T40

2

T60

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T3

2

T11

1

T60

2

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T11

1

T40

1

T47

1

auto[1]

from_0to1

auto[0]

auto[0]

63

1

T40

3

T47

2

T400

1

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T3

1

T40

2

T60

1

auto[1]

from_0to1

auto[1]

auto[0]

74

1

T3

1

T11

1

T40

1

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T3

1

T40

1

T60

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1178

1

T3

18

T11

19

T40

17

auto[1]

1077

1

T3

22

T11

21

T40

23

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

540

1

T3

9

T11

12

T40

10

from_0to1

544

1

T3

8

T11

13

T40

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1124

1

T3

23

T11

28

T40

20

auto[1]

1131

1

T3

17

T11

12

T40

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1131

1

T3

22

T11

24

T40

15

auto[1]

1124

1

T3

18

T11

16

T40

25

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T3

3

T11

2

T40

1

auto[0]

from_1to0

auto[0]

auto[1]

70

1

T3

1

T40

2

T60

1

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T3

2

T60

1

T48

1

auto[0]

from_1to0

auto[1]

auto[1]

71

1

T11

1

T40

2

T47

3

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T3

1

T11

2

T220

1

auto[0]

from_0to1

auto[0]

auto[1]

82

1

T3

1

T11

3

T40

2

auto[0]

from_0to1

auto[1]

auto[0]

59

1

T11

2

T47

1

T49

1

auto[0]

from_0to1

auto[1]

auto[1]

77

1

T3

2

T40

2

T47

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T3

2

T11

5

T47

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T11

3

T48

2

T220

2

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T40

2

T49

2

T400

2

auto[1]

from_1to0

auto[1]

auto[1]

77

1

T3

1

T11

1

T40

3

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T3

1

T11

3

T40

2

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T3

2

T11

1

T40

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T3

1

T11

2

T40

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T40

1

T47

1

T49

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1156

1

T3

20

T11

28

T40

24

auto[1]

1099

1

T3

20

T11

12

T40

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

545

1

T3

9

T11

9

T40

10

from_0to1

538

1

T3

10

T11

9

T40

11

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1146

1

T3

22

T11

17

T40

14

auto[1]

1109

1

T3

18

T11

23

T40

26

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1135

1

T3

23

T11

24

T40

15

auto[1]

1120

1

T3

17

T11

16

T40

25

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T3

1

T60

2

T49

1

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T3

3

T40

2

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

77

1

T3

2

T11

5

T40

1

auto[0]

from_1to0

auto[1]

auto[1]

72

1

T11

3

T40

5

T47

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T3

1

T11

4

T60

2

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T3

1

T40

2

T47

2

auto[0]

from_0to1

auto[1]

auto[0]

79

1

T3

2

T11

2

T40

3

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T3

1

T40

2

T47

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T3

1

T48

1

T49

2

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T11

1

T47

1

T49

3

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T3

1

T40

1

T47

1

auto[1]

from_1to0

auto[1]

auto[1]

64

1

T3

1

T40

1

T47

1

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T3

1

T47

1

T49

1

auto[1]

from_0to1

auto[0]

auto[1]

86

1

T3

1

T11

1

T40

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T3

1

T11

1

T40

3

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T3

2

T11

1

T60

1