Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151405	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117250

1

T1

242

T4

18

T5

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	137597	1			T1	245		T4	2		T5	2
values[0x0]	65283	1			T1	250		T4	30		T5	5
values[0x1]	65775	1			T1	251		T4	30		T5	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	123362	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145293

1

T1

303

T4

25

T5

4

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	786	1			T1	6		T3	2		T27	1
valid_sources[0x01]	762	1			T1	2		T3	2		T21	2
valid_sources[0x02]	786	1			T1	4		T2	2		T3	2
valid_sources[0x03]	692	1			T3	1		T22	1		T11	2
valid_sources[0x04]	817	1			T3	2		T27	1		T24	2
valid_sources[0x05]	1374	1			T3	2		T27	1		T24	2
valid_sources[0x06]	710	1			T1	8		T4	1		T3	3
valid_sources[0x07]	1001	1			T1	3		T3	2		T27	1
valid_sources[0x08]	810	1			T1	12		T27	1		T10	4
valid_sources[0x09]	987	1			T3	2		T27	6		T22	1
valid_sources[0x0a]	920	1			T4	2		T2	1		T3	3
valid_sources[0x0b]	1054	1			T1	7		T3	2		T10	8
valid_sources[0x0c]	855	1			T3	1		T27	2		T11	2
valid_sources[0x0d]	849	1			T3	1		T27	4		T23	1
valid_sources[0x0e]	895	1			T4	1		T3	3		T27	1
valid_sources[0x0f]	894	1			T27	1		T22	1		T10	1
valid_sources[0x10]	769	1			T1	9		T5	1		T3	1
valid_sources[0x11]	1234	1			T1	3		T3	3		T10	2
valid_sources[0x12]	875	1			T3	1		T27	5		T8	1
valid_sources[0x13]	940	1			T1	4		T3	6		T27	1
valid_sources[0x14]	1571	1			T1	4		T3	2		T27	1
valid_sources[0x15]	733	1			T3	2		T27	3		T10	3
valid_sources[0x16]	940	1			T15	6		T27	2		T23	1
valid_sources[0x17]	896	1			T27	1		T11	7		T40	1
valid_sources[0x18]	791	1			T15	1		T27	1		T24	1
valid_sources[0x19]	1006	1			T27	10		T23	1		T10	4
valid_sources[0x1a]	862	1			T1	18		T3	4		T23	1
valid_sources[0x1b]	1333	1			T3	3		T27	1		T11	1
valid_sources[0x1c]	1704	1			T1	12		T15	3		T23	1
valid_sources[0x1d]	890	1			T3	2		T27	1		T10	3
valid_sources[0x1e]	824	1			T4	1		T3	8		T27	6
valid_sources[0x1f]	776	1			T1	6		T27	3		T11	3
valid_sources[0x20]	928	1			T3	1		T11	1		T35	5
valid_sources[0x21]	1810	1			T3	2		T27	1		T11	1
valid_sources[0x22]	805	1			T1	5		T3	5		T27	1
valid_sources[0x23]	1415	1			T1	1		T3	1		T27	2
valid_sources[0x24]	998	1			T5	1		T3	3		T27	5
valid_sources[0x25]	899	1			T5	1		T3	3		T8	1
valid_sources[0x26]	875	1			T3	2		T23	1		T11	10
valid_sources[0x27]	936	1			T5	1		T3	4		T27	2
valid_sources[0x28]	988	1			T1	19		T3	1		T27	4
valid_sources[0x29]	837	1			T3	3		T27	2		T24	1
valid_sources[0x2a]	814	1			T1	11		T3	1		T27	3
valid_sources[0x2b]	827	1			T27	1		T10	3		T32	4
valid_sources[0x2c]	1510	1			T4	2		T27	1		T10	2
valid_sources[0x2d]	939	1			T3	1		T27	4		T11	4
valid_sources[0x2e]	859	1			T3	2		T27	1		T24	1
valid_sources[0x2f]	832	1			T1	19		T4	1		T3	1
valid_sources[0x30]	798	1			T3	3		T27	2		T24	2
valid_sources[0x31]	910	1			T3	1		T27	5		T22	1
valid_sources[0x32]	952	1			T3	4		T27	1		T24	1
valid_sources[0x33]	735	1			T27	2		T11	17		T35	6
valid_sources[0x34]	961	1			T1	2		T3	1		T27	8
valid_sources[0x35]	851	1			T1	4		T15	1		T27	4
valid_sources[0x36]	1124	1			T3	3		T27	1		T10	7
valid_sources[0x37]	849	1			T27	2		T11	3		T35	4
valid_sources[0x38]	1630	1			T3	3		T10	3		T11	2
valid_sources[0x39]	1559	1			T1	1		T3	2		T27	2
valid_sources[0x3a]	1796	1			T1	4		T4	1		T3	3
valid_sources[0x3b]	1780	1			T1	5		T3	4		T27	1
valid_sources[0x3c]	872	1			T3	3		T27	1		T23	1
valid_sources[0x3d]	951	1			T3	2		T27	4		T23	1
valid_sources[0x3e]	756	1			T3	3		T27	2		T10	1
valid_sources[0x3f]	1195	1			T3	3		T27	1		T24	1
valid_sources[0x40]	1554	1			T3	1		T11	2		T35	9
valid_sources[0x41]	801	1			T1	18		T3	2		T27	5
valid_sources[0x42]	1568	1			T15	3		T27	2		T10	4
valid_sources[0x43]	1050	1			T1	2		T3	1		T23	1
valid_sources[0x44]	1180	1			T1	2		T3	5		T27	2
valid_sources[0x45]	807	1			T3	4		T27	1		T11	8
valid_sources[0x46]	932	1			T1	9		T3	2		T10	5
valid_sources[0x47]	732	1			T3	2		T11	11		T35	2
valid_sources[0x48]	1059	1			T1	15		T4	1		T3	2
valid_sources[0x49]	1104	1			T3	5		T8	1		T11	6
valid_sources[0x4a]	1191	1			T1	16		T2	1		T3	2
valid_sources[0x4b]	1113	1			T1	8		T3	1		T24	1
valid_sources[0x4c]	810	1			T1	11		T3	5		T11	5
valid_sources[0x4d]	1379	1			T5	1		T3	1		T27	1
valid_sources[0x4e]	762	1			T1	1		T27	2		T23	1
valid_sources[0x4f]	1357	1			T1	1		T3	2		T22	1
valid_sources[0x50]	961	1			T13	10		T2	1		T3	2
valid_sources[0x51]	1214	1			T1	12		T27	2		T10	1
valid_sources[0x52]	883	1			T3	2		T27	2		T10	4
valid_sources[0x53]	974	1			T4	2		T3	2		T27	1
valid_sources[0x54]	720	1			T1	3		T3	1		T27	1
valid_sources[0x55]	673	1			T1	1		T3	1		T27	2
valid_sources[0x56]	915	1			T1	5		T4	2		T3	5
valid_sources[0x57]	793	1			T1	2		T4	3		T3	2
valid_sources[0x58]	866	1			T1	4		T10	1		T11	4
valid_sources[0x59]	1000	1			T1	9		T15	7		T3	3
valid_sources[0x5a]	900	1			T4	1		T3	3		T27	3
valid_sources[0x5b]	945	1			T3	3		T27	1		T10	1
valid_sources[0x5c]	1185	1			T27	3		T23	1		T11	4
valid_sources[0x5d]	1309	1			T1	18		T3	2		T27	1
valid_sources[0x5e]	1057	1			T1	2		T3	2		T27	2
valid_sources[0x5f]	1124	1			T1	2		T3	4		T27	5
valid_sources[0x60]	841	1			T1	2		T3	3		T27	1
valid_sources[0x61]	941	1			T3	3		T10	2		T11	5
valid_sources[0x62]	1566	1			T3	2		T27	7		T23	1
valid_sources[0x63]	766	1			T3	3		T24	3		T11	4
valid_sources[0x64]	1385	1			T1	4		T15	2		T27	1
valid_sources[0x65]	830	1			T15	6		T3	2		T27	4
valid_sources[0x66]	802	1			T1	14		T15	10		T3	3
valid_sources[0x67]	700	1			T1	3		T3	3		T27	2
valid_sources[0x68]	1018	1			T1	3		T3	5		T21	15
valid_sources[0x69]	730	1			T3	2		T27	4		T11	5
valid_sources[0x6a]	819	1			T3	1		T27	2		T11	7
valid_sources[0x6b]	933	1			T1	1		T3	5		T27	4
valid_sources[0x6c]	844	1			T4	1		T3	4		T24	1
valid_sources[0x6d]	961	1			T1	4		T3	2		T27	4
valid_sources[0x6e]	1144	1			T4	1		T3	3		T10	12
valid_sources[0x6f]	882	1			T3	4		T27	2		T10	1
valid_sources[0x70]	756	1			T3	5		T27	1		T10	1
valid_sources[0x71]	720	1			T3	5		T27	1		T35	1
valid_sources[0x72]	1017	1			T6	19		T24	2		T11	2
valid_sources[0x73]	1692	1			T1	17		T4	3		T24	1
valid_sources[0x74]	938	1			T4	2		T3	5		T11	1
valid_sources[0x75]	818	1			T16	6		T3	4		T27	5
valid_sources[0x76]	839	1			T3	1		T27	3		T11	3
valid_sources[0x77]	1779	1			T1	5		T3	1		T27	2
valid_sources[0x78]	1179	1			T1	4		T5	1		T3	6
valid_sources[0x79]	941	1			T3	1		T27	2		T11	7
valid_sources[0x7a]	1051	1			T1	4		T3	2		T27	2
valid_sources[0x7b]	1725	1			T3	1		T27	3		T23	1
valid_sources[0x7c]	870	1			T4	4		T10	3		T11	4
valid_sources[0x7d]	916	1			T24	2		T23	1		T9	1
valid_sources[0x7e]	1694	1			T3	2		T27	3		T10	2
valid_sources[0x7f]	815	1			T22	1		T11	4		T31	11
valid_sources[0x80]	962	1			T3	2		T27	1		T23	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63109

1

T1

117

T5

1

T13

1

values[0x0]

all_enables

biggest_size

31770

1

T1

80

T4

13

T5

2

values[0x1]

all_enables

biggest_size

22371

1

T1

45

T4

5

T5

1