Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T14
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T14
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T25,T26,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T25,T26,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T26,T11,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T11
1	0	Covered	T1,T4,T14
1	1	Covered	T25,T26,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T26,T11,T47
0	1	Covered	T110
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T11,T47
0	1	Covered	T26,T11,T47
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T26,T11,T47
1	-	Covered	T26,T11,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T26,T11
DetectSt	168	Covered	T26,T11,T47
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T26,T11,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T26,T11,T47
DebounceSt->IdleSt	163	Covered	T25,T11,T40
DetectSt->IdleSt	186	Covered	T110
DetectSt->StableSt	191	Covered	T26,T11,T47
IdleSt->DebounceSt	148	Covered	T25,T26,T11
StableSt->IdleSt	206	Covered	T26,T11,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T26,T11
0	1	Covered	T25,T26,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T26,T11,T47
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T26,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T26,T11,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T25,T11,T142
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T26,T11
DetectSt	-	-	-	-	1	-	-	Covered	T110
DetectSt	-	-	-	-	0	1	-	Covered	T26,T11,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T26,T11,T47
StableSt	-	-	-	-	-	-	0	Covered	T26,T11,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	264	0	0
CntIncr_A	9566120	144938	0	0
CntNoWrap_A	9566120	8934544	0	0
DetectStDropOut_A	9566120	1	0	0
DetectedOut_A	9566120	795	0	0
DetectedPulseOut_A	9566120	118	0	0
DisabledIdleSt_A	9566120	8783611	0	0
DisabledNoDetection_A	9566120	8785922	0	0
EnterDebounceSt_A	9566120	147	0	0
EnterDetectSt_A	9566120	119	0	0
EnterStableSt_A	9566120	118	0	0
PulseIsPulse_A	9566120	118	0	0
StayInStableSt	9566120	677	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9566120	6747	0	0
gen_low_level_sva.LowLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	118	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	264	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T11	0	7	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T25	41158	1	0	0
T26	0	2	0	0
T34	0	2	0	0
T45	12753	0	0	0
T47	0	2	0	0
T48	0	4	0	0
T49	0	2	0	0
T101	0	4	0	0
T102	0	4	0	0
T103	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	144938	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T11	0	259	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T25	41158	14	0	0
T26	0	42	0	0
T34	0	23	0	0
T40	0	70	0	0
T45	12753	0	0	0
T47	0	73	0	0
T48	0	88	0	0
T49	0	12	0	0
T101	0	126	0	0
T102	0	130	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934544	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1	0	0
T110	701	1	0	0
T111	4869	0	0	0
T112	6961	0	0	0
T129	436	0	0	0
T130	404	0	0	0
T131	423	0	0	0
T132	672	0	0	0
T133	9297	0	0	0
T134	1905	0	0	0
T135	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	795	0	0
T11	14742	34	0	0
T12	591	0	0	0
T26	764	11	0	0
T31	31828	0	0	0
T34	0	10	0	0
T35	15717	0	0	0
T40	16284	0	0	0
T46	640	0	0	0
T47	0	10	0	0
T48	0	17	0	0
T49	0	11	0	0
T55	494	0	0	0
T79	402	0	0	0
T101	0	16	0	0
T102	0	11	0	0
T103	0	13	0	0
T137	0	11	0	0
T138	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	118	0	0
T11	14742	3	0	0
T12	591	0	0	0
T26	764	1	0	0
T31	31828	0	0	0
T34	0	1	0	0
T35	15717	0	0	0
T40	16284	0	0	0
T46	640	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T55	494	0	0	0
T79	402	0	0	0
T101	0	2	0	0
T102	0	2	0	0
T103	0	1	0	0
T137	0	1	0	0
T138	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8783611	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8785922	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	147	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T11	0	4	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T25	41158	1	0	0
T26	0	1	0	0
T34	0	1	0	0
T40	0	1	0	0
T45	12753	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T101	0	2	0	0
T102	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	119	0	0
T11	14742	3	0	0
T12	591	0	0	0
T26	764	1	0	0
T31	31828	0	0	0
T34	0	1	0	0
T35	15717	0	0	0
T40	16284	0	0	0
T46	640	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T55	494	0	0	0
T79	402	0	0	0
T101	0	2	0	0
T102	0	2	0	0
T103	0	1	0	0
T137	0	1	0	0
T138	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	118	0	0
T11	14742	3	0	0
T12	591	0	0	0
T26	764	1	0	0
T31	31828	0	0	0
T34	0	1	0	0
T35	15717	0	0	0
T40	16284	0	0	0
T46	640	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T55	494	0	0	0
T79	402	0	0	0
T101	0	2	0	0
T102	0	2	0	0
T103	0	1	0	0
T137	0	1	0	0
T138	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	118	0	0
T11	14742	3	0	0
T12	591	0	0	0
T26	764	1	0	0
T31	31828	0	0	0
T34	0	1	0	0
T35	15717	0	0	0
T40	16284	0	0	0
T46	640	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T55	494	0	0	0
T79	402	0	0	0
T101	0	2	0	0
T102	0	2	0	0
T103	0	1	0	0
T137	0	1	0	0
T138	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	677	0	0
T11	14742	31	0	0
T12	591	0	0	0
T26	764	10	0	0
T31	31828	0	0	0
T34	0	9	0	0
T35	15717	0	0	0
T40	16284	0	0	0
T46	640	0	0	0
T47	0	9	0	0
T48	0	15	0	0
T49	0	10	0	0
T55	494	0	0	0
T79	402	0	0	0
T101	0	14	0	0
T102	0	9	0	0
T103	0	12	0	0
T137	0	10	0	0
T138	402	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6747	0	0
T1	7156	25	0	0
T2	853	4	0	0
T3	5844	20	0	0
T4	522	6	0	0
T5	402	0	0	0
T6	1136	4	0	0
T13	403	0	0	0
T14	4724	21	0	0
T15	2261	1	0	0
T16	1065	0	0	0
T24	0	6	0	0
T25	0	3	0	0
T27	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	118	0	0
T11	14742	3	0	0
T12	591	0	0	0
T26	764	1	0	0
T31	31828	0	0	0
T34	0	1	0	0
T35	15717	0	0	0
T40	16284	0	0	0
T46	640	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T55	494	0	0	0
T79	402	0	0	0
T101	0	2	0	0
T102	0	2	0	0
T103	0	1	0	0
T137	0	1	0	0
T138	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T14
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T14
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T6,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T11
1	0	Covered	T1,T4,T14
1	1	Covered	T2,T6,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T11
0	1	Covered	T12,T98,T99
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T11
0	1	Unreachable
1	0	Covered	T2,T6,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T11
DetectSt	168	Covered	T2,T6,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T6,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T11
DebounceSt->IdleSt	163	Covered	T11,T53,T140
DetectSt->IdleSt	186	Covered	T12,T98,T99
DetectSt->StableSt	191	Covered	T2,T6,T11
IdleSt->DebounceSt	148	Covered	T2,T6,T11
StableSt->IdleSt	206	Covered	T2,T6,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T11
0	1	Covered	T2,T6,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T53,T140
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T11
DetectSt	-	-	-	-	1	-	-	Covered	T12,T98,T99
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	172	0	0
CntIncr_A	9566120	56516	0	0
CntNoWrap_A	9566120	8934636	0	0
DetectStDropOut_A	9566120	15	0	0
DetectedOut_A	9566120	342555	0	0
DetectedPulseOut_A	9566120	46	0	0
DisabledIdleSt_A	9566120	6654595	0	0
DisabledNoDetection_A	9566120	6656952	0	0
EnterDebounceSt_A	9566120	113	0	0
EnterDetectSt_A	9566120	61	0	0
EnterStableSt_A	9566120	46	0	0
PulseIsPulse_A	9566120	46	0	0
StayInStableSt	9566120	342509	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9566120	6747	0	0
gen_low_level_sva.LowLevelEvent_A	9566120	8937170	0	0
gen_sticky_sva.StableStDropOut_A	9566120	869679	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	172	0	0
T2	853	2	0	0
T3	5844	0	0	0
T6	1136	2	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	5	0	0
T12	0	4	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	2	0	0
T49	0	2	0	0
T51	0	4	0	0
T53	0	12	0	0
T63	0	2	0	0
T64	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	56516	0	0
T2	853	58	0	0
T3	5844	0	0	0
T6	1136	86	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	146	0	0
T12	0	26	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	24	0	0
T49	0	29	0	0
T51	0	20	0	0
T53	0	756	0	0
T63	0	85	0	0
T64	0	165	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934636	0	0
T1	7156	6755	0	0
T2	853	450	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	733	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	15	0	0
T12	591	1	0	0
T31	31828	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T40	16284	0	0	0
T46	640	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T98	0	3	0	0
T99	0	1	0	0
T138	402	0	0	0
T143	0	1	0	0
T144	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0
T147	0	2	0	0
T148	0	3	0	0
T149	0	1	0	0
T150	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	342555	0	0
T2	853	193	0	0
T3	5844	0	0	0
T6	1136	526	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	362	0	0
T12	0	1	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	70	0	0
T49	0	33	0	0
T51	0	95	0	0
T63	0	65	0	0
T64	0	558	0	0
T97	0	196	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	46	0	0
T2	853	1	0	0
T3	5844	0	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T63	0	1	0	0
T64	0	3	0	0
T97	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6654595	0	0
T1	7156	6755	0	0
T2	853	25	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	27	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6656952	0	0
T1	7156	6756	0	0
T2	853	26	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	28	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	113	0	0
T2	853	1	0	0
T3	5844	0	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	3	0	0
T12	0	2	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T53	0	12	0	0
T63	0	1	0	0
T64	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	61	0	0
T2	853	1	0	0
T3	5844	0	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T63	0	1	0	0
T64	0	3	0	0
T97	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	46	0	0
T2	853	1	0	0
T3	5844	0	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T63	0	1	0	0
T64	0	3	0	0
T97	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	46	0	0
T2	853	1	0	0
T3	5844	0	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T63	0	1	0	0
T64	0	3	0	0
T97	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	342509	0	0
T2	853	192	0	0
T3	5844	0	0	0
T6	1136	525	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	360	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	69	0	0
T49	0	32	0	0
T51	0	93	0	0
T63	0	64	0	0
T64	0	555	0	0
T97	0	195	0	0
T140	0	311	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6747	0	0
T1	7156	25	0	0
T2	853	4	0	0
T3	5844	20	0	0
T4	522	6	0	0
T5	402	0	0	0
T6	1136	4	0	0
T13	403	0	0	0
T14	4724	21	0	0
T15	2261	1	0	0
T16	1065	0	0	0
T24	0	6	0	0
T25	0	3	0	0
T27	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	869679	0	0
T2	853	161	0	0
T3	5844	0	0	0
T6	1136	70	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	233	0	0
T12	0	62	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	139	0	0
T49	0	123	0	0
T51	0	549	0	0
T63	0	101135	0	0
T64	0	1047	0	0
T97	0	139	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T15,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T15,T2
1	1	Covered	T4,T15,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T6,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T51,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T11
1	0	Covered	T4,T15,T3
1	1	Covered	T2,T6,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T51,T47
0	1	Covered	T51,T53,T97
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T51,T47
0	1	Unreachable
1	0	Covered	T6,T51,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T11
DetectSt	168	Covered	T6,T51,T47
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T51,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T51,T47
DebounceSt->IdleSt	163	Covered	T2,T11,T12
DetectSt->IdleSt	186	Covered	T51,T53,T97
DetectSt->StableSt	191	Covered	T6,T51,T47
IdleSt->DebounceSt	148	Covered	T2,T6,T11
StableSt->IdleSt	206	Covered	T6,T51,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T11
0	1	Covered	T2,T6,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T6,T51,T47
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T15,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T51,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T11,T12
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T11
DetectSt	-	-	-	-	1	-	-	Covered	T51,T53,T97
DetectSt	-	-	-	-	0	1	-	Covered	T6,T51,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T51,T47
StableSt	-	-	-	-	-	-	0	Covered	T6,T51,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	180	0	0
CntIncr_A	9566120	516895	0	0
CntNoWrap_A	9566120	8934628	0	0
DetectStDropOut_A	9566120	12	0	0
DetectedOut_A	9566120	1176814	0	0
DetectedPulseOut_A	9566120	38	0	0
DisabledIdleSt_A	9566120	6654595	0	0
DisabledNoDetection_A	9566120	6656952	0	0
EnterDebounceSt_A	9566120	132	0	0
EnterDetectSt_A	9566120	50	0	0
EnterStableSt_A	9566120	38	0	0
PulseIsPulse_A	9566120	38	0	0
StayInStableSt	9566120	1176776	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_sticky_sva.StableStDropOut_A	9566120	193823	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	180	0	0
T2	853	4	0	0
T3	5844	0	0	0
T6	1136	2	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	7	0	0
T12	0	2	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	2	0	0
T49	0	2	0	0
T51	0	6	0	0
T53	0	10	0	0
T63	0	2	0	0
T64	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	516895	0	0
T2	853	92	0	0
T3	5844	0	0	0
T6	1136	47	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	602	0	0
T12	0	100	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	55	0	0
T49	0	42	0	0
T51	0	273	0	0
T53	0	170	0	0
T63	0	61622	0	0
T64	0	282	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934628	0	0
T1	7156	6755	0	0
T2	853	448	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	733	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	12	0	0
T39	928	0	0	0
T47	13428	0	0	0
T51	1139	1	0	0
T53	0	2	0	0
T61	9906	0	0	0
T62	10355	0	0	0
T97	0	1	0	0
T136	510	0	0	0
T151	0	3	0	0
T152	0	1	0	0
T153	0	4	0	0
T154	451	0	0	0
T155	840	0	0	0
T156	404	0	0	0
T157	445	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1176814	0	0
T6	1136	189	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T45	12753	0	0	0
T47	0	123	0	0
T49	0	95	0	0
T51	0	280	0	0
T53	0	247	0	0
T63	0	39636	0	0
T64	0	1271	0	0
T97	0	45	0	0
T140	0	173	0	0
T141	0	673203	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	38	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T45	12753	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T53	0	3	0	0
T63	0	1	0	0
T64	0	3	0	0
T97	0	1	0	0
T140	0	2	0	0
T141	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6654595	0	0
T1	7156	6755	0	0
T2	853	25	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	27	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6656952	0	0
T1	7156	6756	0	0
T2	853	26	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	28	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	132	0	0
T2	853	4	0	0
T3	5844	0	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	7	0	0
T12	0	2	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	3	0	0
T53	0	5	0	0
T63	0	1	0	0
T64	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	50	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T45	12753	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	3	0	0
T53	0	5	0	0
T63	0	1	0	0
T64	0	3	0	0
T97	0	2	0	0
T140	0	2	0	0
T141	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	38	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T45	12753	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T53	0	3	0	0
T63	0	1	0	0
T64	0	3	0	0
T97	0	1	0	0
T140	0	2	0	0
T141	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	38	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T45	12753	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T53	0	3	0	0
T63	0	1	0	0
T64	0	3	0	0
T97	0	1	0	0
T140	0	2	0	0
T141	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1176776	0	0
T6	1136	188	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T45	12753	0	0	0
T47	0	122	0	0
T49	0	94	0	0
T51	0	278	0	0
T53	0	244	0	0
T63	0	39635	0	0
T64	0	1268	0	0
T97	0	44	0	0
T140	0	171	0	0
T141	0	673200	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	193823	0	0
T6	1136	457	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T45	12753	0	0	0
T47	0	60	0	0
T49	0	51	0	0
T51	0	93	0	0
T53	0	517	0	0
T63	0	26	0	0
T64	0	215	0	0
T97	0	222	0	0
T140	0	462	0	0
T141	0	467	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T2,T6,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T6,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T6,T11
1	0	Covered	T1,T4,T14
1	1	Covered	T2,T6,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T11
0	1	Covered	T2,T11,T49
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T6,T11
0	1	Unreachable
1	0	Covered	T2,T6,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T6,T11
DetectSt	168	Covered	T2,T6,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T6,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T6,T11
DebounceSt->IdleSt	163	Covered	T49,T64,T98
DetectSt->IdleSt	186	Covered	T2,T11,T49
DetectSt->StableSt	191	Covered	T2,T6,T11
IdleSt->DebounceSt	148	Covered	T2,T6,T11
StableSt->IdleSt	206	Covered	T2,T6,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T6,T11
0	1	Covered	T2,T6,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T6,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T6,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T6,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T49,T64,T98
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T6,T11
DetectSt	-	-	-	-	1	-	-	Covered	T2,T11,T49
DetectSt	-	-	-	-	0	1	-	Covered	T2,T6,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T6,T11
StableSt	-	-	-	-	-	-	0	Covered	T2,T6,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	167	0	0
CntIncr_A	9566120	210613	0	0
CntNoWrap_A	9566120	8934641	0	0
DetectStDropOut_A	9566120	16	0	0
DetectedOut_A	9566120	11533	0	0
DetectedPulseOut_A	9566120	45	0	0
DisabledIdleSt_A	9566120	6654595	0	0
DisabledNoDetection_A	9566120	6656952	0	0
EnterDebounceSt_A	9566120	108	0	0
EnterDetectSt_A	9566120	61	0	0
EnterStableSt_A	9566120	45	0	0
PulseIsPulse_A	9566120	45	0	0
StayInStableSt	9566120	11488	0	0
gen_high_event_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_sticky_sva.StableStDropOut_A	9566120	1487235	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	167	0	0
T2	853	4	0	0
T3	5844	0	0	0
T6	1136	2	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	6	0	0
T12	0	2	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	2	0	0
T49	0	3	0	0
T51	0	4	0	0
T53	0	6	0	0
T63	0	2	0	0
T64	0	11	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	210613	0	0
T2	853	160	0	0
T3	5844	0	0	0
T6	1136	58	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	118	0	0
T12	0	11	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	42	0	0
T49	0	40	0	0
T51	0	70	0	0
T53	0	63	0	0
T63	0	16298	0	0
T64	0	413	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934641	0	0
T1	7156	6755	0	0
T2	853	448	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	733	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	16	0	0
T2	853	1	0	0
T3	5844	0	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	1	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T49	0	1	0	0
T64	0	3	0	0
T140	0	2	0	0
T149	0	3	0	0
T158	0	1	0	0
T159	0	3	0	0
T160	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	11533	0	0
T2	853	164	0	0
T3	5844	0	0	0
T6	1136	389	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	348	0	0
T12	0	15	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	133	0	0
T51	0	175	0	0
T53	0	372	0	0
T63	0	3876	0	0
T64	0	181	0	0
T97	0	299	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	45	0	0
T2	853	1	0	0
T3	5844	0	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	1	0	0
T51	0	2	0	0
T53	0	3	0	0
T63	0	1	0	0
T64	0	1	0	0
T97	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6654595	0	0
T1	7156	6755	0	0
T2	853	25	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	27	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6656952	0	0
T1	7156	6756	0	0
T2	853	26	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	28	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	108	0	0
T2	853	2	0	0
T3	5844	0	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	3	0	0
T12	0	1	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	1	0	0
T49	0	2	0	0
T51	0	2	0	0
T53	0	3	0	0
T63	0	1	0	0
T64	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	61	0	0
T2	853	2	0	0
T3	5844	0	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	3	0	0
T12	0	1	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	0	2	0	0
T53	0	3	0	0
T63	0	1	0	0
T64	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	45	0	0
T2	853	1	0	0
T3	5844	0	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	1	0	0
T51	0	2	0	0
T53	0	3	0	0
T63	0	1	0	0
T64	0	1	0	0
T97	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	45	0	0
T2	853	1	0	0
T3	5844	0	0	0
T6	1136	1	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	1	0	0
T51	0	2	0	0
T53	0	3	0	0
T63	0	1	0	0
T64	0	1	0	0
T97	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	11488	0	0
T2	853	163	0	0
T3	5844	0	0	0
T6	1136	388	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	346	0	0
T12	0	14	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	132	0	0
T51	0	173	0	0
T53	0	369	0	0
T63	0	3875	0	0
T64	0	180	0	0
T97	0	298	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1487235	0	0
T2	853	80	0	0
T3	5844	0	0	0
T6	1136	255	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	281	0	0
T12	0	125	0	0
T16	1065	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T47	0	75	0	0
T51	0	430	0	0
T53	0	620	0	0
T63	0	81128	0	0
T64	0	485	0	0
T97	0	50	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T36,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T36,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T36,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T40
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T36,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T36,T44
0	1	Covered	T161
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T36,T44
0	1	Covered	T3,T36,T44
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T36,T44
1	-	Covered	T3,T36,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T36,T41
DetectSt	168	Covered	T3,T36,T44
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T36,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T36,T44
DebounceSt->IdleSt	163	Covered	T41,T87,T162
DetectSt->IdleSt	186	Covered	T161
DetectSt->StableSt	191	Covered	T3,T36,T44
IdleSt->DebounceSt	148	Covered	T3,T36,T41
StableSt->IdleSt	206	Covered	T3,T36,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T36,T41
0	1	Covered	T3,T36,T41
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T36,T44
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T36,T41
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T36,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T41,T162
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T36,T41
DetectSt	-	-	-	-	1	-	-	Covered	T161
DetectSt	-	-	-	-	0	1	-	Covered	T3,T36,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T36,T44
StableSt	-	-	-	-	-	-	0	Covered	T3,T36,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	63	0	0
CntIncr_A	9566120	1662	0	0
CntNoWrap_A	9566120	8934745	0	0
DetectStDropOut_A	9566120	1	0	0
DetectedOut_A	9566120	2235	0	0
DetectedPulseOut_A	9566120	29	0	0
DisabledIdleSt_A	9566120	8916395	0	0
DisabledNoDetection_A	9566120	8918708	0	0
EnterDebounceSt_A	9566120	33	0	0
EnterDetectSt_A	9566120	30	0	0
EnterStableSt_A	9566120	29	0	0
PulseIsPulse_A	9566120	29	0	0
StayInStableSt	9566120	2190	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	63	0	0
T3	5844	2	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	4	0	0
T41	0	1	0	0
T42	0	2	0	0
T44	0	4	0	0
T109	0	2	0	0
T163	0	2	0	0
T164	0	2	0	0
T165	0	2	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1662	0	0
T3	5844	100	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	116	0	0
T41	0	43	0	0
T42	0	73	0	0
T44	0	78	0	0
T109	0	39	0	0
T163	0	34	0	0
T164	0	32	0	0
T165	0	24	0	0
T166	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934745	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1158	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1	0	0
T161	957	1	0	0
T167	55202	0	0	0
T168	415	0	0	0
T169	413	0	0	0
T170	6004	0	0	0
T171	721	0	0	0
T172	495	0	0	0
T173	873	0	0	0
T174	505	0	0	0
T175	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	2235	0	0
T3	5844	141	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	79	0	0
T42	0	140	0	0
T44	0	166	0	0
T96	0	141	0	0
T109	0	45	0	0
T163	0	53	0	0
T164	0	40	0	0
T165	0	58	0	0
T166	0	267	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	29	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T96	0	1	0	0
T109	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8916395	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	746	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8918708	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	758	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	33	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T44	0	2	0	0
T109	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	30	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T96	0	1	0	0
T109	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	29	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T96	0	1	0	0
T109	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	29	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T42	0	1	0	0
T44	0	2	0	0
T96	0	1	0	0
T109	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T166	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	2190	0	0
T3	5844	140	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	76	0	0
T42	0	138	0	0
T44	0	163	0	0
T96	0	140	0	0
T109	0	43	0	0
T163	0	51	0	0
T164	0	39	0	0
T165	0	57	0	0
T166	0	265	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	12	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	1	0	0
T44	0	1	0	0
T96	0	1	0	0
T162	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0
T178	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T9,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T9,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T11
1	0	Covered	T4,T15,T3
1	1	Covered	T3,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T9,T11
0	1	Covered	T39,T37,T38
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T9,T11
1	-	Covered	T39,T37,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T11
DetectSt	168	Covered	T3,T9,T11
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T9,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T9,T11
DebounceSt->IdleSt	163	Covered	T3,T87
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T9,T11
IdleSt->DebounceSt	148	Covered	T3,T9,T11
StableSt->IdleSt	206	Covered	T3,T11,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T11
0	1	Covered	T3,T9,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T9,T11
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T9,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T3
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T37,T38
StableSt	-	-	-	-	-	-	0	Covered	T3,T9,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	92	0	0
CntIncr_A	9566120	62718	0	0
CntNoWrap_A	9566120	8934716	0	0
DetectStDropOut_A	9566120	0	0	0
DetectedOut_A	9566120	62992	0	0
DetectedPulseOut_A	9566120	45	0	0
DisabledIdleSt_A	9566120	8797560	0	0
DisabledNoDetection_A	9566120	8799882	0	0
EnterDebounceSt_A	9566120	47	0	0
EnterDetectSt_A	9566120	45	0	0
EnterStableSt_A	9566120	45	0	0
PulseIsPulse_A	9566120	45	0	0
StayInStableSt	9566120	62924	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9566120	2538	0	0
gen_low_level_sva.LowLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	92	0	0
T3	5844	3	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	0	2	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	4	0	0
T38	0	4	0	0
T39	0	4	0	0
T40	0	2	0	0
T163	0	2	0	0
T179	0	2	0	0
T180	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	62718	0	0
T3	5844	200	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	0	27	0	0
T11	0	100	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	96	0	0
T38	0	38	0	0
T39	0	132	0	0
T40	0	60	0	0
T163	0	34	0	0
T179	0	60440	0	0
T180	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934716	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1157	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	62992	0	0
T3	5844	38	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	0	87	0	0
T11	0	226	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	46	0	0
T38	0	83	0	0
T39	0	258	0	0
T40	0	43	0	0
T163	0	97	0	0
T179	0	60480	0	0
T180	0	137	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	45	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T163	0	1	0	0
T179	0	1	0	0
T180	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8797560	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	746	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8799882	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	758	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	47	0	0
T3	5844	2	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T163	0	1	0	0
T179	0	1	0	0
T180	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	45	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T163	0	1	0	0
T179	0	1	0	0
T180	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	45	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T163	0	1	0	0
T179	0	1	0	0
T180	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	45	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T163	0	1	0	0
T179	0	1	0	0
T180	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	62924	0	0
T3	5844	36	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	0	85	0	0
T11	0	224	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	43	0	0
T38	0	80	0	0
T39	0	255	0	0
T40	0	41	0	0
T163	0	96	0	0
T179	0	60478	0	0
T180	0	134	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	2538	0	0
T2	853	0	0	0
T3	5844	21	0	0
T4	522	6	0	0
T5	402	0	0	0
T6	1136	0	0	0
T8	0	1	0	0
T9	0	1	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	1	0	0
T16	1065	0	0	0
T20	0	2	0	0
T21	0	6	0	0
T22	0	3	0	0
T23	0	5	0	0
T24	0	3	0	0
T27	5021	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	21	0	0
T34	50331	0	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	928	1	0	0
T60	506	0	0	0
T86	28043	0	0	0
T91	0	1	0	0
T109	0	1	0	0
T136	510	0	0	0
T139	25984	0	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T180	0	1	0	0
T181	0	1	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0