Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T13
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T39,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T40,T39,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T39,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T40
1	0	Covered	T1,T4,T5
1	1	Covered	T40,T39,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T39,T43
0	1	Covered	T162
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T39,T43
0	1	Covered	T39,T163,T186
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T39,T43
1	-	Covered	T39,T163,T186

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T39,T43
DetectSt	168	Covered	T40,T39,T43
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T40,T39,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T39,T43
DebounceSt->IdleSt	163	Covered	T163,T87
DetectSt->IdleSt	186	Covered	T162
DetectSt->StableSt	191	Covered	T40,T39,T43
IdleSt->DebounceSt	148	Covered	T40,T39,T43
StableSt->IdleSt	206	Covered	T40,T39,T163

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T39,T43
0	1	Covered	T40,T39,T43
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T39,T43
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T39,T43
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T39,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T163
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T39,T43
DetectSt	-	-	-	-	1	-	-	Covered	T162
DetectSt	-	-	-	-	0	1	-	Covered	T40,T39,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T163,T186
StableSt	-	-	-	-	-	-	0	Covered	T40,T39,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	78	0	0
CntIncr_A	9566120	63583	0	0
CntNoWrap_A	9566120	8934730	0	0
DetectStDropOut_A	9566120	1	0	0
DetectedOut_A	9566120	64203	0	0
DetectedPulseOut_A	9566120	37	0	0
DisabledIdleSt_A	9566120	8540514	0	0
DisabledNoDetection_A	9566120	8542826	0	0
EnterDebounceSt_A	9566120	40	0	0
EnterDetectSt_A	9566120	38	0	0
EnterStableSt_A	9566120	37	0	0
PulseIsPulse_A	9566120	37	0	0
StayInStableSt	9566120	64142	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	78	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	16284	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	2	0	0
T138	402	0	0	0
T150	422	0	0	0
T163	0	3	0	0
T180	0	2	0	0
T187	0	2	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	63583	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T38	0	19	0	0
T39	0	66	0	0
T40	16284	33	0	0
T42	0	73	0	0
T43	0	61712	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	95	0	0
T138	402	0	0	0
T150	422	0	0	0
T163	0	68	0	0
T180	0	40	0	0
T187	0	88	0	0
T188	0	11	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934730	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1	0	0
T50	7400	0	0	0
T162	25172	1	0	0
T189	6835	0	0	0
T190	5472	0	0	0
T191	4325	0	0	0
T192	1857	0	0	0
T193	521	0	0	0
T194	22562	0	0	0
T195	498	0	0	0
T196	422	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	64203	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T38	0	40	0	0
T39	0	40	0	0
T40	16284	97	0	0
T42	0	257	0	0
T43	0	61756	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	40	0	0
T138	402	0	0	0
T150	422	0	0	0
T163	0	39	0	0
T180	0	70	0	0
T187	0	43	0	0
T188	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	37	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	16284	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	1	0	0
T138	402	0	0	0
T150	422	0	0	0
T163	0	1	0	0
T180	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8540514	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	746	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8542826	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	758	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	40	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	16284	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	1	0	0
T138	402	0	0	0
T150	422	0	0	0
T163	0	2	0	0
T180	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	38	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	16284	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	1	0	0
T138	402	0	0	0
T150	422	0	0	0
T163	0	1	0	0
T180	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	37	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	16284	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	1	0	0
T138	402	0	0	0
T150	422	0	0	0
T163	0	1	0	0
T180	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	37	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	16284	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	1	0	0
T138	402	0	0	0
T150	422	0	0	0
T163	0	1	0	0
T180	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	64142	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T38	0	38	0	0
T39	0	39	0	0
T40	16284	95	0	0
T42	0	255	0	0
T43	0	61754	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	38	0	0
T138	402	0	0	0
T150	422	0	0	0
T163	0	38	0	0
T180	0	68	0	0
T187	0	41	0	0
T188	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	12	0	0
T34	50331	0	0	0
T39	928	1	0	0
T60	506	0	0	0
T73	0	1	0	0
T86	28043	0	0	0
T117	0	1	0	0
T136	510	0	0	0
T139	25984	0	0	0
T162	0	2	0	0
T163	0	1	0	0
T165	0	1	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0
T186	0	2	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T13
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T34,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T40,T34,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T40,T43,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T40,T34
1	0	Covered	T4,T15,T16
1	1	Covered	T40,T34,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T40,T43,T36
0	1	Covered	T90,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T40,T43,T36
0	1	Covered	T40,T43,T36
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T40,T43,T36
1	-	Covered	T40,T43,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T40,T34,T43
DetectSt	168	Covered	T40,T43,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T40,T43,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T40,T43,T36
DebounceSt->IdleSt	163	Covered	T34,T165,T198
DetectSt->IdleSt	186	Covered	T90,T91
DetectSt->StableSt	191	Covered	T40,T43,T36
IdleSt->DebounceSt	148	Covered	T40,T34,T43
StableSt->IdleSt	206	Covered	T40,T43,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T40,T34,T43
0	1	Covered	T40,T34,T43
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T40,T43,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T40,T34,T43
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T40,T43,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T165,T198
DebounceSt	-	0	0	-	-	-	-	Covered	T40,T34,T43
DetectSt	-	-	-	-	1	-	-	Covered	T90,T91
DetectSt	-	-	-	-	0	1	-	Covered	T40,T43,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T40,T43,T36
StableSt	-	-	-	-	-	-	0	Covered	T40,T43,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	95	0	0
CntIncr_A	9566120	64241	0	0
CntNoWrap_A	9566120	8934713	0	0
DetectStDropOut_A	9566120	2	0	0
DetectedOut_A	9566120	66800	0	0
DetectedPulseOut_A	9566120	43	0	0
DisabledIdleSt_A	9566120	8667716	0	0
DisabledNoDetection_A	9566120	8670031	0	0
EnterDebounceSt_A	9566120	50	0	0
EnterDetectSt_A	9566120	45	0	0
EnterStableSt_A	9566120	43	0	0
PulseIsPulse_A	9566120	43	0	0
StayInStableSt	9566120	66738	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9566120	2925	0	0
gen_low_level_sva.LowLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	95	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T34	0	1	0	0
T35	15717	0	0	0
T36	0	6	0	0
T40	16284	2	0	0
T42	0	4	0	0
T43	0	2	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	2	0	0
T138	402	0	0	0
T150	422	0	0	0
T180	0	2	0	0
T188	0	2	0	0
T200	0	2	0	0
T201	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	64241	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T34	0	45	0	0
T35	15717	0	0	0
T36	0	174	0	0
T40	16284	33	0	0
T42	0	89	0	0
T43	0	61712	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	95	0	0
T138	402	0	0	0
T150	422	0	0	0
T180	0	40	0	0
T188	0	11	0	0
T200	0	66	0	0
T201	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934713	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	2	0	0
T42	7599	0	0	0
T90	641	1	0	0
T91	0	1	0	0
T187	629	0	0	0
T202	7392	0	0	0
T203	405	0	0	0
T204	502	0	0	0
T205	524	0	0	0
T206	429	0	0	0
T207	501	0	0	0
T208	638	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	66800	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T36	0	107	0	0
T40	16284	40	0	0
T42	0	64	0	0
T43	0	63189	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T138	402	0	0	0
T150	422	0	0	0
T164	0	46	0	0
T180	0	102	0	0
T188	0	65	0	0
T200	0	113	0	0
T201	0	60	0	0
T209	0	118	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	43	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T36	0	3	0	0
T40	16284	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T138	402	0	0	0
T150	422	0	0	0
T164	0	1	0	0
T180	0	1	0	0
T188	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8667716	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8670031	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	50	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T34	0	1	0	0
T35	15717	0	0	0
T36	0	3	0	0
T40	16284	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	1	0	0
T138	402	0	0	0
T150	422	0	0	0
T180	0	1	0	0
T188	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	45	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T36	0	3	0	0
T40	16284	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T90	0	1	0	0
T138	402	0	0	0
T150	422	0	0	0
T164	0	1	0	0
T180	0	1	0	0
T188	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	43	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T36	0	3	0	0
T40	16284	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T138	402	0	0	0
T150	422	0	0	0
T164	0	1	0	0
T180	0	1	0	0
T188	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	43	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T36	0	3	0	0
T40	16284	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T138	402	0	0	0
T150	422	0	0	0
T164	0	1	0	0
T180	0	1	0	0
T188	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	66738	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T36	0	103	0	0
T40	16284	39	0	0
T42	0	61	0	0
T43	0	63188	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T138	402	0	0	0
T150	422	0	0	0
T164	0	44	0	0
T180	0	101	0	0
T188	0	64	0	0
T200	0	111	0	0
T201	0	59	0	0
T209	0	117	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	2925	0	0
T2	853	0	0	0
T3	5844	13	0	0
T4	522	5	0	0
T5	402	0	0	0
T6	1136	0	0	0
T11	0	38	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	4	0	0
T16	1065	5	0	0
T20	0	6	0	0
T21	0	4	0	0
T22	0	6	0	0
T23	0	5	0	0
T24	0	5	0	0
T27	5021	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	23	0	0
T32	20322	0	0	0
T33	43477	0	0	0
T35	15717	0	0	0
T36	0	2	0	0
T40	16284	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	640	0	0	0
T51	1139	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T95	0	1	0	0
T138	402	0	0	0
T150	422	0	0	0
T165	0	2	0	0
T180	0	1	0	0
T188	0	1	0	0
T201	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T14
1	1	Covered	T1,T4,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T9,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T9,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T40,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T11
1	0	Covered	T1,T4,T14
1	1	Covered	T3,T9,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T40,T39
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T40,T39
0	1	Covered	T39,T43,T36
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T40,T39
1	-	Covered	T39,T43,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T9,T11
DetectSt	168	Covered	T9,T40,T39
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T40,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T40,T39
DebounceSt->IdleSt	163	Covered	T3,T11,T42
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T40,T39
IdleSt->DebounceSt	148	Covered	T3,T9,T11
StableSt->IdleSt	206	Covered	T40,T39,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T9,T40
0	1	Covered	T3,T9,T11
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T40,T39
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T9,T11
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T40,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T42,T187
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T9,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T40,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T43,T36
StableSt	-	-	-	-	-	-	0	Covered	T9,T40,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	95	0	0
CntIncr_A	9566120	125807	0	0
CntNoWrap_A	9566120	8934713	0	0
DetectStDropOut_A	9566120	0	0	0
DetectedOut_A	9566120	67248	0	0
DetectedPulseOut_A	9566120	44	0	0
DisabledIdleSt_A	9566120	8673528	0	0
DisabledNoDetection_A	9566120	8675845	0	0
EnterDebounceSt_A	9566120	52	0	0
EnterDetectSt_A	9566120	44	0	0
EnterStableSt_A	9566120	44	0	0
PulseIsPulse_A	9566120	44	0	0
StayInStableSt	9566120	67187	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	95	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	7	0	0
T43	0	4	0	0
T44	0	2	0	0
T187	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	125807	0	0
T3	5844	100	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	0	27	0	0
T11	0	55	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	58	0	0
T38	0	19	0	0
T39	0	66	0	0
T40	0	33	0	0
T42	0	178	0	0
T43	0	123424	0	0
T44	0	39	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934713	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1159	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	67248	0	0
T9	524	88	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T35	15717	0	0	0
T36	0	270	0	0
T38	0	56	0	0
T39	0	61	0	0
T40	16284	205	0	0
T42	0	219	0	0
T43	0	63232	0	0
T44	0	337	0	0
T46	640	0	0	0
T79	402	0	0	0
T164	0	60	0	0
T188	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	44	0	0
T9	524	1	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T35	15717	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	16284	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	640	0	0	0
T79	402	0	0	0
T164	0	2	0	0
T188	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8673528	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	746	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8675845	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	758	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	52	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T9	0	1	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	4	0	0
T43	0	2	0	0
T44	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	44	0	0
T9	524	1	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T35	15717	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	16284	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	640	0	0	0
T79	402	0	0	0
T164	0	2	0	0
T188	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	44	0	0
T9	524	1	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T35	15717	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	16284	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	640	0	0	0
T79	402	0	0	0
T164	0	2	0	0
T188	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	44	0	0
T9	524	1	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T35	15717	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	16284	1	0	0
T42	0	3	0	0
T43	0	2	0	0
T44	0	1	0	0
T46	640	0	0	0
T79	402	0	0	0
T164	0	2	0	0
T188	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	67187	0	0
T9	524	86	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T35	15717	0	0	0
T36	0	269	0	0
T38	0	54	0	0
T39	0	60	0	0
T40	16284	203	0	0
T42	0	214	0	0
T43	0	63229	0	0
T44	0	335	0	0
T46	640	0	0	0
T79	402	0	0	0
T164	0	58	0	0
T188	0	43	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	26	0	0
T34	50331	0	0	0
T36	0	1	0	0
T39	928	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T60	506	0	0	0
T86	28043	0	0	0
T109	0	1	0	0
T136	510	0	0	0
T139	25984	0	0	0
T164	0	2	0	0
T181	0	1	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0
T188	0	1	0	0
T210	0	1	0	0
T211	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T14
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T14
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T39,T41,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T39,T41,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T39,T41,T42

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T40,T39
1	0	Covered	T1,T4,T14
1	1	Covered	T39,T41,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T39,T41,T42
0	1	Not Covered
1	0	Covered	T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T39,T41,T42
0	1	Covered	T41,T42,T164
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T39,T41,T42
1	-	Covered	T41,T42,T164

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T39,T41,T42
DetectSt	168	Covered	T39,T41,T42
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T39,T41,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T39,T41,T42
DebounceSt->IdleSt	163	Covered	T87,T212
DetectSt->IdleSt	186	Covered	T50
DetectSt->StableSt	191	Covered	T39,T41,T42
IdleSt->DebounceSt	148	Covered	T39,T41,T42
StableSt->IdleSt	206	Covered	T41,T42,T164

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T39,T41,T42
0	1	Covered	T39,T41,T42
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T39,T41,T42
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T39,T41,T42
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T39,T41,T42
DebounceSt	-	0	1	0	-	-	-	Covered	T212
DebounceSt	-	0	0	-	-	-	-	Covered	T39,T41,T42
DetectSt	-	-	-	-	1	-	-	Covered	T50
DetectSt	-	-	-	-	0	1	-	Covered	T39,T41,T42
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T42,T164
StableSt	-	-	-	-	-	-	0	Covered	T39,T41,T42
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	50	0	0
CntIncr_A	9566120	1154	0	0
CntNoWrap_A	9566120	8934758	0	0
DetectStDropOut_A	9566120	0	0	0
DetectedOut_A	9566120	1480	0	0
DetectedPulseOut_A	9566120	23	0	0
DisabledIdleSt_A	9566120	8796205	0	0
DisabledNoDetection_A	9566120	8798524	0	0
EnterDebounceSt_A	9566120	26	0	0
EnterDetectSt_A	9566120	24	0	0
EnterStableSt_A	9566120	23	0	0
PulseIsPulse_A	9566120	23	0	0
StayInStableSt	9566120	1441	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9566120	6337	0	0
gen_low_level_sva.LowLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	7	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	50	0	0
T34	50331	0	0	0
T39	928	2	0	0
T41	0	2	0	0
T42	0	2	0	0
T60	506	0	0	0
T86	28043	0	0	0
T109	0	4	0	0
T136	510	0	0	0
T139	25984	0	0	0
T164	0	4	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0
T187	0	2	0	0
T188	0	2	0	0
T209	0	4	0	0
T213	0	2	0	0
T214	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1154	0	0
T34	50331	0	0	0
T39	928	66	0	0
T41	0	43	0	0
T42	0	73	0	0
T60	506	0	0	0
T86	28043	0	0	0
T109	0	70	0	0
T136	510	0	0	0
T139	25984	0	0	0
T164	0	64	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0
T187	0	88	0	0
T188	0	11	0	0
T209	0	60	0	0
T213	0	38	0	0
T214	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934758	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1480	0	0
T34	50331	0	0	0
T39	928	217	0	0
T41	0	40	0	0
T42	0	43	0	0
T60	506	0	0	0
T86	28043	0	0	0
T109	0	93	0	0
T136	510	0	0	0
T139	25984	0	0	0
T164	0	85	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0
T187	0	43	0	0
T188	0	60	0	0
T209	0	87	0	0
T213	0	78	0	0
T214	0	83	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	23	0	0
T34	50331	0	0	0
T39	928	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T60	506	0	0	0
T86	28043	0	0	0
T109	0	2	0	0
T136	510	0	0	0
T139	25984	0	0	0
T164	0	2	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	2	0	0
T213	0	1	0	0
T214	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8796205	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8798524	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	26	0	0
T34	50331	0	0	0
T39	928	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T60	506	0	0	0
T86	28043	0	0	0
T109	0	2	0	0
T136	510	0	0	0
T139	25984	0	0	0
T164	0	2	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	2	0	0
T213	0	1	0	0
T214	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	24	0	0
T34	50331	0	0	0
T39	928	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T60	506	0	0	0
T86	28043	0	0	0
T109	0	2	0	0
T136	510	0	0	0
T139	25984	0	0	0
T164	0	2	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	2	0	0
T213	0	1	0	0
T214	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	23	0	0
T34	50331	0	0	0
T39	928	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T60	506	0	0	0
T86	28043	0	0	0
T109	0	2	0	0
T136	510	0	0	0
T139	25984	0	0	0
T164	0	2	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	2	0	0
T213	0	1	0	0
T214	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	23	0	0
T34	50331	0	0	0
T39	928	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T60	506	0	0	0
T86	28043	0	0	0
T109	0	2	0	0
T136	510	0	0	0
T139	25984	0	0	0
T164	0	2	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	2	0	0
T213	0	1	0	0
T214	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1441	0	0
T34	50331	0	0	0
T39	928	215	0	0
T41	0	39	0	0
T42	0	42	0	0
T60	506	0	0	0
T86	28043	0	0	0
T109	0	90	0	0
T136	510	0	0	0
T139	25984	0	0	0
T164	0	82	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0
T187	0	41	0	0
T188	0	58	0	0
T209	0	84	0	0
T213	0	76	0	0
T214	0	80	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6337	0	0
T1	7156	21	0	0
T2	853	4	0	0
T3	5844	14	0	0
T4	522	4	0	0
T5	402	0	0	0
T6	1136	4	0	0
T7	0	26	0	0
T13	403	0	0	0
T14	4724	32	0	0
T15	2261	1	0	0
T16	1065	0	0	0
T24	0	5	0	0
T27	0	21	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	7	0	0
T41	618	1	0	0
T42	0	1	0	0
T106	22406	0	0	0
T109	0	1	0	0
T120	2610	0	0	0
T121	412	0	0	0
T122	602	0	0	0
T123	8473	0	0	0
T124	2372	0	0	0
T125	672	0	0	0
T126	16496	0	0	0
T127	499	0	0	0
T164	0	1	0	0
T209	0	1	0	0
T214	0	1	0	0
T215	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T14
1	1	Covered	T1,T4,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T11,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T11,T40

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T11,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T40
1	0	Covered	T1,T4,T14
1	1	Covered	T3,T11,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T40
0	1	Covered	T90
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T40
0	1	Covered	T3,T40,T42
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T40
1	-	Covered	T3,T40,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T40
DetectSt	168	Covered	T3,T11,T40
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T11,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T40
DebounceSt->IdleSt	163	Covered	T188,T165,T216
DetectSt->IdleSt	186	Covered	T90
DetectSt->StableSt	191	Covered	T3,T11,T40
IdleSt->DebounceSt	148	Covered	T3,T11,T40
StableSt->IdleSt	206	Covered	T3,T11,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T40
0	1	Covered	T3,T11,T40
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T40
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T188,T165,T198
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T40
DetectSt	-	-	-	-	1	-	-	Covered	T90
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T40,T42
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	95	0	0
CntIncr_A	9566120	13954	0	0
CntNoWrap_A	9566120	8934713	0	0
DetectStDropOut_A	9566120	1	0	0
DetectedOut_A	9566120	3262	0	0
DetectedPulseOut_A	9566120	44	0	0
DisabledIdleSt_A	9566120	8908467	0	0
DisabledNoDetection_A	9566120	8910783	0	0
EnterDebounceSt_A	9566120	52	0	0
EnterDetectSt_A	9566120	45	0	0
EnterStableSt_A	9566120	44	0	0
PulseIsPulse_A	9566120	44	0	0
StayInStableSt	9566120	3195	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	95	0	0
T3	5844	2	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T34	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T90	0	2	0	0
T186	0	2	0	0
T187	0	2	0	0
T188	0	3	0	0
T213	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	13954	0	0
T3	5844	100	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	100	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T34	0	45	0	0
T40	0	33	0	0
T42	0	16	0	0
T90	0	95	0	0
T186	0	31	0	0
T187	0	88	0	0
T188	0	22	0	0
T213	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934713	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1158	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1	0	0
T42	7599	0	0	0
T90	641	1	0	0
T187	629	0	0	0
T202	7392	0	0	0
T203	405	0	0	0
T204	502	0	0	0
T205	524	0	0	0
T206	429	0	0	0
T207	501	0	0	0
T208	638	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	3262	0	0
T3	5844	141	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	227	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T34	0	257	0	0
T40	0	18	0	0
T42	0	40	0	0
T186	0	55	0	0
T187	0	43	0	0
T188	0	60	0	0
T209	0	85	0	0
T213	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	44	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	2	0	0
T213	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8908467	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	581	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8910783	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	592	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	52	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T90	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	2	0	0
T213	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	45	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T90	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T213	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	44	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	2	0	0
T213	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	44	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	2	0	0
T213	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	3195	0	0
T3	5844	140	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	225	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T34	0	255	0	0
T40	0	17	0	0
T42	0	39	0	0
T186	0	54	0	0
T187	0	41	0	0
T188	0	58	0	0
T209	0	82	0	0
T213	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	20	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T40	0	1	0	0
T42	0	1	0	0
T96	0	1	0	0
T165	0	1	0	0
T186	0	1	0	0
T197	0	1	0	0
T198	0	2	0	0
T209	0	1	0	0
T217	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T14
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T14
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T40,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T40,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T40,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T40
1	0	Covered	T1,T4,T14
1	1	Covered	T3,T40,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T40,T39
0	1	Covered	T37
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T40,T39
0	1	Covered	T39,T209,T95
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T40,T39
1	-	Covered	T39,T209,T95

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T40,T39
DetectSt	168	Covered	T3,T40,T39
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T40,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T40,T39
DebounceSt->IdleSt	163	Covered	T87,T218
DetectSt->IdleSt	186	Covered	T37
DetectSt->StableSt	191	Covered	T3,T40,T39
IdleSt->DebounceSt	148	Covered	T3,T40,T39
StableSt->IdleSt	206	Covered	T3,T40,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T40,T39
0	1	Covered	T3,T40,T39
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T40,T39
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T40,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T40,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T218
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T40,T39
DetectSt	-	-	-	-	1	-	-	Covered	T37
DetectSt	-	-	-	-	0	1	-	Covered	T3,T40,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T39,T209,T95
StableSt	-	-	-	-	-	-	0	Covered	T3,T40,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	52	0	0
CntIncr_A	9566120	1217	0	0
CntNoWrap_A	9566120	8934756	0	0
DetectStDropOut_A	9566120	1	0	0
DetectedOut_A	9566120	1647	0	0
DetectedPulseOut_A	9566120	24	0	0
DisabledIdleSt_A	9566120	8921855	0	0
DisabledNoDetection_A	9566120	8924171	0	0
EnterDebounceSt_A	9566120	27	0	0
EnterDetectSt_A	9566120	25	0	0
EnterStableSt_A	9566120	24	0	0
PulseIsPulse_A	9566120	24	0	0
StayInStableSt	9566120	1607	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9566120	6075	0	0
gen_low_level_sva.LowLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	7	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	52	0	0
T3	5844	2	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	2	0	0
T39	0	4	0	0
T40	0	2	0	0
T90	0	2	0	0
T95	0	2	0	0
T164	0	2	0	0
T180	0	2	0	0
T186	0	2	0	0
T209	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1217	0	0
T3	5844	100	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	48	0	0
T39	0	132	0	0
T40	0	33	0	0
T90	0	95	0	0
T95	0	30	0	0
T164	0	32	0	0
T180	0	40	0	0
T186	0	31	0	0
T209	0	30	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934756	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1158	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1	0	0
T37	693	1	0	0
T58	497	0	0	0
T89	9480	0	0	0
T219	735	0	0	0
T220	502	0	0	0
T221	22821	0	0	0
T222	1606	0	0	0
T223	409	0	0	0
T224	436	0	0	0
T225	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1647	0	0
T3	5844	38	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	169	0	0
T40	0	45	0	0
T90	0	41	0	0
T95	0	20	0	0
T164	0	110	0	0
T165	0	41	0	0
T180	0	155	0	0
T186	0	200	0	0
T209	0	1	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	24	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T90	0	1	0	0
T95	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T180	0	1	0	0
T186	0	1	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8921855	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	581	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8924171	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	592	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	27	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T90	0	1	0	0
T95	0	1	0	0
T164	0	1	0	0
T180	0	1	0	0
T186	0	1	0	0
T209	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	25	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T37	0	1	0	0
T39	0	2	0	0
T40	0	1	0	0
T90	0	1	0	0
T95	0	1	0	0
T164	0	1	0	0
T180	0	1	0	0
T186	0	1	0	0
T209	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	24	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T90	0	1	0	0
T95	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T180	0	1	0	0
T186	0	1	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	24	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	2	0	0
T40	0	1	0	0
T90	0	1	0	0
T95	0	1	0	0
T164	0	1	0	0
T165	0	1	0	0
T180	0	1	0	0
T186	0	1	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1607	0	0
T3	5844	36	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	166	0	0
T40	0	43	0	0
T90	0	39	0	0
T95	0	19	0	0
T164	0	108	0	0
T165	0	39	0	0
T180	0	153	0	0
T186	0	198	0	0
T198	0	66	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6075	0	0
T1	7156	29	0	0
T2	853	0	0	0
T3	5844	15	0	0
T4	522	4	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	26	0	0
T13	403	0	0	0
T14	4724	22	0	0
T15	2261	3	0	0
T16	1065	0	0	0
T20	0	7	0	0
T23	0	3	0	0
T24	0	3	0	0
T27	0	23	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	7	0	0
T34	50331	0	0	0
T39	928	1	0	0
T60	506	0	0	0
T86	28043	0	0	0
T95	0	1	0	0
T136	510	0	0	0
T139	25984	0	0	0
T178	0	2	0	0
T182	425	0	0	0
T183	446	0	0	0
T184	31554	0	0	0
T185	621	0	0	0
T198	0	1	0	0
T209	0	1	0	0
T226	0	1	0	0