Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.84	95.65	95.24		100.00	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.84	95.65	95.24		100.00	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.85	100.00	90.48		100.00	100.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.70	93.48	100.00		100.00	90.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.70	93.48	100.00		100.00	90.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T14
1	1	Covered	T1,T4,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T4,T14
1	1	Covered	T3,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Not Covered
1	0	Covered	T87

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T3,T8,T11
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T9
1	-	Covered	T3,T8,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T9
DetectSt	168	Covered	T3,T8,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T9
DebounceSt->IdleSt	163	Covered	T3,T227,T197
DetectSt->IdleSt	186	Covered	T87
DetectSt->StableSt	191	Covered	T3,T8,T9
IdleSt->DebounceSt	148	Covered	T3,T8,T9
StableSt->IdleSt	206	Covered	T3,T8,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T14
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T227,T197
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T87
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	108	0	0
CntIncr_A	9566120	64460	0	0
CntNoWrap_A	9566120	8934700	0	0
DetectStDropOut_A	9566120	0	0	0
DetectedOut_A	9566120	127394	0	0
DetectedPulseOut_A	9566120	51	0	0
DisabledIdleSt_A	9566120	8662127	0	0
DisabledNoDetection_A	9566120	8664437	0	0
EnterDebounceSt_A	9566120	56	0	0
EnterDetectSt_A	9566120	52	0	0
EnterStableSt_A	9566120	51	0	0
PulseIsPulse_A	9566120	51	0	0
StayInStableSt	9566120	127317	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	108	0	0
T3	5844	3	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	2	0	0
T9	0	2	0	0
T11	0	4	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	6	0	0
T43	0	2	0	0
T47	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	64460	0	0
T3	5844	169	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	16	0	0
T9	0	27	0	0
T11	0	172	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	66	0	0
T40	0	60	0	0
T41	0	43	0	0
T42	0	105	0	0
T43	0	61712	0	0
T47	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934700	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1157	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	127394	0	0
T3	5844	170	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	2	0	0
T9	0	87	0	0
T11	0	159	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	235	0	0
T40	0	15	0	0
T41	0	41	0	0
T42	0	315	0	0
T43	0	123513	0	0
T47	0	26	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	51	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T47	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8662127	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	581	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8664437	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	592	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	56	0	0
T3	5844	2	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T47	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	52	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T47	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	51	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T47	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	51	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T47	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	127317	0	0
T3	5844	169	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	1	0	0
T9	0	85	0	0
T11	0	156	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	234	0	0
T40	0	14	0	0
T41	0	39	0	0
T42	0	311	0	0
T43	0	123511	0	0
T47	0	24	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	24	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	1	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T186	0	1	0	0
T188	0	1	0	0
T201	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T14
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T14
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T11,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T11,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T11,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T11
1	0	Covered	T1,T4,T14
1	1	Covered	T3,T11,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T39
0	1	Not Covered
1	0	Covered	T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T39
0	1	Covered	T11,T36,T42
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T39
1	-	Covered	T11,T36,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T39
DetectSt	168	Covered	T3,T11,T39
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T11,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T39
DebounceSt->IdleSt	163	Covered	T38,T87,T215
DetectSt->IdleSt	186	Covered	T50
DetectSt->StableSt	191	Covered	T3,T11,T39
IdleSt->DebounceSt	148	Covered	T3,T11,T39
StableSt->IdleSt	206	Covered	T3,T11,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T39
0	1	Covered	T3,T11,T39
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T39
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T38,T215
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T39
DetectSt	-	-	-	-	1	-	-	Covered	T50
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T36,T42
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	65	0	0
CntIncr_A	9566120	1710	0	0
CntNoWrap_A	9566120	8934743	0	0
DetectStDropOut_A	9566120	0	0	0
DetectedOut_A	9566120	1797	0	0
DetectedPulseOut_A	9566120	30	0	0
DisabledIdleSt_A	9566120	8659601	0	0
DisabledNoDetection_A	9566120	8661909	0	0
EnterDebounceSt_A	9566120	34	0	0
EnterDetectSt_A	9566120	31	0	0
EnterStableSt_A	9566120	30	0	0
PulseIsPulse_A	9566120	30	0	0
StayInStableSt	9566120	1749	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9566120	6148	0	0
gen_low_level_sva.LowLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	65	0	0
T3	5844	2	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T38	0	1	0	0
T39	0	2	0	0
T42	0	4	0	0
T186	0	2	0	0
T187	0	2	0	0
T188	0	2	0	0
T228	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1710	0	0
T3	5844	69	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	86	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	58	0	0
T38	0	19	0	0
T39	0	66	0	0
T42	0	89	0	0
T186	0	31	0	0
T187	0	88	0	0
T188	0	11	0	0
T228	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934743	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1158	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1797	0	0
T3	5844	42	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	40	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	99	0	0
T39	0	42	0	0
T42	0	46	0	0
T186	0	76	0	0
T187	0	43	0	0
T188	0	42	0	0
T209	0	42	0	0
T228	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	30	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	1	0	0
T228	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8659601	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	995	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8661909	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1007	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	34	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T228	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	31	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	1	0	0
T228	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	30	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	1	0	0
T228	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	30	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	1	0	0
T39	0	1	0	0
T42	0	2	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T209	0	1	0	0
T228	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1749	0	0
T3	5844	40	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	39	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	98	0	0
T39	0	40	0	0
T42	0	43	0	0
T186	0	74	0	0
T187	0	41	0	0
T188	0	40	0	0
T209	0	40	0	0
T228	0	40	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6148	0	0
T1	7156	28	0	0
T2	853	0	0	0
T3	5844	16	0	0
T4	522	2	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	24	0	0
T8	0	1	0	0
T13	403	0	0	0
T14	4724	23	0	0
T15	2261	2	0	0
T16	1065	0	0	0
T23	0	6	0	0
T24	0	3	0	0
T27	0	24	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	12	0	0
T11	14742	1	0	0
T12	591	0	0	0
T31	31828	0	0	0
T35	15717	0	0	0
T36	0	1	0	0
T40	16284	0	0	0
T42	0	1	0	0
T46	640	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T95	0	1	0	0
T117	0	1	0	0
T138	402	0	0	0
T150	422	0	0	0
T162	0	3	0	0
T197	0	1	0	0
T198	0	1	0	0
T212	0	1	0	0
T214	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T14
1	1	Covered	T1,T4,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T11,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T8,T11,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T8,T11,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T47
1	0	Covered	T1,T4,T14
1	1	Covered	T8,T11,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T39
0	1	Covered	T95,T96,T229
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T39
0	1	Covered	T11,T39,T37
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T39
1	-	Covered	T11,T39,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T39
DetectSt	168	Covered	T8,T11,T39
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T8,T11,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T39
DebounceSt->IdleSt	163	Covered	T91,T87,T218
DetectSt->IdleSt	186	Covered	T95,T96,T229
DetectSt->StableSt	191	Covered	T8,T11,T39
IdleSt->DebounceSt	148	Covered	T8,T11,T39
StableSt->IdleSt	206	Covered	T11,T39,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T39
0	1	Covered	T8,T11,T39
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T39
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T39
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T91,T218
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T39
DetectSt	-	-	-	-	1	-	-	Covered	T95,T96,T229
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T39,T37
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	103	0	0
CntIncr_A	9566120	2640	0	0
CntNoWrap_A	9566120	8934705	0	0
DetectStDropOut_A	9566120	3	0	0
DetectedOut_A	9566120	4436	0	0
DetectedPulseOut_A	9566120	47	0	0
DisabledIdleSt_A	9566120	8669855	0	0
DisabledNoDetection_A	9566120	8672169	0	0
EnterDebounceSt_A	9566120	53	0	0
EnterDetectSt_A	9566120	50	0	0
EnterStableSt_A	9566120	47	0	0
PulseIsPulse_A	9566120	47	0	0
StayInStableSt	9566120	4362	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	103	0	0
T8	483	2	0	0
T9	524	0	0	0
T10	18578	0	0	0
T11	14742	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T39	0	4	0	0
T41	0	2	0	0
T45	12753	0	0	0
T91	0	1	0	0
T109	0	4	0	0
T164	0	2	0	0
T213	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	2640	0	0
T8	483	16	0	0
T9	524	0	0	0
T10	18578	0	0	0
T11	14742	100	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T34	0	45	0	0
T37	0	48	0	0
T39	0	132	0	0
T41	0	43	0	0
T45	12753	0	0	0
T91	0	96	0	0
T109	0	74	0	0
T164	0	32	0	0
T213	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934705	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	3	0	0
T95	719	1	0	0
T96	0	1	0	0
T165	6713	0	0	0
T229	0	1	0	0
T230	17027	0	0	0
T231	946	0	0	0
T232	503	0	0	0
T233	12445	0	0	0
T234	616	0	0	0
T235	36690	0	0	0
T236	5170	0	0	0
T237	19780	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	4436	0	0
T8	483	58	0	0
T9	524	0	0	0
T10	18578	0	0	0
T11	14742	85	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T34	0	122	0	0
T37	0	42	0	0
T39	0	318	0	0
T41	0	166	0	0
T45	12753	0	0	0
T109	0	219	0	0
T164	0	182	0	0
T186	0	133	0	0
T213	0	78	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	47	0	0
T8	483	1	0	0
T9	524	0	0	0
T10	18578	0	0	0
T11	14742	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T45	12753	0	0	0
T109	0	2	0	0
T164	0	1	0	0
T186	0	2	0	0
T213	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8669855	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8672169	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	53	0	0
T8	483	1	0	0
T9	524	0	0	0
T10	18578	0	0	0
T11	14742	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T45	12753	0	0	0
T91	0	1	0	0
T109	0	2	0	0
T164	0	1	0	0
T213	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	50	0	0
T8	483	1	0	0
T9	524	0	0	0
T10	18578	0	0	0
T11	14742	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T45	12753	0	0	0
T109	0	2	0	0
T164	0	1	0	0
T186	0	2	0	0
T213	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	47	0	0
T8	483	1	0	0
T9	524	0	0	0
T10	18578	0	0	0
T11	14742	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T45	12753	0	0	0
T109	0	2	0	0
T164	0	1	0	0
T186	0	2	0	0
T213	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	47	0	0
T8	483	1	0	0
T9	524	0	0	0
T10	18578	0	0	0
T11	14742	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T39	0	2	0	0
T41	0	1	0	0
T45	12753	0	0	0
T109	0	2	0	0
T164	0	1	0	0
T186	0	2	0	0
T213	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	4362	0	0
T8	483	56	0	0
T9	524	0	0	0
T10	18578	0	0	0
T11	14742	84	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T34	0	120	0	0
T37	0	41	0	0
T39	0	315	0	0
T41	0	164	0	0
T45	12753	0	0	0
T109	0	216	0	0
T164	0	180	0	0
T186	0	130	0	0
T213	0	76	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	19	0	0
T11	14742	1	0	0
T12	591	0	0	0
T31	31828	0	0	0
T35	15717	0	0	0
T37	0	1	0	0
T39	0	1	0	0
T40	16284	0	0	0
T46	640	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T95	0	1	0	0
T109	0	1	0	0
T117	0	2	0	0
T138	402	0	0	0
T150	422	0	0	0
T161	0	1	0	0
T165	0	2	0	0
T181	0	1	0	0
T186	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T14
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T14
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T37,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T11,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T37,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T11
1	0	Covered	T1,T4,T14
1	1	Covered	T3,T11,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T37,T38
0	1	Covered	T227
1	0	Covered	T87

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T37,T38
0	1	Covered	T163,T186,T95
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T37,T38
1	-	Covered	T163,T186,T95

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T37
DetectSt	168	Covered	T3,T37,T38
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T37,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T37,T38
DebounceSt->IdleSt	163	Covered	T11,T238
DetectSt->IdleSt	186	Covered	T227,T87
DetectSt->StableSt	191	Covered	T3,T37,T38
IdleSt->DebounceSt	148	Covered	T3,T11,T37
StableSt->IdleSt	206	Covered	T3,T163,T186

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T37,T38
0	1	Covered	T3,T11,T37
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T37,T38
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T37
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T37,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T37
DetectSt	-	-	-	-	1	-	-	Covered	T227,T87
DetectSt	-	-	-	-	0	1	-	Covered	T3,T37,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T163,T186,T95
StableSt	-	-	-	-	-	-	0	Covered	T3,T37,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	56	0	0
CntIncr_A	9566120	1427	0	0
CntNoWrap_A	9566120	8934752	0	0
DetectStDropOut_A	9566120	1	0	0
DetectedOut_A	9566120	2226	0	0
DetectedPulseOut_A	9566120	26	0	0
DisabledIdleSt_A	9566120	8666255	0	0
DisabledNoDetection_A	9566120	8668569	0	0
EnterDebounceSt_A	9566120	30	0	0
EnterDetectSt_A	9566120	28	0	0
EnterStableSt_A	9566120	26	0	0
PulseIsPulse_A	9566120	26	0	0
StayInStableSt	9566120	2188	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9566120	6018	0	0
gen_low_level_sva.LowLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	56	0	0
T3	5844	2	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T91	0	2	0	0
T95	0	4	0	0
T163	0	4	0	0
T186	0	2	0	0
T209	0	2	0	0
T227	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1427	0	0
T3	5844	100	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	56	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	58	0	0
T37	0	48	0	0
T38	0	19	0	0
T91	0	96	0	0
T163	0	68	0	0
T186	0	31	0	0
T209	0	30	0	0
T227	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934752	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1158	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1	0	0
T227	648	1	0	0
T239	763	0	0	0
T240	447	0	0	0
T241	32943	0	0	0
T242	403	0	0	0
T243	422	0	0	0
T244	504	0	0	0
T245	502	0	0	0
T246	489	0	0	0
T247	1343	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	2226	0	0
T3	5844	280	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	39	0	0
T37	0	93	0	0
T38	0	56	0	0
T91	0	51	0	0
T95	0	81	0	0
T163	0	71	0	0
T165	0	39	0	0
T186	0	78	0	0
T209	0	73	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	26	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T91	0	1	0	0
T95	0	2	0	0
T163	0	2	0	0
T165	0	1	0	0
T186	0	1	0	0
T209	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8666255	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	746	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8668569	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	758	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	30	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T91	0	1	0	0
T163	0	2	0	0
T186	0	1	0	0
T209	0	1	0	0
T227	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	28	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T91	0	1	0	0
T95	0	2	0	0
T163	0	2	0	0
T186	0	1	0	0
T209	0	1	0	0
T227	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	26	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T91	0	1	0	0
T95	0	2	0	0
T163	0	2	0	0
T165	0	1	0	0
T186	0	1	0	0
T209	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	26	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T91	0	1	0	0
T95	0	2	0	0
T163	0	2	0	0
T165	0	1	0	0
T186	0	1	0	0
T209	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	2188	0	0
T3	5844	278	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	37	0	0
T37	0	91	0	0
T38	0	54	0	0
T91	0	49	0	0
T95	0	79	0	0
T163	0	68	0	0
T165	0	38	0	0
T186	0	77	0	0
T209	0	71	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6018	0	0
T1	7156	28	0	0
T2	853	0	0	0
T3	5844	14	0	0
T4	522	5	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	31	0	0
T13	403	0	0	0
T14	4724	30	0	0
T15	2261	1	0	0
T16	1065	0	0	0
T20	0	4	0	0
T23	0	4	0	0
T24	0	2	0	0
T27	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	13	0	0
T42	7599	0	0	0
T73	0	1	0	0
T90	641	0	0	0
T95	0	2	0	0
T96	0	1	0	0
T117	0	1	0	0
T162	0	1	0	0
T163	27187	1	0	0
T165	0	1	0	0
T186	0	1	0	0
T202	7392	0	0	0
T203	405	0	0	0
T204	502	0	0	0
T205	524	0	0	0
T206	429	0	0	0
T207	501	0	0	0
T208	638	0	0	0
T212	0	1	0	0
T217	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T14
1	1	Covered	T1,T4,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T3,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T4,T14
1	1	Covered	T3,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T9
0	1	Covered	T9,T11,T43
1	0	Covered	T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T9
1	-	Covered	T9,T11,T43

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T9
DetectSt	168	Covered	T3,T8,T9
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T9
DebounceSt->IdleSt	163	Covered	T3,T41,T188
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T8,T9
IdleSt->DebounceSt	148	Covered	T3,T8,T9
StableSt->IdleSt	206	Covered	T3,T9,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T9
0	1	Covered	T3,T8,T9
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T9
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T87
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T41,T188
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T11,T43
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	103	0	0
CntIncr_A	9566120	125854	0	0
CntNoWrap_A	9566120	8934705	0	0
DetectStDropOut_A	9566120	0	0	0
DetectedOut_A	9566120	67280	0	0
DetectedPulseOut_A	9566120	49	0	0
DisabledIdleSt_A	9566120	8665880	0	0
DisabledNoDetection_A	9566120	8668196	0	0
EnterDebounceSt_A	9566120	54	0	0
EnterDetectSt_A	9566120	49	0	0
EnterStableSt_A	9566120	49	0	0
PulseIsPulse_A	9566120	49	0	0
StayInStableSt	9566120	67209	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	103	0	0
T3	5844	3	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	2	0	0
T9	0	2	0	0
T11	0	4	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	4	0	0
T37	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	4	0	0
T44	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	125854	0	0
T3	5844	200	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	16	0	0
T9	0	27	0	0
T11	0	186	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	116	0	0
T37	0	48	0	0
T40	0	33	0	0
T41	0	43	0	0
T43	0	123424	0	0
T44	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934705	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1157	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	67280	0	0
T3	5844	139	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	39	0	0
T9	0	15	0	0
T11	0	75	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	251	0	0
T37	0	184	0	0
T40	0	96	0	0
T42	0	220	0	0
T43	0	63234	0	0
T44	0	149	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	49	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8665880	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	746	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8668196	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	758	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	54	0	0
T3	5844	2	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	49	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	49	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	49	0	0
T3	5844	1	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	1	0	0
T9	0	1	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	2	0	0
T37	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T43	0	2	0	0
T44	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	67209	0	0
T3	5844	137	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T8	483	37	0	0
T9	0	14	0	0
T11	0	72	0	0
T20	492	0	0	0
T21	489	0	0	0
T23	523	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T36	0	248	0	0
T37	0	182	0	0
T40	0	94	0	0
T42	0	219	0	0
T43	0	63231	0	0
T44	0	147	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	25	0	0
T9	524	1	0	0
T10	18578	0	0	0
T11	14742	1	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T35	15717	0	0	0
T36	0	1	0	0
T40	16284	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	640	0	0	0
T79	402	0	0	0
T109	0	1	0	0
T201	0	1	0	0
T209	0	2	0	0
T227	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T14
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T14
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T34,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T9,T34,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T9,T34,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T11
1	0	Covered	T1,T4,T14
1	1	Covered	T9,T34,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T34,T36
0	1	Covered	T248
1	0	Covered	T87,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T34,T36
0	1	Covered	T36,T44,T188
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T34,T36
1	-	Covered	T36,T44,T188

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T34,T43
DetectSt	168	Covered	T9,T34,T36
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T9,T34,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T34,T36
DebounceSt->IdleSt	163	Covered	T43
DetectSt->IdleSt	186	Covered	T87,T50,T248
DetectSt->StableSt	191	Covered	T9,T34,T36
IdleSt->DebounceSt	148	Covered	T9,T34,T43
StableSt->IdleSt	206	Covered	T34,T36,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T34,T43
0	1	Covered	T9,T34,T43
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T34,T36
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T34,T43
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T34,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T43
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T34,T43
DetectSt	-	-	-	-	1	-	-	Covered	T87,T50,T248
DetectSt	-	-	-	-	0	1	-	Covered	T9,T34,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T36,T44,T188
StableSt	-	-	-	-	-	-	0	Covered	T9,T34,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	51	0	0
CntIncr_A	9566120	62966	0	0
CntNoWrap_A	9566120	8934757	0	0
DetectStDropOut_A	9566120	1	0	0
DetectedOut_A	9566120	1274	0	0
DetectedPulseOut_A	9566120	22	0	0
DisabledIdleSt_A	9566120	8549311	0	0
DisabledNoDetection_A	9566120	8551625	0	0
EnterDebounceSt_A	9566120	26	0	0
EnterDetectSt_A	9566120	25	0	0
EnterStableSt_A	9566120	22	0	0
PulseIsPulse_A	9566120	22	0	0
StayInStableSt	9566120	1238	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	9566120	6747	0	0
gen_low_level_sva.LowLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	51	0	0
T9	524	2	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T34	0	2	0	0
T35	15717	0	0	0
T36	0	2	0	0
T40	16284	0	0	0
T43	0	1	0	0
T44	0	4	0	0
T46	640	0	0	0
T79	402	0	0	0
T163	0	2	0	0
T164	0	2	0	0
T180	0	2	0	0
T188	0	2	0	0
T200	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	62966	0	0
T9	524	27	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T34	0	45	0	0
T35	15717	0	0	0
T36	0	58	0	0
T40	16284	0	0	0
T43	0	61712	0	0
T44	0	78	0	0
T46	640	0	0	0
T79	402	0	0	0
T163	0	34	0	0
T164	0	32	0	0
T180	0	40	0	0
T188	0	11	0	0
T200	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8934757	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1	0	0
T248	2520	1	0	0
T249	441	0	0	0
T250	609	0	0	0
T251	25659	0	0	0
T252	402	0	0	0
T253	426	0	0	0
T254	525	0	0	0
T255	18005	0	0	0
T256	585	0	0	0
T257	19332	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1274	0	0
T9	524	44	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T34	0	44	0	0
T35	15717	0	0	0
T36	0	112	0	0
T40	16284	0	0	0
T44	0	68	0	0
T46	640	0	0	0
T79	402	0	0	0
T91	0	50	0	0
T163	0	53	0	0
T164	0	46	0	0
T180	0	38	0	0
T188	0	43	0	0
T200	0	46	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	22	0	0
T9	524	1	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T34	0	1	0	0
T35	15717	0	0	0
T36	0	1	0	0
T40	16284	0	0	0
T44	0	2	0	0
T46	640	0	0	0
T79	402	0	0	0
T91	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T180	0	1	0	0
T188	0	1	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8549311	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8551625	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	26	0	0
T9	524	1	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T34	0	1	0	0
T35	15717	0	0	0
T36	0	1	0	0
T40	16284	0	0	0
T43	0	1	0	0
T44	0	2	0	0
T46	640	0	0	0
T79	402	0	0	0
T163	0	1	0	0
T164	0	1	0	0
T180	0	1	0	0
T188	0	1	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	25	0	0
T9	524	1	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T34	0	1	0	0
T35	15717	0	0	0
T36	0	1	0	0
T40	16284	0	0	0
T44	0	2	0	0
T46	640	0	0	0
T79	402	0	0	0
T91	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T180	0	1	0	0
T188	0	1	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	22	0	0
T9	524	1	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T34	0	1	0	0
T35	15717	0	0	0
T36	0	1	0	0
T40	16284	0	0	0
T44	0	2	0	0
T46	640	0	0	0
T79	402	0	0	0
T91	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T180	0	1	0	0
T188	0	1	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	22	0	0
T9	524	1	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T34	0	1	0	0
T35	15717	0	0	0
T36	0	1	0	0
T40	16284	0	0	0
T44	0	2	0	0
T46	640	0	0	0
T79	402	0	0	0
T91	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T180	0	1	0	0
T188	0	1	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1238	0	0
T9	524	42	0	0
T10	18578	0	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T34	0	42	0	0
T35	15717	0	0	0
T36	0	111	0	0
T40	16284	0	0	0
T44	0	65	0	0
T46	640	0	0	0
T79	402	0	0	0
T91	0	48	0	0
T163	0	51	0	0
T164	0	44	0	0
T180	0	36	0	0
T188	0	42	0	0
T200	0	44	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	6747	0	0
T1	7156	25	0	0
T2	853	4	0	0
T3	5844	20	0	0
T4	522	6	0	0
T5	402	0	0	0
T6	1136	4	0	0
T13	403	0	0	0
T14	4724	21	0	0
T15	2261	1	0	0
T16	1065	0	0	0
T24	0	6	0	0
T25	0	3	0	0
T27	0	27	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8	0	0
T36	949	1	0	0
T44	0	1	0	0
T95	0	1	0	0
T162	0	1	0	0
T188	0	1	0	0
T248	0	1	0	0
T258	0	1	0	0
T259	0	1	0	0
T260	521	0	0	0
T261	626659	0	0	0
T262	504	0	0	0
T263	777	0	0	0
T264	524	0	0	0
T265	422	0	0	0
T266	10106	0	0	0
T267	407	0	0	0
T268	15933	0	0	0