Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T27
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T7,T45
1	1	Covered	T1,T14,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T27
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T35,T32

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T33
0	1	Covered	T7,T45,T33
1	0	Covered	T92,T94,T115

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T45,T33
1	-	Covered	T7,T45,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T27
DetectSt	168	Covered	T1,T14,T27
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T45,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T27
DebounceSt->IdleSt	163	Covered	T100,T269,T87
DetectSt->IdleSt	186	Covered	T1,T14,T27
DetectSt->StableSt	191	Covered	T7,T45,T33
IdleSt->DebounceSt	148	Covered	T1,T14,T27
StableSt->IdleSt	206	Covered	T7,T45,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T27
0	1	Covered	T1,T14,T27
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T27
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T27
IdleSt	0	-	-	-	-	-	-	Covered	T1,T14,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T100,T269,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T27
DetectSt	-	-	-	-	1	-	-	Covered	T1,T14,T27
DetectSt	-	-	-	-	0	1	-	Covered	T7,T45,T33
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T27
StableSt	-	-	-	-	-	-	1	Covered	T7,T45,T33
StableSt	-	-	-	-	-	-	0	Covered	T7,T45,T33
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	2820	0	0
CntIncr_A	9566120	99881	0	0
CntNoWrap_A	9566120	8931988	0	0
DetectStDropOut_A	9566120	291	0	0
DetectedOut_A	9566120	76645	0	0
DetectedPulseOut_A	9566120	992	0	0
DisabledIdleSt_A	9566120	8465389	0	0
DisabledNoDetection_A	9566120	8467553	0	0
EnterDebounceSt_A	9566120	1422	0	0
EnterDetectSt_A	9566120	1398	0	0
EnterStableSt_A	9566120	992	0	0
PulseIsPulse_A	9566120	992	0	0
StayInStableSt	9566120	75546	0	0
gen_high_event_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	875	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	2820	0	0
T1	7156	48	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	24	0	0
T13	403	0	0	0
T14	4724	30	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	54	0	0
T32	0	20	0	0
T33	0	26	0	0
T35	0	60	0	0
T45	0	20	0	0
T61	0	38	0	0
T62	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	99881	0	0
T1	7156	1517	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	420	0	0
T13	403	0	0	0
T14	4724	622	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	1294	0	0
T32	0	586	0	0
T33	0	3861	0	0
T35	0	2192	0	0
T45	0	770	0	0
T61	0	1273	0	0
T62	0	354	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8931988	0	0
T1	7156	6707	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4293	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	291	0	0
T1	7156	16	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T13	403	0	0	0
T14	4724	15	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	27	0	0
T32	0	7	0	0
T35	0	26	0	0
T104	0	19	0	0
T105	0	10	0	0
T111	0	7	0	0
T114	0	25	0	0
T115	0	8	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	76645	0	0
T7	10904	1096	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T33	0	3490	0	0
T45	12753	392	0	0
T61	0	1764	0	0
T62	0	177	0	0
T88	0	59	0	0
T89	0	2474	0	0
T92	0	2	0	0
T93	0	291	0	0
T136	0	85	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	992	0	0
T7	10904	12	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T33	0	13	0	0
T45	12753	10	0	0
T61	0	19	0	0
T62	0	6	0	0
T88	0	13	0	0
T89	0	25	0	0
T92	0	2	0	0
T93	0	11	0	0
T136	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8465389	0	0
T1	7156	3407	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	2014	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8467553	0	0
T1	7156	3407	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	2014	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1422	0	0
T1	7156	24	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	12	0	0
T13	403	0	0	0
T14	4724	15	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	27	0	0
T32	0	10	0	0
T33	0	13	0	0
T35	0	30	0	0
T45	0	10	0	0
T61	0	19	0	0
T62	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1398	0	0
T1	7156	24	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	12	0	0
T13	403	0	0	0
T14	4724	15	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	27	0	0
T32	0	10	0	0
T33	0	13	0	0
T35	0	30	0	0
T45	0	10	0	0
T61	0	19	0	0
T62	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	992	0	0
T7	10904	12	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T33	0	13	0	0
T45	12753	10	0	0
T61	0	19	0	0
T62	0	6	0	0
T88	0	13	0	0
T89	0	25	0	0
T92	0	2	0	0
T93	0	11	0	0
T136	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	992	0	0
T7	10904	12	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T33	0	13	0	0
T45	12753	10	0	0
T61	0	19	0	0
T62	0	6	0	0
T88	0	13	0	0
T89	0	25	0	0
T92	0	2	0	0
T93	0	11	0	0
T136	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	75546	0	0
T7	10904	1084	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T33	0	3472	0	0
T45	12753	380	0	0
T61	0	1744	0	0
T62	0	171	0	0
T88	0	46	0	0
T89	0	2449	0	0
T93	0	280	0	0
T136	0	83	0	0
T270	0	37	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	875	0	0
T7	10904	12	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T33	0	8	0	0
T45	12753	8	0	0
T61	0	18	0	0
T62	0	6	0	0
T88	0	13	0	0
T89	0	25	0	0
T93	0	11	0	0
T270	0	1	0	0
T271	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T15
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T15
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T15,T7,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T15,T7,T45

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T45,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T15,T7,T45
1	0	Covered	T1,T14,T15
1	1	Covered	T15,T7,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T10
0	1	Covered	T106,T107,T108
1	0	Covered	T87,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T10
0	1	Covered	T7,T10,T11
1	0	Covered	T89,T87

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T45,T10
1	-	Covered	T7,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T15,T7,T45
DetectSt	168	Covered	T7,T45,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T45,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T45,T10
DebounceSt->IdleSt	163	Covered	T15,T11,T157
DetectSt->IdleSt	186	Covered	T106,T107,T108
DetectSt->StableSt	191	Covered	T7,T45,T10
IdleSt->DebounceSt	148	Covered	T15,T7,T45
StableSt->IdleSt	206	Covered	T7,T45,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T15,T7,T45
0	1	Covered	T15,T7,T45
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T45,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T15,T7,T45
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T45,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T11,T157
DebounceSt	-	0	0	-	-	-	-	Covered	T15,T7,T45
DetectSt	-	-	-	-	1	-	-	Covered	T106,T107,T108
DetectSt	-	-	-	-	0	1	-	Covered	T7,T45,T10
DetectSt	-	-	-	-	0	0	-	Covered	T7,T45,T10
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T45,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	899	0	0
CntIncr_A	9566120	48898	0	0
CntNoWrap_A	9566120	8933909	0	0
DetectStDropOut_A	9566120	39	0	0
DetectedOut_A	9566120	14617	0	0
DetectedPulseOut_A	9566120	373	0	0
DisabledIdleSt_A	9566120	8552619	0	0
DisabledNoDetection_A	9566120	8554165	0	0
EnterDebounceSt_A	9566120	484	0	0
EnterDetectSt_A	9566120	416	0	0
EnterStableSt_A	9566120	373	0	0
PulseIsPulse_A	9566120	373	0	0
StayInStableSt	9566120	14226	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	351	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	899	0	0
T2	853	0	0	0
T3	5844	0	0	0
T6	1136	0	0	0
T7	10904	8	0	0
T8	483	0	0	0
T10	0	14	0	0
T11	0	4	0	0
T15	2261	1	0	0
T16	1065	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T31	0	12	0	0
T33	0	10	0	0
T40	0	2	0	0
T45	0	4	0	0
T47	0	4	0	0
T61	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	48898	0	0
T2	853	0	0	0
T3	5844	0	0	0
T6	1136	0	0	0
T7	10904	256	0	0
T8	483	0	0	0
T10	0	651	0	0
T11	0	65	0	0
T15	2261	20	0	0
T16	1065	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T31	0	1116	0	0
T33	0	1430	0	0
T40	0	25	0	0
T45	0	128	0	0
T47	0	244	0	0
T61	0	70	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8933909	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	256	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	39	0	0
T106	22406	6	0	0
T107	0	2	0	0
T108	0	1	0	0
T109	0	2	0	0
T112	0	1	0	0
T113	0	2	0	0
T116	0	3	0	0
T117	0	2	0	0
T118	0	2	0	0
T119	0	12	0	0
T120	2610	0	0	0
T121	412	0	0	0
T122	602	0	0	0
T123	8473	0	0	0
T124	2372	0	0	0
T125	672	0	0	0
T126	16496	0	0	0
T127	499	0	0	0
T128	652	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	14617	0	0
T7	10904	188	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	388	0	0
T11	0	3	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	37	0	0
T33	0	315	0	0
T40	0	3	0	0
T45	12753	147	0	0
T47	0	42	0	0
T61	0	78	0	0
T136	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	373	0	0
T7	10904	4	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	7	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	6	0	0
T33	0	5	0	0
T40	0	1	0	0
T45	12753	2	0	0
T47	0	2	0	0
T61	0	1	0	0
T136	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8552619	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	223	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8554165	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	226	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	484	0	0
T2	853	0	0	0
T3	5844	0	0	0
T6	1136	0	0	0
T7	10904	4	0	0
T8	483	0	0	0
T10	0	7	0	0
T11	0	3	0	0
T15	2261	1	0	0
T16	1065	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	0	0	0
T31	0	6	0	0
T33	0	5	0	0
T40	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T61	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	416	0	0
T7	10904	4	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	7	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	6	0	0
T33	0	5	0	0
T40	0	1	0	0
T45	12753	2	0	0
T47	0	2	0	0
T61	0	1	0	0
T136	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	373	0	0
T7	10904	4	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	7	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	6	0	0
T33	0	5	0	0
T40	0	1	0	0
T45	12753	2	0	0
T47	0	2	0	0
T61	0	1	0	0
T136	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	373	0	0
T7	10904	4	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	7	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	6	0	0
T33	0	5	0	0
T40	0	1	0	0
T45	12753	2	0	0
T47	0	2	0	0
T61	0	1	0	0
T136	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	14226	0	0
T7	10904	184	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	381	0	0
T11	0	2	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	31	0	0
T33	0	310	0	0
T40	0	2	0	0
T45	12753	143	0	0
T47	0	40	0	0
T61	0	76	0	0
T136	0	3	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	351	0	0
T7	10904	4	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	7	0	0
T11	0	1	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	6	0	0
T33	0	5	0	0
T34	0	4	0	0
T40	0	1	0	0
T45	12753	0	0	0
T47	0	2	0	0
T136	0	1	0	0
T139	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T27
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T7,T45
1	1	Covered	T1,T14,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T27
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T33,T104

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T35
0	1	Covered	T7,T45,T35
1	0	Covered	T272,T87,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T45,T35
1	-	Covered	T7,T45,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T27
DetectSt	168	Covered	T1,T14,T27
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T45,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T27
DebounceSt->IdleSt	163	Covered	T100,T269,T87
DetectSt->IdleSt	186	Covered	T1,T14,T27
DetectSt->StableSt	191	Covered	T7,T45,T35
IdleSt->DebounceSt	148	Covered	T1,T14,T27
StableSt->IdleSt	206	Covered	T7,T45,T35

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T27
0	1	Covered	T1,T14,T27
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T27
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T27
IdleSt	0	-	-	-	-	-	-	Covered	T1,T14,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T100,T269,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T27
DetectSt	-	-	-	-	1	-	-	Covered	T1,T14,T27
DetectSt	-	-	-	-	0	1	-	Covered	T7,T45,T35
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T27
StableSt	-	-	-	-	-	-	1	Covered	T7,T45,T35
StableSt	-	-	-	-	-	-	0	Covered	T7,T45,T35
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	2994	0	0
CntIncr_A	9566120	98956	0	0
CntNoWrap_A	9566120	8931814	0	0
DetectStDropOut_A	9566120	279	0	0
DetectedOut_A	9566120	76907	0	0
DetectedPulseOut_A	9566120	1064	0	0
DisabledIdleSt_A	9566120	8468115	0	0
DisabledNoDetection_A	9566120	8470276	0	0
EnterDebounceSt_A	9566120	1513	0	0
EnterDetectSt_A	9566120	1482	0	0
EnterStableSt_A	9566120	1064	0	0
PulseIsPulse_A	9566120	1064	0	0
StayInStableSt	9566120	75732	0	0
gen_high_event_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	950	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	2994	0	0
T1	7156	12	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	22	0	0
T13	403	0	0	0
T14	4724	42	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	54	0	0
T32	0	22	0	0
T33	0	42	0	0
T35	0	12	0	0
T45	0	34	0	0
T61	0	54	0	0
T62	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	98956	0	0
T1	7156	378	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	462	0	0
T13	403	0	0	0
T14	4724	877	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	1294	0	0
T32	0	627	0	0
T33	0	6654	0	0
T35	0	402	0	0
T45	0	1445	0	0
T61	0	1863	0	0
T62	0	300	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8931814	0	0
T1	7156	6743	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4281	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	279	0	0
T1	7156	3	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T13	403	0	0	0
T14	4724	21	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	27	0	0
T33	0	6	0	0
T104	0	8	0	0
T105	0	13	0	0
T111	0	13	0	0
T114	0	13	0	0
T272	0	1	0	0
T273	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	76907	0	0
T7	10904	513	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T32	0	2632	0	0
T35	0	482	0	0
T45	12753	1757	0	0
T61	0	537	0	0
T62	0	230	0	0
T88	0	317	0	0
T89	0	87	0	0
T92	0	1807	0	0
T93	0	125	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1064	0	0
T7	10904	11	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T32	0	11	0	0
T35	0	6	0	0
T45	12753	17	0	0
T61	0	27	0	0
T62	0	6	0	0
T88	0	14	0	0
T89	0	3	0	0
T92	0	27	0	0
T93	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8468115	0	0
T1	7156	3407	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	2014	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8470276	0	0
T1	7156	3407	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	2014	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1513	0	0
T1	7156	6	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	11	0	0
T13	403	0	0	0
T14	4724	21	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	27	0	0
T32	0	11	0	0
T33	0	21	0	0
T35	0	6	0	0
T45	0	17	0	0
T61	0	27	0	0
T62	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1482	0	0
T1	7156	6	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	11	0	0
T13	403	0	0	0
T14	4724	21	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	27	0	0
T32	0	11	0	0
T33	0	21	0	0
T35	0	6	0	0
T45	0	17	0	0
T61	0	27	0	0
T62	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1064	0	0
T7	10904	11	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T32	0	11	0	0
T35	0	6	0	0
T45	12753	17	0	0
T61	0	27	0	0
T62	0	6	0	0
T88	0	14	0	0
T89	0	3	0	0
T92	0	27	0	0
T93	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1064	0	0
T7	10904	11	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T32	0	11	0	0
T35	0	6	0	0
T45	12753	17	0	0
T61	0	27	0	0
T62	0	6	0	0
T88	0	14	0	0
T89	0	3	0	0
T92	0	27	0	0
T93	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	75732	0	0
T7	10904	500	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T32	0	2615	0	0
T35	0	475	0	0
T45	12753	1738	0	0
T61	0	509	0	0
T62	0	224	0	0
T88	0	303	0	0
T89	0	84	0	0
T92	0	1779	0	0
T93	0	117	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	950	0	0
T7	10904	9	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T32	0	5	0	0
T35	0	5	0	0
T45	12753	15	0	0
T61	0	26	0	0
T62	0	6	0	0
T88	0	14	0	0
T89	0	3	0	0
T92	0	26	0	0
T93	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T27
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T45,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T7,T45,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T45,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T45,T10
1	0	Covered	T1,T14,T15
1	1	Covered	T7,T45,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T10
0	1	Covered	T86,T107,T274
1	0	Covered	T87,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T10
0	1	Covered	T7,T10,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T45,T10
1	-	Covered	T7,T10,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T45,T10
DetectSt	168	Covered	T7,T45,T10
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T45,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T45,T10
DebounceSt->IdleSt	163	Covered	T10,T31,T40
DetectSt->IdleSt	186	Covered	T86,T107,T274
DetectSt->StableSt	191	Covered	T7,T45,T10
IdleSt->DebounceSt	148	Covered	T7,T45,T10
StableSt->IdleSt	206	Covered	T7,T45,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T45,T10
0	1	Covered	T7,T45,T10
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T45,T10
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T45,T10
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T45,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T31,T32
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T45,T10
DetectSt	-	-	-	-	1	-	-	Covered	T86,T107,T274
DetectSt	-	-	-	-	0	1	-	Covered	T7,T45,T10
DetectSt	-	-	-	-	0	0	-	Covered	T7,T45,T10
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T31
StableSt	-	-	-	-	-	-	0	Covered	T7,T45,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	910	0	0
CntIncr_A	9566120	50652	0	0
CntNoWrap_A	9566120	8933898	0	0
DetectStDropOut_A	9566120	58	0	0
DetectedOut_A	9566120	14631	0	0
DetectedPulseOut_A	9566120	369	0	0
DisabledIdleSt_A	9566120	8552088	0	0
DisabledNoDetection_A	9566120	8553680	0	0
EnterDebounceSt_A	9566120	480	0	0
EnterDetectSt_A	9566120	431	0	0
EnterStableSt_A	9566120	369	0	0
PulseIsPulse_A	9566120	369	0	0
StayInStableSt	9566120	14234	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	339	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	910	0	0
T7	10904	4	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	7	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	13	0	0
T32	0	13	0	0
T34	0	22	0	0
T35	0	2	0	0
T40	0	2	0	0
T45	12753	4	0	0
T139	0	14	0	0
T184	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	50652	0	0
T7	10904	74	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	485	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	1097	0	0
T32	0	617	0	0
T34	0	583	0	0
T35	0	75	0	0
T40	0	139	0	0
T45	12753	172	0	0
T139	0	1211	0	0
T184	0	754	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8933898	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	58	0	0
T48	3032	0	0	0
T52	1087	0	0	0
T56	495	0	0	0
T57	43191	0	0	0
T73	0	1	0	0
T86	28043	2	0	0
T88	6151	0	0	0
T107	0	12	0	0
T117	0	4	0	0
T118	0	1	0	0
T274	0	4	0	0
T275	0	1	0	0
T276	0	3	0	0
T277	0	1	0	0
T278	0	3	0	0
T279	422	0	0	0
T280	581	0	0	0
T281	527	0	0	0
T282	451	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	14631	0	0
T7	10904	149	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	17	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	153	0	0
T32	0	367	0	0
T34	0	553	0	0
T35	0	29	0	0
T40	0	60	0	0
T45	12753	103	0	0
T139	0	199	0	0
T184	0	463	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	369	0	0
T7	10904	2	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	3	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	6	0	0
T32	0	6	0	0
T34	0	11	0	0
T35	0	1	0	0
T40	0	1	0	0
T45	12753	2	0	0
T139	0	7	0	0
T184	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8552088	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8553680	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	480	0	0
T7	10904	2	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	4	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T34	0	11	0	0
T35	0	1	0	0
T40	0	2	0	0
T45	12753	2	0	0
T139	0	7	0	0
T184	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	431	0	0
T7	10904	2	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	3	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	6	0	0
T32	0	6	0	0
T34	0	11	0	0
T35	0	1	0	0
T40	0	1	0	0
T45	12753	2	0	0
T139	0	7	0	0
T184	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	369	0	0
T7	10904	2	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	3	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	6	0	0
T32	0	6	0	0
T34	0	11	0	0
T35	0	1	0	0
T40	0	1	0	0
T45	12753	2	0	0
T139	0	7	0	0
T184	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	369	0	0
T7	10904	2	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	3	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	6	0	0
T32	0	6	0	0
T34	0	11	0	0
T35	0	1	0	0
T40	0	1	0	0
T45	12753	2	0	0
T139	0	7	0	0
T184	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	14234	0	0
T7	10904	147	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	14	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	147	0	0
T32	0	361	0	0
T34	0	542	0	0
T35	0	27	0	0
T40	0	58	0	0
T45	12753	99	0	0
T139	0	192	0	0
T184	0	450	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	339	0	0
T7	10904	2	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	3	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	6	0	0
T32	0	6	0	0
T34	0	11	0	0
T45	12753	0	0	0
T57	0	4	0	0
T92	0	1	0	0
T139	0	7	0	0
T184	0	13	0	0
T221	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T27
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T7,T45
1	1	Covered	T1,T14,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T27
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T35,T32

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T45,T33
0	1	Covered	T7,T45,T33
1	0	Covered	T283,T284

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T45,T33
1	-	Covered	T7,T45,T33

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T27
DetectSt	168	Covered	T1,T14,T27
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T45,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T27
DebounceSt->IdleSt	163	Covered	T100,T269,T87
DetectSt->IdleSt	186	Covered	T1,T14,T27
DetectSt->StableSt	191	Covered	T7,T45,T33
IdleSt->DebounceSt	148	Covered	T1,T14,T27
StableSt->IdleSt	206	Covered	T7,T45,T33

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T27
0	1	Covered	T1,T14,T27
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T27
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T27
IdleSt	0	-	-	-	-	-	-	Covered	T1,T14,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T100,T269,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T27
DetectSt	-	-	-	-	1	-	-	Covered	T1,T14,T27
DetectSt	-	-	-	-	0	1	-	Covered	T7,T45,T33
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T27
StableSt	-	-	-	-	-	-	1	Covered	T7,T45,T33
StableSt	-	-	-	-	-	-	0	Covered	T7,T45,T33
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	3227	0	0
CntIncr_A	9566120	109987	0	0
CntNoWrap_A	9566120	8931581	0	0
DetectStDropOut_A	9566120	334	0	0
DetectedOut_A	9566120	90440	0	0
DetectedPulseOut_A	9566120	1058	0	0
DisabledIdleSt_A	9566120	8460746	0	0
DisabledNoDetection_A	9566120	8462912	0	0
EnterDebounceSt_A	9566120	1626	0	0
EnterDetectSt_A	9566120	1602	0	0
EnterStableSt_A	9566120	1058	0	0
PulseIsPulse_A	9566120	1058	0	0
StayInStableSt	9566120	89277	0	0
gen_high_event_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	930	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	3227	0	0
T1	7156	52	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	46	0	0
T13	403	0	0	0
T14	4724	18	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	42	0	0
T32	0	20	0	0
T33	0	20	0	0
T35	0	26	0	0
T45	0	38	0	0
T61	0	30	0	0
T62	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	109987	0	0
T1	7156	1640	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	644	0	0
T13	403	0	0	0
T14	4724	375	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	1010	0	0
T32	0	593	0	0
T33	0	2860	0	0
T35	0	944	0	0
T45	0	1425	0	0
T61	0	840	0	0
T62	0	156	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8931581	0	0
T1	7156	6703	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4305	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	334	0	0
T1	7156	22	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T13	403	0	0	0
T14	4724	9	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	21	0	0
T32	0	4	0	0
T35	0	9	0	0
T92	0	13	0	0
T104	0	2	0	0
T105	0	13	0	0
T123	0	8	0	0
T271	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	90440	0	0
T7	10904	1733	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T33	0	2112	0	0
T45	12753	262	0	0
T61	0	231	0	0
T62	0	110	0	0
T88	0	1052	0	0
T89	0	1949	0	0
T93	0	1978	0	0
T270	0	74	0	0
T285	0	1432	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1058	0	0
T7	10904	23	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T33	0	10	0	0
T45	12753	19	0	0
T61	0	15	0	0
T62	0	3	0	0
T88	0	10	0	0
T89	0	24	0	0
T93	0	24	0	0
T270	0	2	0	0
T285	0	18	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8460746	0	0
T1	7156	3407	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	2014	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8462912	0	0
T1	7156	3407	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	2014	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1626	0	0
T1	7156	26	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	23	0	0
T13	403	0	0	0
T14	4724	9	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	21	0	0
T32	0	10	0	0
T33	0	10	0	0
T35	0	13	0	0
T45	0	19	0	0
T61	0	15	0	0
T62	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1602	0	0
T1	7156	26	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	23	0	0
T13	403	0	0	0
T14	4724	9	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	21	0	0
T32	0	10	0	0
T33	0	10	0	0
T35	0	13	0	0
T45	0	19	0	0
T61	0	15	0	0
T62	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1058	0	0
T7	10904	23	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T33	0	10	0	0
T45	12753	19	0	0
T61	0	15	0	0
T62	0	3	0	0
T88	0	10	0	0
T89	0	24	0	0
T93	0	24	0	0
T270	0	2	0	0
T285	0	18	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1058	0	0
T7	10904	23	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T33	0	10	0	0
T45	12753	19	0	0
T61	0	15	0	0
T62	0	3	0	0
T88	0	10	0	0
T89	0	24	0	0
T93	0	24	0	0
T270	0	2	0	0
T285	0	18	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	89277	0	0
T7	10904	1709	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T33	0	2099	0	0
T45	12753	243	0	0
T61	0	216	0	0
T62	0	107	0	0
T88	0	1042	0	0
T89	0	1925	0	0
T93	0	1952	0	0
T270	0	72	0	0
T285	0	1412	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	930	0	0
T7	10904	22	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	0	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T33	0	7	0	0
T45	12753	19	0	0
T61	0	15	0	0
T62	0	3	0	0
T88	0	10	0	0
T89	0	24	0	0
T93	0	22	0	0
T270	0	2	0	0
T285	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T27
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T10,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T7,T10,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T7,T10,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T45,T10
1	0	Covered	T1,T14,T15
1	1	Covered	T7,T10,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T31
0	1	Covered	T47,T57,T117
1	0	Covered	T87,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T31
0	1	Covered	T7,T10,T31
1	0	Covered	T88,T87,T50

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T10,T31
1	-	Covered	T7,T10,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T10,T31
DetectSt	168	Covered	T7,T10,T31
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T7,T10,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T31
DebounceSt->IdleSt	163	Covered	T40,T86,T221
DetectSt->IdleSt	186	Covered	T47,T57,T117
DetectSt->StableSt	191	Covered	T7,T10,T31
IdleSt->DebounceSt	148	Covered	T7,T10,T31
StableSt->IdleSt	206	Covered	T7,T10,T31

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T10,T31
0	1	Covered	T7,T10,T31
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T31
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T10,T31
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T40,T86,T221
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T10,T31
DetectSt	-	-	-	-	1	-	-	Covered	T47,T57,T117
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T31
DetectSt	-	-	-	-	0	0	-	Covered	T7,T10,T31
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T31
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T31
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	1011	0	0
CntIncr_A	9566120	57326	0	0
CntNoWrap_A	9566120	8933797	0	0
DetectStDropOut_A	9566120	43	0	0
DetectedOut_A	9566120	20885	0	0
DetectedPulseOut_A	9566120	437	0	0
DisabledIdleSt_A	9566120	8541693	0	0
DisabledNoDetection_A	9566120	8543290	0	0
EnterDebounceSt_A	9566120	529	0	0
EnterDetectSt_A	9566120	484	0	0
EnterStableSt_A	9566120	437	0	0
PulseIsPulse_A	9566120	437	0	0
StayInStableSt	9566120	20425	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	411	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1011	0	0
T7	10904	8	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	12	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	2	0	0
T33	0	6	0	0
T34	0	2	0	0
T40	0	3	0	0
T45	12753	0	0	0
T47	0	4	0	0
T86	0	15	0	0
T139	0	2	0	0
T184	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	57326	0	0
T7	10904	192	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	678	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	112	0	0
T33	0	906	0	0
T34	0	91	0	0
T40	0	200	0	0
T45	12753	0	0	0
T47	0	285	0	0
T86	0	1313	0	0
T139	0	137	0	0
T184	0	624	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8933797	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	43	0	0
T34	50331	0	0	0
T39	928	0	0	0
T47	13428	2	0	0
T57	0	1	0	0
T60	506	0	0	0
T61	9906	0	0	0
T62	10355	0	0	0
T74	0	1	0	0
T117	0	7	0	0
T118	0	2	0	0
T136	510	0	0	0
T139	25984	0	0	0
T157	445	0	0	0
T182	425	0	0	0
T286	0	11	0	0
T287	0	9	0	0
T288	0	4	0	0
T289	0	1	0	0
T290	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	20885	0	0
T7	10904	251	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	210	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	80	0	0
T33	0	138	0	0
T34	0	11	0	0
T40	0	70	0	0
T45	12753	0	0	0
T86	0	112	0	0
T88	0	320	0	0
T139	0	64	0	0
T184	0	593	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	437	0	0
T7	10904	4	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	6	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	1	0	0
T33	0	3	0	0
T34	0	1	0	0
T40	0	1	0	0
T45	12753	0	0	0
T86	0	7	0	0
T88	0	4	0	0
T139	0	1	0	0
T184	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8541693	0	0
T1	7156	6755	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8543290	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	529	0	0
T7	10904	4	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	6	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	1	0	0
T33	0	3	0	0
T34	0	1	0	0
T40	0	3	0	0
T45	12753	0	0	0
T47	0	2	0	0
T86	0	8	0	0
T139	0	1	0	0
T184	0	13	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	484	0	0
T7	10904	4	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	6	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	1	0	0
T33	0	3	0	0
T34	0	1	0	0
T40	0	1	0	0
T45	12753	0	0	0
T47	0	2	0	0
T86	0	7	0	0
T139	0	1	0	0
T184	0	13	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	437	0	0
T7	10904	4	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	6	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	1	0	0
T33	0	3	0	0
T34	0	1	0	0
T40	0	1	0	0
T45	12753	0	0	0
T86	0	7	0	0
T88	0	4	0	0
T139	0	1	0	0
T184	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	437	0	0
T7	10904	4	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	6	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	1	0	0
T33	0	3	0	0
T34	0	1	0	0
T40	0	1	0	0
T45	12753	0	0	0
T86	0	7	0	0
T88	0	4	0	0
T139	0	1	0	0
T184	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	20425	0	0
T7	10904	247	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	204	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	79	0	0
T33	0	135	0	0
T34	0	10	0	0
T40	0	68	0	0
T45	12753	0	0	0
T86	0	105	0	0
T88	0	316	0	0
T139	0	63	0	0
T184	0	580	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	411	0	0
T7	10904	4	0	0
T8	483	0	0	0
T9	524	0	0	0
T10	18578	6	0	0
T20	492	0	0	0
T21	489	0	0	0
T22	493	0	0	0
T23	523	0	0	0
T26	764	0	0	0
T31	0	1	0	0
T33	0	3	0	0
T34	0	1	0	0
T45	12753	0	0	0
T86	0	7	0	0
T88	0	3	0	0
T89	0	2	0	0
T139	0	1	0	0
T184	0	13	0	0