Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T27
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T27

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T27

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T14,T27

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T27
1	0	Covered	T7,T45,T35
1	1	Covered	T1,T14,T27

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T14,T27
0	1	Covered	T14,T27,T32
1	0	Covered	T32,T61,T88

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T45
0	1	Covered	T1,T7,T45
1	0	Covered	T93

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T45
1	-	Covered	T1,T7,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T14,T27
DetectSt	168	Covered	T1,T14,T27
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T7,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T14,T27
DebounceSt->IdleSt	163	Covered	T100,T269,T87
DetectSt->IdleSt	186	Covered	T14,T27,T32
DetectSt->StableSt	191	Covered	T1,T7,T45
IdleSt->DebounceSt	148	Covered	T1,T14,T27
StableSt->IdleSt	206	Covered	T1,T7,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T14,T27
0	1	Covered	T1,T14,T27
0	0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T14,T27
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T14,T27
IdleSt	0	-	-	-	-	-	-	Covered	T1,T14,T27
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T14,T27
DebounceSt	-	0	1	0	-	-	-	Covered	T100,T269,T87
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T14,T27
DetectSt	-	-	-	-	1	-	-	Covered	T14,T27,T32
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T45
DetectSt	-	-	-	-	0	0	-	Covered	T1,T14,T27
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T45
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T45
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	3039	0	0
CntIncr_A	9566120	114805	0	0
CntNoWrap_A	9566120	8931769	0	0
DetectStDropOut_A	9566120	326	0	0
DetectedOut_A	9566120	75846	0	0
DetectedPulseOut_A	9566120	923	0	0
DisabledIdleSt_A	9566120	8467198	0	0
DisabledNoDetection_A	9566120	8469355	0	0
EnterDebounceSt_A	9566120	1532	0	0
EnterDetectSt_A	9566120	1507	0	0
EnterStableSt_A	9566120	923	0	0
PulseIsPulse_A	9566120	923	0	0
StayInStableSt	9566120	74807	0	0
gen_high_event_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	806	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	3039	0	0
T1	7156	24	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	22	0	0
T13	403	0	0	0
T14	4724	44	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	42	0	0
T32	0	22	0	0
T33	0	52	0	0
T35	0	18	0	0
T45	0	8	0	0
T61	0	32	0	0
T62	0	66	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	114805	0	0
T1	7156	672	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	462	0	0
T13	403	0	0	0
T14	4724	923	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	1010	0	0
T32	0	647	0	0
T33	0	7774	0	0
T35	0	522	0	0
T45	0	340	0	0
T61	0	1117	0	0
T62	0	2013	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8931769	0	0
T1	7156	6731	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4279	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	326	0	0
T2	853	0	0	0
T3	5844	0	0	0
T6	1136	0	0	0
T7	10904	0	0	0
T14	4724	22	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T24	522	0	0	0
T25	41158	0	0	0
T27	5021	21	0	0
T32	0	6	0	0
T88	0	18	0	0
T89	0	2	0	0
T105	0	25	0	0
T123	0	3	0	0
T271	0	7	0	0
T291	0	13	0	0
T292	0	6	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	75846	0	0
T1	7156	1471	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	892	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T33	0	4417	0	0
T35	0	1155	0	0
T45	0	153	0	0
T62	0	2206	0	0
T93	0	1	0	0
T100	0	10	0	0
T270	0	3079	0	0
T285	0	2749	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	923	0	0
T1	7156	12	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	11	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T33	0	26	0	0
T35	0	9	0	0
T45	0	4	0	0
T62	0	33	0	0
T93	0	1	0	0
T100	0	1	0	0
T270	0	27	0	0
T285	0	32	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8467198	0	0
T1	7156	2015	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	2014	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8469355	0	0
T1	7156	2015	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	2014	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1532	0	0
T1	7156	12	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	11	0	0
T13	403	0	0	0
T14	4724	22	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	21	0	0
T32	0	11	0	0
T33	0	26	0	0
T35	0	9	0	0
T45	0	4	0	0
T61	0	16	0	0
T62	0	33	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	1507	0	0
T1	7156	12	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	11	0	0
T13	403	0	0	0
T14	4724	22	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T27	0	21	0	0
T32	0	11	0	0
T33	0	26	0	0
T35	0	9	0	0
T45	0	4	0	0
T61	0	16	0	0
T62	0	33	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	923	0	0
T1	7156	12	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	11	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T33	0	26	0	0
T35	0	9	0	0
T45	0	4	0	0
T62	0	33	0	0
T93	0	1	0	0
T100	0	1	0	0
T270	0	27	0	0
T285	0	32	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	923	0	0
T1	7156	12	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	11	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T33	0	26	0	0
T35	0	9	0	0
T45	0	4	0	0
T62	0	33	0	0
T93	0	1	0	0
T100	0	1	0	0
T270	0	27	0	0
T285	0	32	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	74807	0	0
T1	7156	1459	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	881	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T33	0	4384	0	0
T35	0	1143	0	0
T45	0	148	0	0
T62	0	2172	0	0
T100	0	9	0	0
T270	0	3047	0	0
T285	0	2713	0	0
T293	0	322	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	806	0	0
T1	7156	12	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	11	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T33	0	19	0	0
T35	0	6	0	0
T45	0	3	0	0
T62	0	32	0	0
T100	0	1	0	0
T270	0	22	0	0
T285	0	28	0	0
T293	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T14,T27
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T14,T27
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T7,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T1,T4,T5	VC_COV_UNR
1	Covered	T1,T7,T45

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T7,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T45
1	0	Covered	T1,T14,T15
1	1	Covered	T1,T7,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T45
0	1	Covered	T10,T40,T184
1	0	Covered	T87,T50

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T45
0	1	Covered	T1,T7,T31
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T45
1	-	Covered	T1,T7,T31

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T45
DetectSt	168	Covered	T1,T7,T45
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T7,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T45
DebounceSt->IdleSt	163	Covered	T1,T10,T35
DetectSt->IdleSt	186	Covered	T10,T40,T184
DetectSt->StableSt	191	Covered	T1,T7,T45
IdleSt->DebounceSt	148	Covered	T1,T7,T45
StableSt->IdleSt	206	Covered	T1,T7,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T7,T45
0	1	Covered	T1,T7,T45
0	0	Excluded	T1,T4,T5	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T45
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T45
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T87,T50
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T10,T35
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T45
DetectSt	-	-	-	-	1	-	-	Covered	T10,T40,T184
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T45
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T45
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T31
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	9566120	941	0	0
CntIncr_A	9566120	53560	0	0
CntNoWrap_A	9566120	8933867	0	0
DetectStDropOut_A	9566120	63	0	0
DetectedOut_A	9566120	15924	0	0
DetectedPulseOut_A	9566120	377	0	0
DisabledIdleSt_A	9566120	8557083	0	0
DisabledNoDetection_A	9566120	8558681	0	0
EnterDebounceSt_A	9566120	497	0	0
EnterDetectSt_A	9566120	444	0	0
EnterStableSt_A	9566120	377	0	0
PulseIsPulse_A	9566120	377	0	0
StayInStableSt	9566120	15521	0	0
gen_high_level_sva.HighLevelEvent_A	9566120	8937170	0	0
gen_not_sticky_sva.StableStDropOut_A	9566120	346	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	941	0	0
T1	7156	5	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	10	0	0
T10	0	13	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T31	0	8	0	0
T33	0	14	0	0
T34	0	22	0	0
T35	0	7	0	0
T40	0	2	0	0
T45	0	2	0	0
T62	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	53560	0	0
T1	7156	143	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	185	0	0
T10	0	949	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T31	0	584	0	0
T33	0	2114	0	0
T34	0	682	0	0
T35	0	272	0	0
T40	0	160	0	0
T45	0	70	0	0
T62	0	34	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8933867	0	0
T1	7156	6750	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	63	0	0
T10	18578	6	0	0
T11	14742	0	0	0
T12	591	0	0	0
T26	764	0	0	0
T31	31828	0	0	0
T35	15717	0	0	0
T40	16284	1	0	0
T46	640	0	0	0
T55	494	0	0	0
T79	402	0	0	0
T117	0	1	0	0
T118	0	1	0	0
T184	0	1	0	0
T221	0	2	0	0
T275	0	2	0	0
T286	0	10	0	0
T294	0	1	0	0
T295	0	12	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	15924	0	0
T1	7156	158	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	370	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T31	0	188	0	0
T33	0	324	0	0
T34	0	454	0	0
T35	0	92	0	0
T45	0	67	0	0
T62	0	80	0	0
T86	0	52	0	0
T139	0	75	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	377	0	0
T1	7156	2	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	5	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T31	0	4	0	0
T33	0	7	0	0
T34	0	11	0	0
T35	0	3	0	0
T45	0	1	0	0
T62	0	1	0	0
T86	0	2	0	0
T139	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8557083	0	0
T1	7156	5284	0	0
T2	853	452	0	0
T3	5844	1160	0	0
T4	522	121	0	0
T5	402	1	0	0
T6	1136	735	0	0
T13	403	2	0	0
T14	4724	4323	0	0
T15	2261	257	0	0
T16	1065	664	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8558681	0	0
T1	7156	5285	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	497	0	0
T1	7156	3	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	5	0	0
T10	0	7	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T31	0	4	0	0
T33	0	7	0	0
T34	0	11	0	0
T35	0	4	0	0
T40	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	444	0	0
T1	7156	2	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	5	0	0
T10	0	6	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T31	0	4	0	0
T33	0	7	0	0
T34	0	11	0	0
T35	0	3	0	0
T40	0	1	0	0
T45	0	1	0	0
T62	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	377	0	0
T1	7156	2	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	5	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T31	0	4	0	0
T33	0	7	0	0
T34	0	11	0	0
T35	0	3	0	0
T45	0	1	0	0
T62	0	1	0	0
T86	0	2	0	0
T139	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	377	0	0
T1	7156	2	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	5	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T31	0	4	0	0
T33	0	7	0	0
T34	0	11	0	0
T35	0	3	0	0
T45	0	1	0	0
T62	0	1	0	0
T86	0	2	0	0
T139	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	15521	0	0
T1	7156	156	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	365	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T31	0	184	0	0
T33	0	314	0	0
T34	0	443	0	0
T35	0	89	0	0
T45	0	65	0	0
T62	0	78	0	0
T86	0	50	0	0
T139	0	74	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	8937170	0	0
T1	7156	6756	0	0
T2	853	453	0	0
T3	5844	1173	0	0
T4	522	122	0	0
T5	402	2	0	0
T6	1136	736	0	0
T13	403	3	0	0
T14	4724	4324	0	0
T15	2261	261	0	0
T16	1065	665	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	9566120	346	0	0
T1	7156	2	0	0
T2	853	0	0	0
T3	5844	0	0	0
T4	522	0	0	0
T5	402	0	0	0
T6	1136	0	0	0
T7	0	5	0	0
T13	403	0	0	0
T14	4724	0	0	0
T15	2261	0	0	0
T16	1065	0	0	0
T31	0	4	0	0
T33	0	4	0	0
T34	0	11	0	0
T35	0	3	0	0
T57	0	14	0	0
T86	0	2	0	0
T139	0	1	0	0
T270	0	2	0	0