Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1291646528	8806	0	0
auto_block_debounce_ctl_rd_A	1291646528	1680	0	0
auto_block_out_ctl_rd_A	1291646528	2411	0	0
com_det_ctl_0_rd_A	1291646528	3811	0	0
com_det_ctl_1_rd_A	1291646528	3745	0	0
com_det_ctl_2_rd_A	1291646528	3792	0	0
com_det_ctl_3_rd_A	1291646528	3941	0	0
com_out_ctl_0_rd_A	1291646528	4366	0	0
com_out_ctl_1_rd_A	1291646528	4458	0	0
com_out_ctl_2_rd_A	1291646528	4398	0	0
com_out_ctl_3_rd_A	1291646528	4297	0	0
com_pre_det_ctl_0_rd_A	1291646528	1103	0	0
com_pre_det_ctl_1_rd_A	1291646528	1211	0	0
com_pre_det_ctl_2_rd_A	1291646528	1138	0	0
com_pre_det_ctl_3_rd_A	1291646528	1183	0	0
com_pre_sel_ctl_0_rd_A	1291646528	4612	0	0
com_pre_sel_ctl_1_rd_A	1291646528	4749	0	0
com_pre_sel_ctl_2_rd_A	1291646528	4761	0	0
com_pre_sel_ctl_3_rd_A	1291646528	4542	0	0
com_sel_ctl_0_rd_A	1291646528	4938	0	0
com_sel_ctl_1_rd_A	1291646528	4732	0	0
com_sel_ctl_2_rd_A	1291646528	4859	0	0
com_sel_ctl_3_rd_A	1291646528	4659	0	0
ec_rst_ctl_rd_A	1291646528	2337	0	0
intr_enable_rd_A	1291646528	2029	0	0
key_intr_ctl_rd_A	1291646528	4044	0	0
key_intr_debounce_ctl_rd_A	1291646528	1223	0	0
key_invert_ctl_rd_A	1291646528	5021	0	0
pin_allowed_ctl_rd_A	1291646528	7070	0	0
pin_out_ctl_rd_A	1291646528	4815	0	0
pin_out_value_rd_A	1291646528	5396	0	0
regwen_rd_A	1291646528	1449	0	0
ulp_ac_debounce_ctl_rd_A	1291646528	1342	0	0
ulp_ctl_rd_A	1291646528	1355	0	0
ulp_lid_debounce_ctl_rd_A	1291646528	1281	0	0
ulp_pwrb_debounce_ctl_rd_A	1291646528	1449	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	8806	0	0
T3	134329	4	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T11	0	15	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T40	0	16	0	0
T42	0	10	0	0
T47	0	10	0	0
T49	0	24	0	0
T72	0	4	0	0
T109	0	26	0	0
T133	0	4	0	0
T294	0	8	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	1680	0	0
T3	134329	8	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	12	0	0
T27	627770	0	0	0
T48	0	14	0	0
T102	0	9	0	0
T107	0	10	0	0
T120	0	18	0	0
T137	0	10	0	0
T163	0	36	0	0
T306	0	10	0	0
T307	0	13	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	2411	0	0
T3	134329	22	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	14	0	0
T27	627770	0	0	0
T48	0	10	0	0
T102	0	6	0	0
T107	0	2	0	0
T120	0	17	0	0
T137	0	11	0	0
T163	0	37	0	0
T306	0	6	0	0
T307	0	1	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	3811	0	0
T3	134329	6	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	59	0	0
T88	0	28	0	0
T93	0	44	0	0
T179	0	40	0	0
T266	0	86	0	0
T285	0	42	0	0
T308	0	42	0	0
T309	0	60	0	0
T310	0	49	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	3745	0	0
T3	134329	2	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	13	0	0
T88	0	33	0	0
T93	0	53	0	0
T179	0	58	0	0
T266	0	81	0	0
T285	0	54	0	0
T308	0	37	0	0
T309	0	87	0	0
T310	0	59	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	3792	0	0
T32	985653	33	0	0
T39	192137	0	0	0
T47	659860	0	0	0
T51	247753	0	0	0
T61	247663	0	0	0
T62	129447	0	0	0
T88	0	49	0	0
T93	0	39	0	0
T106	0	66	0	0
T154	219366	0	0	0
T155	420318	0	0	0
T156	99185	0	0	0
T157	44626	0	0	0
T179	0	43	0	0
T266	0	66	0	0
T285	0	43	0	0
T308	0	23	0	0
T309	0	49	0	0
T310	0	75	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	3941	0	0
T32	985653	36	0	0
T39	192137	0	0	0
T47	659860	0	0	0
T51	247753	0	0	0
T61	247663	0	0	0
T62	129447	0	0	0
T88	0	38	0	0
T93	0	53	0	0
T106	0	61	0	0
T154	219366	0	0	0
T155	420318	0	0	0
T156	99185	0	0	0
T157	44626	0	0	0
T179	0	19	0	0
T266	0	81	0	0
T285	0	46	0	0
T308	0	72	0	0
T309	0	87	0	0
T310	0	58	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4366	0	0
T3	134329	7	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	17	0	0
T88	0	53	0	0
T93	0	36	0	0
T179	0	35	0	0
T266	0	55	0	0
T285	0	49	0	0
T308	0	19	0	0
T309	0	69	0	0
T310	0	64	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4458	0	0
T3	134329	8	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	49	0	0
T88	0	47	0	0
T93	0	32	0	0
T179	0	60	0	0
T266	0	48	0	0
T285	0	57	0	0
T308	0	25	0	0
T309	0	56	0	0
T310	0	53	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4398	0	0
T3	134329	13	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	29	0	0
T88	0	27	0	0
T93	0	41	0	0
T179	0	48	0	0
T266	0	68	0	0
T285	0	44	0	0
T308	0	73	0	0
T309	0	73	0	0
T310	0	62	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4297	0	0
T3	134329	6	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	20	0	0
T88	0	36	0	0
T93	0	47	0	0
T179	0	48	0	0
T266	0	63	0	0
T285	0	66	0	0
T308	0	53	0	0
T309	0	59	0	0
T310	0	63	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	1103	0	0
T42	360924	0	0	0
T90	76976	0	0	0
T117	0	19	0	0
T133	0	2	0	0
T163	337728	14	0	0
T198	0	6	0	0
T202	170006	0	0	0
T203	50677	0	0	0
T204	228317	0	0	0
T205	120742	0	0	0
T206	51582	0	0	0
T207	240809	0	0	0
T208	201407	0	0	0
T218	0	23	0	0
T277	0	7	0	0
T311	0	6	0	0
T312	0	24	0	0
T313	0	11	0	0
T314	0	7	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	1211	0	0
T3	134329	6	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T117	0	22	0	0
T133	0	21	0	0
T163	0	9	0	0
T198	0	5	0	0
T277	0	20	0	0
T311	0	3	0	0
T312	0	24	0	0
T313	0	21	0	0
T314	0	10	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	1138	0	0
T3	134329	7	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T117	0	4	0	0
T133	0	14	0	0
T163	0	15	0	0
T198	0	3	0	0
T277	0	2	0	0
T311	0	22	0	0
T312	0	15	0	0
T313	0	8	0	0
T314	0	11	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	1183	0	0
T3	134329	1	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T117	0	1	0	0
T133	0	17	0	0
T163	0	12	0	0
T198	0	1	0	0
T277	0	10	0	0
T311	0	5	0	0
T312	0	15	0	0
T313	0	14	0	0
T314	0	8	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4612	0	0
T3	134329	12	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	33	0	0
T88	0	36	0	0
T93	0	50	0	0
T179	0	57	0	0
T266	0	60	0	0
T285	0	57	0	0
T308	0	32	0	0
T309	0	62	0	0
T310	0	71	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4749	0	0
T3	134329	3	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	43	0	0
T88	0	52	0	0
T93	0	50	0	0
T179	0	27	0	0
T266	0	69	0	0
T285	0	33	0	0
T308	0	38	0	0
T309	0	73	0	0
T310	0	71	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4761	0	0
T3	134329	10	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	56	0	0
T88	0	32	0	0
T93	0	45	0	0
T179	0	37	0	0
T266	0	66	0	0
T285	0	71	0	0
T308	0	37	0	0
T309	0	54	0	0
T310	0	71	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4542	0	0
T3	134329	6	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	39	0	0
T88	0	56	0	0
T93	0	46	0	0
T179	0	38	0	0
T266	0	59	0	0
T285	0	59	0	0
T308	0	62	0	0
T309	0	91	0	0
T310	0	63	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4938	0	0
T3	134329	5	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	25	0	0
T88	0	51	0	0
T93	0	55	0	0
T179	0	44	0	0
T266	0	74	0	0
T285	0	59	0	0
T308	0	57	0	0
T309	0	72	0	0
T310	0	49	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4732	0	0
T3	134329	1	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	78	0	0
T88	0	22	0	0
T93	0	53	0	0
T179	0	29	0	0
T266	0	78	0	0
T285	0	30	0	0
T308	0	43	0	0
T309	0	74	0	0
T310	0	59	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4859	0	0
T3	134329	13	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	46	0	0
T88	0	59	0	0
T93	0	52	0	0
T179	0	34	0	0
T266	0	47	0	0
T285	0	34	0	0
T308	0	29	0	0
T309	0	62	0	0
T310	0	53	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4659	0	0
T3	134329	4	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T32	0	49	0	0
T88	0	39	0	0
T93	0	40	0	0
T179	0	42	0	0
T266	0	75	0	0
T285	0	58	0	0
T308	0	48	0	0
T309	0	70	0	0
T310	0	67	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	2337	0	0
T2	115031	0	0	0
T3	134329	7	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T15	110827	1	0	0
T16	133106	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	3	0	0
T32	0	12	0	0
T88	0	4	0	0
T93	0	13	0	0
T155	0	3	0	0
T219	0	6	0	0
T308	0	31	0	0
T309	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	2029	0	0
T2	115031	0	0	0
T3	134329	38	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T15	110827	7	0	0
T16	133106	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T48	0	17	0	0
T117	0	29	0	0
T120	0	28	0	0
T124	0	22	0	0
T133	0	35	0	0
T163	0	62	0	0
T311	0	12	0	0
T312	0	41	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4044	0	0
T3	134329	24	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T41	0	6	0	0
T95	0	3	0	0
T133	0	19	0	0
T163	0	24	0	0
T179	0	7	0	0
T181	0	3	0	0
T187	0	3	0	0
T213	0	2	0	0
T311	0	2	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	1223	0	0
T3	134329	11	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T117	0	19	0	0
T133	0	14	0	0
T163	0	26	0	0
T198	0	5	0	0
T277	0	16	0	0
T311	0	6	0	0
T312	0	23	0	0
T313	0	22	0	0
T314	0	9	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	5021	0	0
T9	53207	0	0	0
T10	928937	0	0	0
T11	580123	0	0	0
T12	107515	0	0	0
T20	236324	48	0	0
T21	244547	0	0	0
T22	244564	0	0	0
T26	95555	0	0	0
T31	159139	0	0	0
T45	612173	0	0	0
T56	0	60	0	0
T117	0	120	0	0
T133	0	7	0	0
T163	0	81	0	0
T311	0	47	0	0
T312	0	22	0	0
T313	0	25	0	0
T315	0	61	0	0
T316	0	46	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	7070	0	0
T3	134329	92	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T48	0	77	0	0
T60	0	38	0	0
T163	0	22	0	0
T207	0	61	0	0
T317	0	34	0	0
T318	0	73	0	0
T319	0	59	0	0
T320	0	21	0	0
T321	0	70	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	4815	0	0
T3	134329	81	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T48	0	58	0	0
T60	0	41	0	0
T163	0	22	0	0
T207	0	59	0	0
T317	0	50	0	0
T318	0	66	0	0
T319	0	67	0	0
T320	0	47	0	0
T321	0	64	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	5396	0	0
T3	134329	34	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T48	0	81	0	0
T60	0	62	0	0
T163	0	8	0	0
T207	0	75	0	0
T317	0	35	0	0
T318	0	67	0	0
T319	0	82	0	0
T320	0	39	0	0
T321	0	74	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	1449	0	0
T3	134329	11	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T117	0	7	0	0
T133	0	15	0	0
T163	0	18	0	0
T198	0	3	0	0
T218	0	19	0	0
T311	0	10	0	0
T312	0	10	0	0
T313	0	19	0	0
T314	0	11	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	1342	0	0
T3	134329	9	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T53	0	12	0	0
T63	0	9	0	0
T64	0	15	0	0
T98	0	1	0	0
T124	0	11	0	0
T163	0	10	0	0
T261	0	1	0	0
T322	0	7	0	0
T323	0	7	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	1355	0	0
T3	134329	8	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T12	0	5	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T53	0	13	0	0
T63	0	5	0	0
T64	0	3	0	0
T124	0	3	0	0
T163	0	2	0	0
T261	0	9	0	0
T322	0	8	0	0
T323	0	7	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	1281	0	0
T3	134329	10	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T53	0	16	0	0
T63	0	8	0	0
T64	0	10	0	0
T98	0	7	0	0
T124	0	8	0	0
T133	0	12	0	0
T163	0	22	0	0
T261	0	14	0	0
T322	0	9	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1291646528	1449	0	0
T3	134329	7	0	0
T6	88485	0	0	0
T7	103587	0	0	0
T8	231892	0	0	0
T20	236324	0	0	0
T21	244547	0	0	0
T23	128252	0	0	0
T24	130741	0	0	0
T25	226371	0	0	0
T27	627770	0	0	0
T53	0	5	0	0
T63	0	6	0	0
T64	0	11	0	0
T98	0	1	0	0
T124	0	5	0	0
T163	0	27	0	0
T261	0	5	0	0
T322	0	12	0	0
T323	0	1	0	0