Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
92.68	92.68	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	92.68	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.68	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	6	56	90.32

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	6	25	80.65	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2016

1

T1

3

T12

10

T4

1

auto[1]

654

1

T1

1

T12

6

T4

5

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2062

1

T1

4

T12

10

T4

5

auto[1]

608

1

T12

6

T4

1

T44

2

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2088

1

T1

3

T12

14

T4

5

auto[1]

582

1

T1

1

T12

2

T4

1

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1900

1

T1

4

T12

10

T4

1

auto[1]

770

1

T12

6

T4

5

T14

2

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2465

1

T1

4

T12

12

T4

6

auto[1]

205

1

T12

4

T8

2

T42

2

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2506

1

T1

3

T12

12

T4

6

auto[1]

164

1

T1

1

T12

4

T8

2

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2385

1

T1

4

T12

10

T4

6

auto[1]

285

1

T12

6

T14

2

T8

2

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2446

1

T1

3

T12

16

T4

6

auto[1]

224

1

T1

1

T8

4

T42

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2362

1

T1

3

T12

14

T4

6

auto[1]

308

1

T1

1

T12

2

T29

6

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2151

1

T1

4

T12

16

T4

5

auto[1]

519

1

T4

1

T8

2

T9

3

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	6	25	80.65	6
Automatically Generated Cross Bins	31	6	25	80.65	6
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	*	[auto[1]]	[auto[1]]	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

801

1

T4

6

T9

4

T44

2

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

75

1

T42

2

T154

6

T155

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

107

1

T155

6

T337

3

T349

3

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

24

1

T246

4

T350

1

T351

2

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T42

2

T108

2

T341

5

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

20

1

T131

16

T346

1

T352

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

45

1

T153

1

T168

3

T310

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

76

1

T12

4

T108

2

T246

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

4

1

T12

2

T353

2

-

-

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

57

1

T29

6

T246

10

T247

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

3

1

T246

3

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T354

10

T341

5

T127

7

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T8

2

T347

2

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

16

1

T355

4

T356

1

T357

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

24

1

T12

2

T108

2

T358

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

39

1

T29

8

T337

1

T359

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

9

1

T360

4

T347

2

T361

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

5

1

T12

2

T362

1

T356

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

2

1

T8

2

-

-

-

-

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

5

1

T337

1

T363

4

-

-

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

5

1

T1

1

T364

2

T348

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

37

1

T349

3

T362

10

T365

18

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

8

1

T29

5

T311

2

T356

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

3

1

T155

1

T349

2

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

9

1

T362

6

T366

3

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

126

1

T8

2

T29

6

T87

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

52

1

T8

2

T9

2

T268

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

55

1

T354

10

T367

1

T368

10

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

153

1

T29

8

T86

7

T248

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

67

1

T12

2

T4

5

T108

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

46

1

T29

5

T248

6

T333

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

45

1

T336

3

T269

1

T270

5

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

92

1

T12

2

T89

13

T337

4

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

37

1

T1

1

T93

4

T98

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

45

1

T42

4

T87

6

T34

7

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

20

1

T9

1

T37

1

T74

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

77

1

T108

2

T30

3

T336

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

47

1

T9

1

T174

2

T93

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

31

1

T88

2

T34

3

T90

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

5

1

T268

1

T99

1

T369

3

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

79

1

T12

2

T295

9

T154

6

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

77

1

T30

2

T252

7

T174

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

34

1

T28

7

T295

2

T189

1

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

19

1

T338

1

T335

4

T339

4

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

108

1

T27

9

T252

4

T206

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T12

4

T30

1

T155

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

33

1

T44

2

T28

5

T89

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

12

1

T27

2

T295

2

T95

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

78

1

T246

4

T168

3

T269

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

20

1

T88

4

T34

3

T252

5

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

32

1

T4

1

T30

4

T248

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

14

1

T108

2

T98

1

T127

8

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

13

1

T88

1

T252

3

T296

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

5

1

T28

1

T338

1

T340

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

18

1

T27

3

T296

1

T370

5

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T371

2

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded