Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

936

1

T9

8

T22

10

T53

11

auto[1]

969

1

T9

12

T22

10

T53

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

441

1

T9

6

T22

5

T53

3

from_0to1

444

1

T9

6

T22

5

T53

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

951

1

T9

12

T22

11

T53

10

auto[1]

954

1

T9

8

T22

9

T53

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

968

1

T9

12

T22

10

T53

10

auto[1]

937

1

T9

8

T22

10

T53

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T22

2

T53

1

T43

2

auto[0]

from_1to0

auto[0]

auto[1]

56

1

T9

1

T55

2

T43

1

auto[0]

from_1to0

auto[1]

auto[0]

43

1

T9

2

T22

1

T55

1

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T22

1

T53

1

T67

2

auto[0]

from_0to1

auto[0]

auto[0]

50

1

T9

2

T67

2

T46

1

auto[0]

from_0to1

auto[0]

auto[1]

58

1

T22

1

T53

2

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T9

1

T53

1

T55

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T22

1

T43

1

T46

1

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T9

1

T46

1

T229

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T9

2

T55

1

T46

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T22

1

T53

1

T55

1

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T43

1

T67

2

T229

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T9

2

T55

1

T229

1

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T22

1

T55

2

T43

3

auto[1]

from_0to1

auto[1]

auto[0]

55

1

T22

1

T55

1

T67

1

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T9

1

T22

1

T229

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

927

1

T9

9

T22

9

T53

7

auto[1]

978

1

T9

11

T22

11

T53

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

455

1

T9

5

T22

2

T53

6

from_0to1

452

1

T9

6

T22

2

T53

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

976

1

T9

6

T22

10

T53

12

auto[1]

929

1

T9

14

T22

10

T53

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

965

1

T9

12

T22

11

T53

11

auto[1]

940

1

T9

8

T22

9

T53

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T9

1

T53

1

T229

2

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T43

1

T46

1

T262

1

auto[0]

from_1to0

auto[1]

auto[0]

59

1

T55

1

T46

1

T229

2

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T9

1

T53

1

T55

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T53

1

T46

3

T229

1

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T229

1

T296

1

T303

1

auto[0]

from_0to1

auto[1]

auto[0]

47

1

T9

1

T43

1

T67

2

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T9

1

T53

1

T43

1

auto[1]

from_1to0

auto[0]

auto[0]

46

1

T43

2

T262

1

T302

1

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T22

1

T53

2

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T9

3

T22

1

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T53

1

T43

1

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

68

1

T9

1

T22

1

T53

2

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T53

1

T55

2

T43

1

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T9

3

T55

2

T229

1

auto[1]

from_0to1

auto[1]

auto[1]

46

1

T22

1

T67

1

T46

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

952

1

T9

9

T22

12

T53

5

auto[1]

953

1

T9

11

T22

8

T53

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

444

1

T9

4

T22

7

T53

5

from_0to1

444

1

T9

5

T22

7

T53

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

927

1

T9

9

T22

7

T53

10

auto[1]

978

1

T9

11

T22

13

T53

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

941

1

T9

11

T22

11

T53

10

auto[1]

964

1

T9

9

T22

9

T53

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T22

2

T229

1

T262

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T9

1

T22

1

T53

1

auto[0]

from_1to0

auto[1]

auto[0]

54

1

T22

1

T53

1

T43

1

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T229

1

T34

1

T111

2

auto[0]

from_0to1

auto[0]

auto[0]

39

1

T9

1

T22

1

T55

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T9

1

T22

2

T55

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T9

2

T22

2

T46

2

auto[0]

from_0to1

auto[1]

auto[1]

62

1

T22

1

T262

2

T88

2

auto[1]

from_1to0

auto[0]

auto[0]

53

1

T9

1

T55

2

T43

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T53

2

T55

2

T43

1

auto[1]

from_1to0

auto[1]

auto[0]

56

1

T9

1

T22

3

T53

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T9

1

T46

2

T88

2

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T53

1

T43

1

T262

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T9

1

T53

1

T55

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T53

1

T55

2

T43

1

auto[1]

from_0to1

auto[1]

auto[1]

52

1

T22

1

T53

1

T229

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

990

1

T9

11

T22

12

T53

13

auto[1]

915

1

T9

9

T22

8

T53

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

447

1

T9

6

T22

5

T53

4

from_0to1

447

1

T9

6

T22

5

T53

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

937

1

T9

8

T22

12

T53

11

auto[1]

968

1

T9

12

T22

8

T53

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

970

1

T9

9

T22

9

T53

14

auto[1]

935

1

T9

11

T22

11

T53

6

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

55

1

T53

2

T67

1

T88

2

auto[0]

from_1to0

auto[0]

auto[1]

52

1

T9

1

T22

1

T53

1

auto[0]

from_1to0

auto[1]

auto[0]

69

1

T9

2

T22

1

T43

1

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T9

1

T55

1

T46

1

auto[0]

from_0to1

auto[0]

auto[0]

54

1

T22

1

T53

1

T46

2

auto[0]

from_0to1

auto[0]

auto[1]

52

1

T9

1

T22

2

T43

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T53

2

T55

1

T46

1

auto[0]

from_0to1

auto[1]

auto[1]

49

1

T9

1

T22

1

T55

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T9

1

T88

1

T303

1

auto[1]

from_1to0

auto[0]

auto[1]

44

1

T9

1

T22

1

T55

1

auto[1]

from_1to0

auto[1]

auto[0]

57

1

T22

1

T55

1

T43

1

auto[1]

from_1to0

auto[1]

auto[1]

46

1

T22

1

T53

1

T43

1

auto[1]

from_0to1

auto[0]

auto[0]

58

1

T53

1

T55

2

T43

2

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T9

1

T229

1

T88

1

auto[1]

from_0to1

auto[1]

auto[0]

59

1

T67

1

T46

1

T302

2

auto[1]

from_0to1

auto[1]

auto[1]

51

1

T9

3

T22

1

T67

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

931

1

T9

11

T22

11

T53

10

auto[1]

974

1

T9

9

T22

9

T53

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

452

1

T9

5

T22

5

T53

5

from_0to1

451

1

T9

4

T22

5

T53

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

931

1

T9

7

T22

9

T53

11

auto[1]

974

1

T9

13

T22

11

T53

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

959

1

T9

14

T22

9

T53

8

auto[1]

946

1

T9

6

T22

11

T53

12

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

53

1

T43

1

T229

1

T262

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T9

1

T22

1

T53

3

auto[0]

from_1to0

auto[1]

auto[0]

50

1

T9

1

T22

2

T55

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T9

1

T55

2

T43

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T229

1

T262

1

T88

1

auto[0]

from_0to1

auto[0]

auto[1]

63

1

T22

3

T53

1

T46

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T9

2

T53

1

T67

1

auto[0]

from_0to1

auto[1]

auto[1]

50

1

T22

1

T53

1

T67

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T9

1

T53

1

T55

1

auto[1]

from_1to0

auto[0]

auto[1]

45

1

T55

1

T67

1

T46

2

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T22

1

T43

2

T67

2

auto[1]

from_1to0

auto[1]

auto[1]

60

1

T9

1

T22

1

T53

1

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T9

1

T53

1

T55

1

auto[1]

from_0to1

auto[0]

auto[1]

53

1

T53

1

T55

1

T43

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T9

1

T55

4

T43

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T22

1

T43

1

T46

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

920

1

T9

11

T22

13

T53

12

auto[1]

985

1

T9

9

T22

7

T53

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

454

1

T9

5

T22

5

T53

4

from_0to1

450

1

T9

5

T22

5

T53

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

962

1

T9

13

T22

10

T53

5

auto[1]

943

1

T9

7

T22

10

T53

15

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

904

1

T9

7

T22

7

T53

10

auto[1]

1001

1

T9

13

T22

13

T53

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

44

1

T55

1

T43

1

T46

2

auto[0]

from_1to0

auto[0]

auto[1]

74

1

T9

1

T22

1

T55

1

auto[0]

from_1to0

auto[1]

auto[0]

34

1

T22

2

T46

2

T229

1

auto[0]

from_1to0

auto[1]

auto[1]

63

1

T9

1

T53

2

T55

1

auto[0]

from_0to1

auto[0]

auto[0]

50

1

T9

1

T22

1

T53

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T9

1

T22

1

T34

2

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T9

1

T22

2

T53

2

auto[0]

from_0to1

auto[1]

auto[1]

58

1

T9

1

T55

1

T46

1

auto[1]

from_1to0

auto[0]

auto[0]

58

1

T55

1

T229

2

T262

2

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T9

1

T22

2

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T9

1

T67

3

T111

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T9

1

T53

2

T55

1

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T22

1

T43

1

T229

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T55

2

T43

1

T67

2

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T53

1

T55

1

T43

1

auto[1]

from_0to1

auto[1]

auto[1]

54

1

T9

1

T43

1

T67

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

974

1

T9

15

T22

8

T53

8

auto[1]

931

1

T9

5

T22

12

T53

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

455

1

T9

5

T22

5

T53

3

from_0to1

456

1

T9

6

T22

6

T53

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

951

1

T9

11

T22

7

T53

12

auto[1]

954

1

T9

9

T22

13

T53

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

949

1

T9

13

T22

8

T53

13

auto[1]

956

1

T9

7

T22

12

T53

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

47

1

T9

1

T67

2

T46

2

auto[0]

from_1to0

auto[0]

auto[1]

73

1

T53

1

T43

4

T229

1

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T9

1

T229

2

T262

1

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T22

1

T262

1

T88

2

auto[0]

from_0to1

auto[0]

auto[0]

61

1

T9

2

T22

1

T67

2

auto[0]

from_0to1

auto[0]

auto[1]

53

1

T55

1

T43

1

T46

2

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T9

2

T22

1

T46

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T22

1

T67

1

T262

2

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T9

1

T53

2

T67

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T9

1

T22

1

T43

1

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T22

2

T55

2

T46

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T9

1

T22

1

T46

1

auto[1]

from_0to1

auto[0]

auto[0]

46

1

T9

1

T22

1

T229

2

auto[1]

from_0to1

auto[0]

auto[1]

50

1

T22

1

T53

2

T43

2

auto[1]

from_0to1

auto[1]

auto[0]

54

1

T9

1

T53

1

T43

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T22

1

T55

1

T43

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T9

9

T22

10

T53

7

auto[1]

944

1

T9

11

T22

10

T53

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

469

1

T9

4

T22

4

T53

4

from_0to1

459

1

T9

4

T22

3

T53

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

936

1

T9

16

T22

6

T53

9

auto[1]

969

1

T9

4

T22

14

T53

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

961

1

T9

7

T22

6

T53

10

auto[1]

944

1

T9

13

T22

14

T53

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

49

1

T229

1

T262

1

T88

2

auto[0]

from_1to0

auto[0]

auto[1]

67

1

T9

1

T53

1

T55

1

auto[0]

from_1to0

auto[1]

auto[0]

46

1

T53

1

T43

1

T46

1

auto[0]

from_1to0

auto[1]

auto[1]

57

1

T22

2

T55

1

T229

1

auto[0]

from_0to1

auto[0]

auto[0]

63

1

T9

1

T46

1

T229

1

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T22

1

T53

1

T55

1

auto[0]

from_0to1

auto[1]

auto[0]

69

1

T53

1

T262

1

T34

3

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T9

1

T43

2

T46

1

auto[1]

from_1to0

auto[0]

auto[0]

74

1

T9

1

T55

2

T43

4

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T9

2

T67

2

T229

1

auto[1]

from_1to0

auto[1]

auto[0]

58

1

T22

1

T53

2

T67

1

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T22

1

T67

2

T46

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T9

1

T53

1

T43

1

auto[1]

from_0to1

auto[0]

auto[1]

49

1

T9

1

T53

1

T55

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T22

1

T55

1

T67

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T22

1

T55

1

T67

3