Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	150232	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

114669

1

T1

287

T2

8

T6

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138112	1			T1	295		T2	11		T6	16
values[0x0]	63122	1			T1	259		T2	1		T6	2
values[0x1]	63667	1			T1	238		T2	7		T6	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121566	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

143335

1

T1

363

T2

10

T6

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	966	1			T12	5		T4	3		T14	3
valid_sources[0x01]	879	1			T1	4		T12	9		T4	3
valid_sources[0x02]	798	1			T1	4		T12	3		T14	5
valid_sources[0x03]	1013	1			T1	6		T12	3		T4	6
valid_sources[0x04]	998	1			T1	3		T12	1		T4	3
valid_sources[0x05]	891	1			T1	3		T4	1		T14	9
valid_sources[0x06]	910	1			T1	4		T12	6		T7	3
valid_sources[0x07]	1067	1			T1	1		T12	2		T4	2
valid_sources[0x08]	1798	1			T1	1		T4	4		T5	3
valid_sources[0x09]	1145	1			T1	3		T12	5		T4	2
valid_sources[0x0a]	990	1			T1	2		T12	8		T4	2
valid_sources[0x0b]	904	1			T1	3		T12	1		T4	2
valid_sources[0x0c]	866	1			T1	4		T12	3		T4	4
valid_sources[0x0d]	815	1			T1	2		T12	2		T4	1
valid_sources[0x0e]	835	1			T1	6		T12	2		T14	3
valid_sources[0x0f]	910	1			T1	4		T12	2		T4	1
valid_sources[0x10]	911	1			T1	6		T12	1		T4	2
valid_sources[0x11]	786	1			T1	2		T12	10		T4	2
valid_sources[0x12]	814	1			T1	1		T12	3		T4	2
valid_sources[0x13]	937	1			T1	4		T12	7		T4	1
valid_sources[0x14]	860	1			T1	1		T12	3		T4	4
valid_sources[0x15]	798	1			T1	1		T12	6		T4	3
valid_sources[0x16]	784	1			T1	1		T12	1		T4	2
valid_sources[0x17]	896	1			T1	4		T4	4		T14	5
valid_sources[0x18]	1049	1			T1	1		T12	3		T14	3
valid_sources[0x19]	902	1			T1	4		T4	1		T14	3
valid_sources[0x1a]	832	1			T14	6		T8	3		T42	2
valid_sources[0x1b]	2049	1			T1	6		T12	2		T14	2
valid_sources[0x1c]	767	1			T1	2		T6	4		T12	7
valid_sources[0x1d]	807	1			T1	1		T12	9		T4	2
valid_sources[0x1e]	1022	1			T1	5		T12	4		T4	3
valid_sources[0x1f]	1047	1			T1	1		T12	1		T4	2
valid_sources[0x20]	1062	1			T1	5		T12	4		T4	4
valid_sources[0x21]	800	1			T1	6		T12	6		T4	1
valid_sources[0x22]	1891	1			T1	1		T12	8		T4	2
valid_sources[0x23]	869	1			T1	3		T12	1		T4	2
valid_sources[0x24]	994	1			T1	4		T6	1		T12	4
valid_sources[0x25]	1003	1			T1	5		T12	5		T4	1
valid_sources[0x26]	804	1			T1	5		T12	3		T4	5
valid_sources[0x27]	1155	1			T1	4		T12	1		T4	1
valid_sources[0x28]	1042	1			T12	1		T4	2		T14	5
valid_sources[0x29]	887	1			T1	2		T2	2		T12	2
valid_sources[0x2a]	911	1			T1	2		T12	3		T4	1
valid_sources[0x2b]	994	1			T1	1		T12	2		T4	3
valid_sources[0x2c]	899	1			T1	6		T12	4		T14	4
valid_sources[0x2d]	881	1			T1	2		T12	1		T4	4
valid_sources[0x2e]	1209	1			T1	2		T12	4		T4	2
valid_sources[0x2f]	880	1			T1	1		T12	6		T4	1
valid_sources[0x30]	864	1			T1	3		T12	2		T4	4
valid_sources[0x31]	861	1			T1	4		T4	2		T14	2
valid_sources[0x32]	2064	1			T1	1		T12	4		T14	3
valid_sources[0x33]	844	1			T1	3		T12	2		T14	5
valid_sources[0x34]	870	1			T4	3		T14	3		T8	3
valid_sources[0x35]	966	1			T1	2		T12	4		T4	3
valid_sources[0x36]	803	1			T1	2		T12	4		T14	4
valid_sources[0x37]	879	1			T1	3		T12	4		T4	2
valid_sources[0x38]	2595	1			T1	1		T12	1		T4	6
valid_sources[0x39]	1057	1			T1	1		T12	1		T4	4
valid_sources[0x3a]	981	1			T1	1		T12	13		T4	2
valid_sources[0x3b]	2019	1			T1	5		T12	4		T4	2
valid_sources[0x3c]	703	1			T1	4		T12	1		T3	1
valid_sources[0x3d]	931	1			T1	5		T12	5		T4	1
valid_sources[0x3e]	1133	1			T1	3		T6	2		T12	6
valid_sources[0x3f]	819	1			T1	3		T4	3		T14	8
valid_sources[0x40]	935	1			T1	3		T12	2		T4	1
valid_sources[0x41]	952	1			T1	3		T12	7		T4	2
valid_sources[0x42]	1909	1			T1	1		T12	7		T4	2
valid_sources[0x43]	863	1			T1	3		T2	4		T12	4
valid_sources[0x44]	1511	1			T1	2		T6	1		T12	1
valid_sources[0x45]	851	1			T1	3		T12	1		T4	2
valid_sources[0x46]	1570	1			T1	3		T12	6		T4	2
valid_sources[0x47]	843	1			T1	5		T6	1		T12	4
valid_sources[0x48]	1082	1			T1	4		T12	4		T14	1
valid_sources[0x49]	856	1			T1	3		T12	3		T4	3
valid_sources[0x4a]	792	1			T1	9		T12	10		T4	3
valid_sources[0x4b]	1073	1			T1	4		T14	1		T8	1
valid_sources[0x4c]	789	1			T1	3		T2	2		T12	2
valid_sources[0x4d]	816	1			T1	3		T12	4		T4	3
valid_sources[0x4e]	1024	1			T1	1		T12	4		T14	5
valid_sources[0x4f]	906	1			T1	5		T12	1		T4	3
valid_sources[0x50]	863	1			T1	2		T12	2		T4	2
valid_sources[0x51]	2018	1			T1	4		T12	6		T4	4
valid_sources[0x52]	1065	1			T1	1		T12	4		T4	2
valid_sources[0x53]	1142	1			T1	1		T12	3		T4	5
valid_sources[0x54]	1021	1			T1	4		T4	3		T14	3
valid_sources[0x55]	996	1			T1	6		T12	1		T4	2
valid_sources[0x56]	957	1			T1	4		T2	3		T12	1
valid_sources[0x57]	1699	1			T1	3		T12	1		T4	3
valid_sources[0x58]	1030	1			T1	4		T12	5		T4	4
valid_sources[0x59]	1014	1			T1	3		T12	2		T4	1
valid_sources[0x5a]	882	1			T1	2		T12	4		T4	1
valid_sources[0x5b]	931	1			T1	1		T12	1		T4	4
valid_sources[0x5c]	818	1			T1	3		T12	4		T14	2
valid_sources[0x5d]	831	1			T1	5		T12	3		T3	2
valid_sources[0x5e]	830	1			T1	6		T4	3		T14	3
valid_sources[0x5f]	1711	1			T1	1		T14	5		T8	7
valid_sources[0x60]	838	1			T1	6		T12	6		T4	4
valid_sources[0x61]	1061	1			T1	1		T4	7		T14	2
valid_sources[0x62]	1414	1			T1	3		T12	7		T4	1
valid_sources[0x63]	1080	1			T1	2		T12	3		T4	2
valid_sources[0x64]	872	1			T1	2		T12	2		T4	2
valid_sources[0x65]	906	1			T1	2		T12	2		T4	5
valid_sources[0x66]	1047	1			T1	4		T12	2		T4	3
valid_sources[0x67]	929	1			T1	3		T12	1		T4	3
valid_sources[0x68]	840	1			T1	5		T4	3		T8	5
valid_sources[0x69]	805	1			T1	2		T3	1		T4	3
valid_sources[0x6a]	912	1			T1	4		T12	14		T4	1
valid_sources[0x6b]	1444	1			T1	7		T12	8		T4	2
valid_sources[0x6c]	884	1			T1	4		T12	4		T4	2
valid_sources[0x6d]	768	1			T1	2		T12	3		T4	6
valid_sources[0x6e]	1130	1			T1	2		T12	1		T4	2
valid_sources[0x6f]	1769	1			T1	6		T12	5		T4	1
valid_sources[0x70]	937	1			T1	2		T12	3		T4	1
valid_sources[0x71]	844	1			T1	5		T12	3		T4	3
valid_sources[0x72]	977	1			T1	4		T12	1		T4	2
valid_sources[0x73]	929	1			T1	3		T12	5		T4	4
valid_sources[0x74]	808	1			T1	1		T12	6		T4	5
valid_sources[0x75]	775	1			T1	1		T12	5		T4	2
valid_sources[0x76]	810	1			T1	5		T12	1		T4	4
valid_sources[0x77]	936	1			T1	3		T12	3		T4	2
valid_sources[0x78]	853	1			T1	2		T12	4		T4	3
valid_sources[0x79]	2163	1			T1	2		T12	2		T4	4
valid_sources[0x7a]	1998	1			T1	2		T12	4		T4	2
valid_sources[0x7b]	845	1			T1	4		T12	1		T4	3
valid_sources[0x7c]	852	1			T1	6		T4	5		T14	5
valid_sources[0x7d]	1132	1			T1	2		T12	7		T4	1
valid_sources[0x7e]	843	1			T1	6		T12	4		T3	2
valid_sources[0x7f]	823	1			T1	1		T12	2		T14	1
valid_sources[0x80]	841	1			T1	4		T12	8		T4	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

62283

1

T1

138

T2

3

T6

10

values[0x0]

all_enables

biggest_size

30646

1

T1

109

T2

1

T6

1

values[0x1]

all_enables

biggest_size

21740

1

T1

40

T2

4

T6

1