Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1217500475	11510	0	0
auto_block_debounce_ctl_rd_A	1217500475	2233	0	0
auto_block_out_ctl_rd_A	1217500475	3320	0	0
com_det_ctl_0_rd_A	1217500475	4313	0	0
com_det_ctl_1_rd_A	1217500475	4530	0	0
com_det_ctl_2_rd_A	1217500475	4225	0	0
com_det_ctl_3_rd_A	1217500475	4180	0	0
com_out_ctl_0_rd_A	1217500475	5063	0	0
com_out_ctl_1_rd_A	1217500475	5279	0	0
com_out_ctl_2_rd_A	1217500475	5051	0	0
com_out_ctl_3_rd_A	1217500475	5092	0	0
com_pre_det_ctl_0_rd_A	1217500475	1906	0	0
com_pre_det_ctl_1_rd_A	1217500475	1798	0	0
com_pre_det_ctl_2_rd_A	1217500475	1843	0	0
com_pre_det_ctl_3_rd_A	1217500475	1868	0	0
com_pre_sel_ctl_0_rd_A	1217500475	5306	0	0
com_pre_sel_ctl_1_rd_A	1217500475	5479	0	0
com_pre_sel_ctl_2_rd_A	1217500475	5205	0	0
com_pre_sel_ctl_3_rd_A	1217500475	5475	0	0
com_sel_ctl_0_rd_A	1217500475	5353	0	0
com_sel_ctl_1_rd_A	1217500475	5486	0	0
com_sel_ctl_2_rd_A	1217500475	5337	0	0
com_sel_ctl_3_rd_A	1217500475	4995	0	0
ec_rst_ctl_rd_A	1217500475	2824	0	0
intr_enable_rd_A	1217500475	2298	0	0
key_intr_ctl_rd_A	1217500475	5650	0	0
key_intr_debounce_ctl_rd_A	1217500475	1937	0	0
key_invert_ctl_rd_A	1217500475	7524	0	0
pin_allowed_ctl_rd_A	1217500475	7692	0	0
pin_out_ctl_rd_A	1217500475	5561	0	0
pin_out_value_rd_A	1217500475	5504	0	0
regwen_rd_A	1217500475	2112	0	0
ulp_ac_debounce_ctl_rd_A	1217500475	1885	0	0
ulp_ctl_rd_A	1217500475	1924	0	0
ulp_lid_debounce_ctl_rd_A	1217500475	2028	0	0
ulp_pwrb_debounce_ctl_rd_A	1217500475	1768	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	11510	0	0
T9	270618	17	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T30	0	12	0	0
T37	0	5	0	0
T42	521586	0	0	0
T43	0	12	0	0
T48	0	20	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T74	0	8	0	0
T110	0	6	0	0
T112	0	1	0	0
T173	0	5	0	0
T296	0	8	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	2233	0	0
T9	270618	34	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T37	0	11	0	0
T38	0	18	0	0
T42	521586	0	0	0
T50	0	15	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T141	0	10	0	0
T173	0	29	0	0
T212	0	11	0	0
T296	0	47	0	0
T297	0	5	0	0
T298	0	31	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	3320	0	0
T9	270618	32	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T37	0	12	0	0
T38	0	9	0	0
T42	521586	0	0	0
T50	0	15	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T141	0	7	0	0
T173	0	19	0	0
T212	0	11	0	0
T296	0	32	0	0
T297	0	6	0	0
T299	0	4	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	4313	0	0
T1	186479	42	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	56	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	69	0	0
T37	0	76	0	0
T88	0	78	0	0
T89	0	79	0	0
T108	0	41	0	0
T173	0	25	0	0
T252	0	64	0	0
T296	0	78	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	4530	0	0
T1	186479	28	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	43	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	82	0	0
T37	0	107	0	0
T88	0	56	0	0
T89	0	89	0	0
T108	0	41	0	0
T173	0	17	0	0
T252	0	72	0	0
T296	0	107	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	4225	0	0
T1	186479	30	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	44	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	63	0	0
T37	0	67	0	0
T88	0	83	0	0
T89	0	68	0	0
T108	0	63	0	0
T173	0	17	0	0
T252	0	77	0	0
T296	0	70	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	4180	0	0
T1	186479	39	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	38	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	67	0	0
T37	0	89	0	0
T88	0	78	0	0
T89	0	65	0	0
T108	0	42	0	0
T173	0	21	0	0
T252	0	73	0	0
T296	0	59	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5063	0	0
T1	186479	46	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	30	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	63	0	0
T37	0	105	0	0
T88	0	84	0	0
T89	0	92	0	0
T108	0	45	0	0
T173	0	16	0	0
T252	0	74	0	0
T296	0	60	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5279	0	0
T1	186479	28	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	40	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	85	0	0
T37	0	91	0	0
T88	0	42	0	0
T89	0	72	0	0
T108	0	43	0	0
T173	0	26	0	0
T252	0	91	0	0
T296	0	66	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5051	0	0
T1	186479	26	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	53	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	64	0	0
T37	0	77	0	0
T88	0	63	0	0
T89	0	84	0	0
T108	0	52	0	0
T173	0	16	0	0
T252	0	71	0	0
T296	0	88	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5092	0	0
T1	186479	31	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	35	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	64	0	0
T37	0	85	0	0
T88	0	75	0	0
T89	0	48	0	0
T108	0	50	0	0
T173	0	14	0	0
T252	0	64	0	0
T296	0	59	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	1906	0	0
T9	270618	18	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T37	0	3	0	0
T38	0	5	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T95	0	13	0	0
T141	0	6	0	0
T173	0	22	0	0
T296	0	27	0	0
T298	0	10	0	0
T300	0	17	0	0
T301	0	6	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	1798	0	0
T9	270618	8	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T37	0	5	0	0
T38	0	8	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T81	0	20	0	0
T95	0	12	0	0
T173	0	23	0	0
T296	0	23	0	0
T298	0	25	0	0
T300	0	6	0	0
T301	0	9	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	1843	0	0
T9	270618	13	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T37	0	11	0	0
T38	0	12	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T95	0	12	0	0
T141	0	2	0	0
T173	0	21	0	0
T296	0	36	0	0
T298	0	22	0	0
T300	0	29	0	0
T301	0	19	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	1868	0	0
T9	270618	14	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T37	0	1	0	0
T38	0	7	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T95	0	19	0	0
T141	0	6	0	0
T173	0	27	0	0
T296	0	39	0	0
T298	0	20	0	0
T300	0	7	0	0
T301	0	4	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5306	0	0
T1	186479	26	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	34	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	56	0	0
T37	0	94	0	0
T88	0	64	0	0
T89	0	75	0	0
T108	0	42	0	0
T173	0	27	0	0
T252	0	58	0	0
T296	0	86	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5479	0	0
T1	186479	37	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	56	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	69	0	0
T37	0	67	0	0
T88	0	82	0	0
T89	0	62	0	0
T108	0	49	0	0
T173	0	19	0	0
T252	0	67	0	0
T296	0	57	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5205	0	0
T1	186479	10	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	41	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	54	0	0
T37	0	75	0	0
T88	0	47	0	0
T89	0	60	0	0
T108	0	52	0	0
T173	0	22	0	0
T252	0	79	0	0
T296	0	68	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5475	0	0
T1	186479	40	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	43	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	87	0	0
T37	0	56	0	0
T88	0	71	0	0
T89	0	83	0	0
T108	0	62	0	0
T173	0	19	0	0
T252	0	65	0	0
T296	0	49	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5353	0	0
T1	186479	28	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	53	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	61	0	0
T37	0	111	0	0
T88	0	68	0	0
T89	0	56	0	0
T108	0	49	0	0
T173	0	15	0	0
T252	0	74	0	0
T296	0	72	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5486	0	0
T1	186479	31	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	51	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	76	0	0
T37	0	69	0	0
T88	0	78	0	0
T89	0	88	0	0
T108	0	70	0	0
T173	0	24	0	0
T252	0	65	0	0
T296	0	68	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5337	0	0
T1	186479	60	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	51	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	82	0	0
T37	0	93	0	0
T88	0	75	0	0
T89	0	66	0	0
T108	0	34	0	0
T173	0	36	0	0
T252	0	60	0	0
T296	0	67	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	4995	0	0
T1	186479	38	0	0
T2	25296	0	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T9	0	37	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T28	0	58	0	0
T37	0	97	0	0
T88	0	66	0	0
T89	0	87	0	0
T108	0	55	0	0
T173	0	30	0	0
T252	0	68	0	0
T296	0	60	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	2824	0	0
T9	270618	44	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T28	0	35	0	0
T35	0	1	0	0
T37	0	6	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	5	0	0
T55	160111	0	0	0
T88	0	23	0	0
T108	0	16	0	0
T173	0	26	0	0
T252	0	22	0	0
T296	0	59	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	2298	0	0
T9	270618	34	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T37	0	27	0	0
T38	0	19	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T88	0	16	0	0
T95	0	38	0	0
T141	0	5	0	0
T173	0	18	0	0
T296	0	44	0	0
T298	0	19	0	0
T300	0	24	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5650	0	0
T9	270618	26	0	0
T10	116251	0	0	0
T11	0	8	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T37	0	9	0	0
T38	0	16	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T141	0	12	0	0
T173	0	23	0	0
T176	0	2	0	0
T198	0	4	0	0
T296	0	19	0	0
T298	0	22	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	1937	0	0
T9	270618	18	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T37	0	8	0	0
T38	0	20	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T95	0	3	0	0
T141	0	7	0	0
T173	0	12	0	0
T296	0	41	0	0
T298	0	19	0	0
T300	0	10	0	0
T301	0	12	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	7524	0	0
T9	270618	377	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T35	0	78	0	0
T37	0	214	0	0
T38	0	19	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T60	0	23	0	0
T63	0	46	0	0
T105	0	68	0	0
T141	0	120	0	0
T173	0	10	0	0
T296	0	168	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	7692	0	0
T9	270618	81	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	38	0	0
T37	0	9	0	0
T38	0	10	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T88	0	83	0	0
T173	0	21	0	0
T198	0	69	0	0
T296	0	96	0	0
T302	0	82	0	0
T303	0	42	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5561	0	0
T9	270618	89	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	52	0	0
T37	0	7	0	0
T38	0	19	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T88	0	50	0	0
T173	0	33	0	0
T198	0	86	0	0
T296	0	92	0	0
T302	0	56	0	0
T303	0	32	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	5504	0	0
T9	270618	84	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	47	0	0
T37	0	4	0	0
T38	0	10	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T88	0	81	0	0
T173	0	23	0	0
T198	0	79	0	0
T296	0	97	0	0
T302	0	63	0	0
T303	0	45	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	2112	0	0
T9	270618	17	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T37	0	14	0	0
T38	0	8	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T95	0	9	0	0
T141	0	8	0	0
T173	0	30	0	0
T296	0	53	0	0
T298	0	20	0	0
T300	0	3	0	0
T301	0	1	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	1885	0	0
T9	270618	16	0	0
T10	116251	0	0	0
T20	237671	0	0	0
T22	241073	0	0	0
T35	0	1	0	0
T37	0	4	0	0
T38	0	9	0	0
T42	521586	0	0	0
T51	36771	0	0	0
T52	49086	0	0	0
T53	243701	0	0	0
T54	362324	0	0	0
T55	160111	0	0	0
T83	0	14	0	0
T84	0	20	0	0
T141	0	8	0	0
T173	0	17	0	0
T198	0	6	0	0
T296	0	15	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	1924	0	0
T2	25296	7	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T8	539891	0	0	0
T9	0	16	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T35	0	6	0	0
T37	0	13	0	0
T38	0	11	0	0
T83	0	15	0	0
T173	0	26	0	0
T198	0	1	0	0
T266	0	5	0	0
T296	0	41	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	2028	0	0
T2	25296	4	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T8	539891	0	0	0
T9	0	39	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T35	0	6	0	0
T37	0	12	0	0
T38	0	5	0	0
T83	0	10	0	0
T173	0	14	0	0
T198	0	5	0	0
T266	0	9	0	0
T296	0	39	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1217500475	1768	0	0
T2	25296	2	0	0
T3	250230	0	0	0
T4	904804	0	0	0
T5	79605	0	0	0
T6	49917	0	0	0
T7	71071	0	0	0
T8	539891	0	0	0
T9	0	8	0	0
T12	380533	0	0	0
T13	445986	0	0	0
T14	465047	0	0	0
T35	0	6	0	0
T37	0	7	0	0
T38	0	10	0	0
T83	0	12	0	0
T84	0	4	0	0
T173	0	13	0	0
T266	0	1	0	0
T296	0	27	0	0