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Summary for Variable cfg.vif.key0_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key0_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 160 1 T7 10 T68 8 T21 10
auto[1] 140 1 T7 10 T68 12 T21 10


Summary for Variable cfg.vif.key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key1_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 150 1 T7 10 T68 8 T21 11
auto[1] 150 1 T7 10 T68 12 T21 9


Summary for Variable cfg.vif.key1_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key1_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 159 1 T7 10 T68 16 T21 10
auto[1] 141 1 T7 10 T68 4 T21 10


Summary for Variable cfg.vif.key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key2_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 146 1 T7 7 T68 13 T21 11
auto[1] 154 1 T7 13 T68 7 T21 9


Summary for Variable cfg.vif.key2_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.key2_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 154 1 T7 11 T68 14 T21 11
auto[1] 146 1 T7 9 T68 6 T21 9


Summary for Variable cfg.vif.lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 164 1 T7 11 T68 14 T21 11
auto[1] 136 1 T7 9 T68 6 T21 9


Summary for Variable cfg.vif.pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.pwrb_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 158 1 T7 13 T68 14 T21 11
auto[1] 142 1 T7 7 T68 6 T21 9


Summary for Variable cfg.vif.pwrb_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.pwrb_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 147 1 T7 12 T68 12 T21 9
auto[1] 153 1 T7 8 T68 8 T21 11


Summary for Variable cfg.vif.z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cfg.vif.z3_wakeup

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 152 1 T7 12 T68 11 T21 9
auto[1] 148 1 T7 8 T68 9 T21 11


Summary for Variable cp_ac_present

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_ac_present

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 144 1 T7 9 T68 10 T21 11
auto[1] 156 1 T7 11 T68 10 T21 9


Summary for Variable cp_bat_disable

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_bat_disable

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 159 1 T7 14 T68 11 T21 10
auto[1] 141 1 T7 6 T68 9 T21 10


Summary for Variable cp_key0_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 156 1 T7 12 T68 11 T21 6
auto[1] 144 1 T7 8 T68 9 T21 14


Summary for Variable cp_key0_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key0_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 160 1 T7 14 T68 10 T21 6
auto[1] 140 1 T7 6 T68 10 T21 14


Summary for Variable cp_key1_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 139 1 T7 11 T68 8 T21 10
auto[1] 161 1 T7 9 T68 12 T21 10


Summary for Variable cp_key1_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key1_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 160 1 T7 11 T68 12 T21 5
auto[1] 140 1 T7 9 T68 8 T21 15


Summary for Variable cp_key2_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 137 1 T7 8 T68 7 T21 12
auto[1] 163 1 T7 12 T68 13 T21 8


Summary for Variable cp_key2_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_key2_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 157 1 T7 16 T68 12 T21 8
auto[1] 143 1 T7 4 T68 8 T21 12


Summary for Variable cp_lid_open

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_lid_open

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 142 1 T7 12 T68 9 T21 6
auto[1] 158 1 T7 8 T68 11 T21 14


Summary for Variable cp_pwrb_in

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_in

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 148 1 T7 6 T68 9 T21 14
auto[1] 152 1 T7 14 T68 11 T21 6


Summary for Variable cp_pwrb_out

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_pwrb_out

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 141 1 T7 5 T68 9 T21 12
auto[1] 159 1 T7 15 T68 11 T21 8


Summary for Variable cp_z3_wakeup

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_z3_wakeup

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 152 1 T7 12 T68 11 T21 9
auto[1] 148 1 T7 8 T68 9 T21 11


Summary for Cross key0_inXval

Samples crossed: cp_key0_in cfg.vif.key0_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_inXval

Bins
cp_key0_incfg.vif.key0_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 85 1 T7 9 T68 7 T21 3
auto[0] auto[1] 71 1 T7 3 T68 4 T21 3
auto[1] auto[0] 73 1 T7 1 T68 4 T21 5
auto[1] auto[1] 71 1 T7 7 T68 5 T21 9


Summary for Cross key0_outXval

Samples crossed: cp_key0_out cfg.vif.key0_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key0_outXval

Bins
cp_key0_outcfg.vif.key0_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 88 1 T7 10 T68 5 T21 4
auto[0] auto[1] 72 1 T7 4 T68 5 T21 2
auto[1] auto[0] 72 1 T68 3 T21 6 T291 3
auto[1] auto[1] 68 1 T7 6 T68 7 T21 8


Summary for Cross key1_inXval

Samples crossed: cp_key1_in cfg.vif.key1_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_inXval

Bins
cp_key1_incfg.vif.key1_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 77 1 T7 8 T68 4 T21 5
auto[0] auto[1] 62 1 T7 3 T68 4 T21 5
auto[1] auto[0] 73 1 T7 2 T68 4 T21 6
auto[1] auto[1] 88 1 T7 7 T68 8 T21 4


Summary for Cross key1_outXval

Samples crossed: cp_key1_out cfg.vif.key1_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key1_outXval

Bins
cp_key1_outcfg.vif.key1_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 92 1 T7 8 T68 10 T21 2
auto[0] auto[1] 68 1 T7 3 T68 2 T21 3
auto[1] auto[0] 67 1 T7 2 T68 6 T21 8
auto[1] auto[1] 73 1 T7 7 T68 2 T21 7


Summary for Cross key2_inXval

Samples crossed: cp_key2_in cfg.vif.key2_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_inXval

Bins
cp_key2_incfg.vif.key2_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 71 1 T7 4 T68 4 T21 5
auto[0] auto[1] 66 1 T7 4 T68 3 T21 7
auto[1] auto[0] 75 1 T7 3 T68 9 T21 6
auto[1] auto[1] 88 1 T7 9 T68 4 T21 2


Summary for Cross key2_outXval

Samples crossed: cp_key2_out cfg.vif.key2_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for key2_outXval

Bins
cp_key2_outcfg.vif.key2_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 85 1 T7 10 T68 7 T21 3
auto[0] auto[1] 72 1 T7 6 T68 5 T21 5
auto[1] auto[0] 69 1 T7 1 T68 7 T21 8
auto[1] auto[1] 74 1 T7 3 T68 1 T21 4


Summary for Cross pwrb_inXval

Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_inXval

Bins
cp_pwrb_incfg.vif.pwrb_inCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 81 1 T7 5 T68 6 T21 9
auto[0] auto[1] 67 1 T7 1 T68 3 T21 5
auto[1] auto[0] 77 1 T7 8 T68 8 T21 2
auto[1] auto[1] 75 1 T7 6 T68 3 T21 4


Summary for Cross pwrb_outXval

Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for pwrb_outXval

Bins
cp_pwrb_outcfg.vif.pwrb_outCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 72 1 T7 4 T68 5 T21 7
auto[0] auto[1] 69 1 T7 1 T68 4 T21 5
auto[1] auto[0] 75 1 T7 8 T68 7 T21 2
auto[1] auto[1] 84 1 T7 7 T68 4 T21 6


Summary for Cross ac_presentXval

Samples crossed: cp_ac_present cfg.vif.ac_present
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for ac_presentXval

Bins
cp_ac_presentcfg.vif.ac_presentCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 72 1 T7 6 T68 6 T21 3
auto[0] auto[1] 72 1 T7 3 T68 4 T21 8
auto[1] auto[0] 83 1 T7 6 T68 5 T21 3
auto[1] auto[1] 73 1 T7 5 T68 5 T21 6


Summary for Cross bat_disableXval

Samples crossed: cp_bat_disable cfg.vif.bat_disable
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for bat_disableXval

Bins
cp_bat_disablecfg.vif.bat_disableCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 159 1 T7 14 T68 11 T21 10
auto[1] auto[1] 141 1 T7 6 T68 9 T21 10


User Defined Cross Bins for bat_disableXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded


Summary for Cross lid_openXval

Samples crossed: cp_lid_open cfg.vif.lid_open
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 4 0 4 100.00


Automatically Generated Cross Bins for lid_openXval

Bins
cp_lid_opencfg.vif.lid_openCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 81 1 T7 5 T68 7 T21 5
auto[0] auto[1] 61 1 T7 7 T68 2 T21 1
auto[1] auto[0] 83 1 T7 6 T68 7 T21 6
auto[1] auto[1] 75 1 T7 2 T68 4 T21 8


Summary for Cross z3_wakeupXval

Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 2 0 2 100.00
Automatically Generated Cross Bins 2 0 2 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for z3_wakeupXval

Bins
cp_z3_wakeupcfg.vif.z3_wakeupCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] auto[0] 152 1 T7 12 T68 11 T21 9
auto[1] auto[1] 148 1 T7 8 T68 9 T21 11


User Defined Cross Bins for z3_wakeupXval

Excluded/Illegal bins
NAMECOUNTSTATUS
invalid0 0 Excluded
invalid1 0 Excluded

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