Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T8 |
7 |
|
T23 |
12 |
|
T24 |
12 |
| auto[1] |
814 |
1 |
|
|
T8 |
13 |
|
T23 |
8 |
|
T24 |
8 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T8 |
13 |
|
T23 |
8 |
|
T24 |
9 |
| auto[1] |
811 |
1 |
|
|
T8 |
7 |
|
T23 |
12 |
|
T24 |
11 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
832 |
1 |
|
|
T8 |
10 |
|
T23 |
13 |
|
T24 |
10 |
| auto[1] |
808 |
1 |
|
|
T8 |
10 |
|
T23 |
7 |
|
T24 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
798 |
1 |
|
|
T8 |
8 |
|
T23 |
9 |
|
T24 |
4 |
| auto[1] |
842 |
1 |
|
|
T8 |
12 |
|
T23 |
11 |
|
T24 |
16 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
845 |
1 |
|
|
T8 |
9 |
|
T23 |
9 |
|
T24 |
14 |
| auto[1] |
795 |
1 |
|
|
T8 |
11 |
|
T23 |
11 |
|
T24 |
6 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
818 |
1 |
|
|
T8 |
7 |
|
T23 |
5 |
|
T24 |
10 |
| auto[1] |
822 |
1 |
|
|
T8 |
13 |
|
T23 |
15 |
|
T24 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
818 |
1 |
|
|
T8 |
7 |
|
T23 |
7 |
|
T24 |
9 |
| auto[1] |
822 |
1 |
|
|
T8 |
13 |
|
T23 |
13 |
|
T24 |
11 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
831 |
1 |
|
|
T8 |
10 |
|
T23 |
11 |
|
T24 |
10 |
| auto[1] |
809 |
1 |
|
|
T8 |
10 |
|
T23 |
9 |
|
T24 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
838 |
1 |
|
|
T8 |
14 |
|
T23 |
6 |
|
T24 |
10 |
| auto[1] |
802 |
1 |
|
|
T8 |
6 |
|
T23 |
14 |
|
T24 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
855 |
1 |
|
|
T8 |
13 |
|
T23 |
10 |
|
T24 |
10 |
| auto[1] |
785 |
1 |
|
|
T8 |
7 |
|
T23 |
10 |
|
T24 |
10 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T8 |
6 |
|
T23 |
12 |
|
T24 |
9 |
| auto[1] |
827 |
1 |
|
|
T8 |
14 |
|
T23 |
8 |
|
T24 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
798 |
1 |
|
|
T8 |
7 |
|
T23 |
11 |
|
T24 |
10 |
| auto[1] |
842 |
1 |
|
|
T8 |
13 |
|
T23 |
9 |
|
T24 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
836 |
1 |
|
|
T8 |
11 |
|
T23 |
13 |
|
T24 |
15 |
| auto[1] |
804 |
1 |
|
|
T8 |
9 |
|
T23 |
7 |
|
T24 |
5 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
829 |
1 |
|
|
T8 |
13 |
|
T23 |
8 |
|
T24 |
9 |
| auto[1] |
811 |
1 |
|
|
T8 |
7 |
|
T23 |
12 |
|
T24 |
11 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
821 |
1 |
|
|
T8 |
9 |
|
T23 |
13 |
|
T24 |
5 |
| auto[1] |
819 |
1 |
|
|
T8 |
11 |
|
T23 |
7 |
|
T24 |
15 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
823 |
1 |
|
|
T8 |
15 |
|
T23 |
9 |
|
T24 |
11 |
| auto[1] |
817 |
1 |
|
|
T8 |
5 |
|
T23 |
11 |
|
T24 |
9 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
813 |
1 |
|
|
T8 |
6 |
|
T23 |
9 |
|
T24 |
6 |
| auto[1] |
827 |
1 |
|
|
T8 |
14 |
|
T23 |
11 |
|
T24 |
14 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
826 |
1 |
|
|
T8 |
16 |
|
T23 |
13 |
|
T24 |
12 |
| auto[1] |
814 |
1 |
|
|
T8 |
4 |
|
T23 |
7 |
|
T24 |
8 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
812 |
1 |
|
|
T8 |
11 |
|
T23 |
9 |
|
T24 |
12 |
| auto[1] |
828 |
1 |
|
|
T8 |
9 |
|
T23 |
11 |
|
T24 |
8 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
827 |
1 |
|
|
T8 |
6 |
|
T23 |
11 |
|
T24 |
9 |
| auto[1] |
813 |
1 |
|
|
T8 |
14 |
|
T23 |
9 |
|
T24 |
11 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
811 |
1 |
|
|
T8 |
10 |
|
T23 |
8 |
|
T24 |
9 |
| auto[1] |
829 |
1 |
|
|
T8 |
10 |
|
T23 |
12 |
|
T24 |
11 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
858 |
1 |
|
|
T8 |
12 |
|
T23 |
10 |
|
T24 |
11 |
| auto[1] |
782 |
1 |
|
|
T8 |
8 |
|
T23 |
10 |
|
T24 |
9 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
808 |
1 |
|
|
T8 |
11 |
|
T23 |
10 |
|
T24 |
10 |
| auto[1] |
832 |
1 |
|
|
T8 |
9 |
|
T23 |
10 |
|
T24 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
798 |
1 |
|
|
T8 |
7 |
|
T23 |
11 |
|
T24 |
10 |
| auto[1] |
842 |
1 |
|
|
T8 |
13 |
|
T23 |
9 |
|
T24 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
412 |
1 |
|
|
T8 |
5 |
|
T23 |
10 |
|
T24 |
1 |
| auto[0] |
auto[1] |
409 |
1 |
|
|
T8 |
4 |
|
T23 |
3 |
|
T24 |
4 |
| auto[1] |
auto[0] |
420 |
1 |
|
|
T8 |
5 |
|
T23 |
3 |
|
T24 |
9 |
| auto[1] |
auto[1] |
399 |
1 |
|
|
T8 |
6 |
|
T23 |
4 |
|
T24 |
6 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
396 |
1 |
|
|
T8 |
7 |
|
T23 |
6 |
|
T24 |
1 |
| auto[0] |
auto[1] |
427 |
1 |
|
|
T8 |
8 |
|
T23 |
3 |
|
T24 |
10 |
| auto[1] |
auto[0] |
402 |
1 |
|
|
T8 |
1 |
|
T23 |
3 |
|
T24 |
3 |
| auto[1] |
auto[1] |
415 |
1 |
|
|
T8 |
4 |
|
T23 |
8 |
|
T24 |
6 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
399 |
1 |
|
|
T8 |
1 |
|
T23 |
3 |
|
T24 |
3 |
| auto[0] |
auto[1] |
414 |
1 |
|
|
T8 |
5 |
|
T23 |
6 |
|
T24 |
3 |
| auto[1] |
auto[0] |
446 |
1 |
|
|
T8 |
8 |
|
T23 |
6 |
|
T24 |
11 |
| auto[1] |
auto[1] |
381 |
1 |
|
|
T8 |
6 |
|
T23 |
5 |
|
T24 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
392 |
1 |
|
|
T8 |
5 |
|
T23 |
3 |
|
T24 |
4 |
| auto[0] |
auto[1] |
434 |
1 |
|
|
T8 |
11 |
|
T23 |
10 |
|
T24 |
8 |
| auto[1] |
auto[0] |
426 |
1 |
|
|
T8 |
2 |
|
T23 |
2 |
|
T24 |
6 |
| auto[1] |
auto[1] |
388 |
1 |
|
|
T8 |
2 |
|
T23 |
5 |
|
T24 |
2 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
394 |
1 |
|
|
T8 |
4 |
|
T23 |
6 |
|
T24 |
7 |
| auto[0] |
auto[1] |
418 |
1 |
|
|
T8 |
7 |
|
T23 |
3 |
|
T24 |
5 |
| auto[1] |
auto[0] |
424 |
1 |
|
|
T8 |
3 |
|
T23 |
1 |
|
T24 |
2 |
| auto[1] |
auto[1] |
404 |
1 |
|
|
T8 |
6 |
|
T23 |
10 |
|
T24 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
408 |
1 |
|
|
T8 |
3 |
|
T23 |
9 |
|
T24 |
6 |
| auto[0] |
auto[1] |
419 |
1 |
|
|
T8 |
3 |
|
T23 |
2 |
|
T24 |
3 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T8 |
7 |
|
T23 |
2 |
|
T24 |
4 |
| auto[1] |
auto[1] |
390 |
1 |
|
|
T8 |
7 |
|
T23 |
7 |
|
T24 |
7 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
447 |
1 |
|
|
T8 |
9 |
|
T23 |
6 |
|
T24 |
6 |
| auto[0] |
auto[1] |
411 |
1 |
|
|
T8 |
3 |
|
T23 |
4 |
|
T24 |
5 |
| auto[1] |
auto[0] |
408 |
1 |
|
|
T8 |
4 |
|
T23 |
4 |
|
T24 |
4 |
| auto[1] |
auto[1] |
374 |
1 |
|
|
T8 |
4 |
|
T23 |
6 |
|
T24 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
401 |
1 |
|
|
T8 |
5 |
|
T23 |
7 |
|
T24 |
5 |
| auto[0] |
auto[1] |
407 |
1 |
|
|
T8 |
6 |
|
T23 |
3 |
|
T24 |
5 |
| auto[1] |
auto[0] |
412 |
1 |
|
|
T8 |
1 |
|
T23 |
5 |
|
T24 |
4 |
| auto[1] |
auto[1] |
420 |
1 |
|
|
T8 |
8 |
|
T23 |
5 |
|
T24 |
6 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
422 |
1 |
|
|
T8 |
3 |
|
T23 |
6 |
|
T24 |
8 |
| auto[0] |
auto[1] |
414 |
1 |
|
|
T8 |
8 |
|
T23 |
7 |
|
T24 |
7 |
| auto[1] |
auto[0] |
404 |
1 |
|
|
T8 |
4 |
|
T23 |
6 |
|
T24 |
4 |
| auto[1] |
auto[1] |
400 |
1 |
|
|
T8 |
5 |
|
T23 |
1 |
|
T24 |
1 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
829 |
1 |
|
|
T8 |
13 |
|
T23 |
8 |
|
T24 |
9 |
| auto[1] |
auto[1] |
811 |
1 |
|
|
T8 |
7 |
|
T23 |
12 |
|
T24 |
11 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
396 |
1 |
|
|
T8 |
9 |
|
T23 |
2 |
|
T24 |
5 |
| auto[0] |
auto[1] |
415 |
1 |
|
|
T8 |
1 |
|
T23 |
6 |
|
T24 |
4 |
| auto[1] |
auto[0] |
442 |
1 |
|
|
T8 |
5 |
|
T23 |
4 |
|
T24 |
5 |
| auto[1] |
auto[1] |
387 |
1 |
|
|
T8 |
5 |
|
T23 |
8 |
|
T24 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
798 |
1 |
|
|
T8 |
7 |
|
T23 |
11 |
|
T24 |
10 |
| auto[1] |
auto[1] |
842 |
1 |
|
|
T8 |
13 |
|
T23 |
9 |
|
T24 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130 |
1 |
|
|
T33 |
10 |
|
T36 |
8 |
|
T40 |
10 |
| auto[1] |
150 |
1 |
|
|
T33 |
10 |
|
T36 |
12 |
|
T40 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T33 |
10 |
|
T36 |
11 |
|
T40 |
7 |
| auto[1] |
142 |
1 |
|
|
T33 |
10 |
|
T36 |
9 |
|
T40 |
13 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T33 |
13 |
|
T36 |
8 |
|
T40 |
13 |
| auto[1] |
133 |
1 |
|
|
T33 |
7 |
|
T36 |
12 |
|
T40 |
7 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T33 |
10 |
|
T36 |
8 |
|
T40 |
5 |
| auto[1] |
144 |
1 |
|
|
T33 |
10 |
|
T36 |
12 |
|
T40 |
15 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
140 |
1 |
|
|
T33 |
12 |
|
T36 |
9 |
|
T40 |
12 |
| auto[1] |
140 |
1 |
|
|
T33 |
8 |
|
T36 |
11 |
|
T40 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T33 |
5 |
|
T36 |
10 |
|
T40 |
9 |
| auto[1] |
138 |
1 |
|
|
T33 |
15 |
|
T36 |
10 |
|
T40 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T33 |
11 |
|
T36 |
8 |
|
T40 |
8 |
| auto[1] |
143 |
1 |
|
|
T33 |
9 |
|
T36 |
12 |
|
T40 |
12 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
132 |
1 |
|
|
T33 |
9 |
|
T36 |
6 |
|
T40 |
10 |
| auto[1] |
148 |
1 |
|
|
T33 |
11 |
|
T36 |
14 |
|
T40 |
10 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T33 |
10 |
|
T36 |
9 |
|
T40 |
10 |
| auto[1] |
143 |
1 |
|
|
T33 |
10 |
|
T36 |
11 |
|
T40 |
10 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
122 |
1 |
|
|
T33 |
10 |
|
T36 |
8 |
|
T40 |
4 |
| auto[1] |
158 |
1 |
|
|
T33 |
10 |
|
T36 |
12 |
|
T40 |
16 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
141 |
1 |
|
|
T33 |
12 |
|
T36 |
11 |
|
T40 |
6 |
| auto[1] |
139 |
1 |
|
|
T33 |
8 |
|
T36 |
9 |
|
T40 |
14 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T33 |
5 |
|
T36 |
8 |
|
T40 |
7 |
| auto[1] |
143 |
1 |
|
|
T33 |
15 |
|
T36 |
12 |
|
T40 |
13 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
146 |
1 |
|
|
T33 |
11 |
|
T36 |
7 |
|
T40 |
8 |
| auto[1] |
134 |
1 |
|
|
T33 |
9 |
|
T36 |
13 |
|
T40 |
12 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T33 |
10 |
|
T36 |
11 |
|
T40 |
7 |
| auto[1] |
142 |
1 |
|
|
T33 |
10 |
|
T36 |
9 |
|
T40 |
13 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T33 |
11 |
|
T36 |
11 |
|
T40 |
9 |
| auto[1] |
142 |
1 |
|
|
T33 |
9 |
|
T36 |
9 |
|
T40 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
131 |
1 |
|
|
T33 |
8 |
|
T36 |
7 |
|
T40 |
9 |
| auto[1] |
149 |
1 |
|
|
T33 |
12 |
|
T36 |
13 |
|
T40 |
11 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
142 |
1 |
|
|
T33 |
9 |
|
T36 |
10 |
|
T40 |
9 |
| auto[1] |
138 |
1 |
|
|
T33 |
11 |
|
T36 |
10 |
|
T40 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T33 |
14 |
|
T36 |
11 |
|
T40 |
4 |
| auto[1] |
144 |
1 |
|
|
T33 |
6 |
|
T36 |
9 |
|
T40 |
16 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
130 |
1 |
|
|
T33 |
7 |
|
T36 |
9 |
|
T40 |
7 |
| auto[1] |
150 |
1 |
|
|
T33 |
13 |
|
T36 |
11 |
|
T40 |
13 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T33 |
11 |
|
T36 |
11 |
|
T40 |
11 |
| auto[1] |
127 |
1 |
|
|
T33 |
9 |
|
T36 |
9 |
|
T40 |
9 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
144 |
1 |
|
|
T33 |
9 |
|
T36 |
11 |
|
T40 |
6 |
| auto[1] |
136 |
1 |
|
|
T33 |
11 |
|
T36 |
9 |
|
T40 |
14 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
138 |
1 |
|
|
T33 |
11 |
|
T36 |
8 |
|
T40 |
15 |
| auto[1] |
142 |
1 |
|
|
T33 |
9 |
|
T36 |
12 |
|
T40 |
5 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
129 |
1 |
|
|
T33 |
11 |
|
T36 |
11 |
|
T40 |
7 |
| auto[1] |
151 |
1 |
|
|
T33 |
9 |
|
T36 |
9 |
|
T40 |
13 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T33 |
5 |
|
T36 |
8 |
|
T40 |
7 |
| auto[1] |
143 |
1 |
|
|
T33 |
15 |
|
T36 |
12 |
|
T40 |
13 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
75 |
1 |
|
|
T33 |
7 |
|
T36 |
8 |
|
T40 |
7 |
| auto[0] |
auto[1] |
63 |
1 |
|
|
T33 |
4 |
|
T36 |
3 |
|
T40 |
2 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T33 |
6 |
|
T40 |
6 |
|
T177 |
4 |
| auto[1] |
auto[1] |
70 |
1 |
|
|
T33 |
3 |
|
T36 |
9 |
|
T40 |
5 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
66 |
1 |
|
|
T33 |
4 |
|
T36 |
6 |
|
T40 |
3 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T33 |
4 |
|
T36 |
1 |
|
T40 |
6 |
| auto[1] |
auto[0] |
70 |
1 |
|
|
T33 |
6 |
|
T36 |
2 |
|
T40 |
2 |
| auto[1] |
auto[1] |
79 |
1 |
|
|
T33 |
6 |
|
T36 |
11 |
|
T40 |
9 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
71 |
1 |
|
|
T33 |
5 |
|
T36 |
2 |
|
T40 |
6 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T33 |
4 |
|
T36 |
8 |
|
T40 |
3 |
| auto[1] |
auto[0] |
69 |
1 |
|
|
T33 |
7 |
|
T36 |
7 |
|
T40 |
6 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T33 |
4 |
|
T36 |
3 |
|
T40 |
5 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T33 |
4 |
|
T36 |
3 |
|
T40 |
2 |
| auto[0] |
auto[1] |
67 |
1 |
|
|
T33 |
10 |
|
T36 |
8 |
|
T40 |
2 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T33 |
1 |
|
T36 |
7 |
|
T40 |
7 |
| auto[1] |
auto[1] |
71 |
1 |
|
|
T33 |
5 |
|
T36 |
2 |
|
T40 |
9 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
65 |
1 |
|
|
T33 |
4 |
|
T36 |
4 |
|
T40 |
2 |
| auto[0] |
auto[1] |
65 |
1 |
|
|
T33 |
3 |
|
T36 |
5 |
|
T40 |
5 |
| auto[1] |
auto[0] |
72 |
1 |
|
|
T33 |
7 |
|
T36 |
4 |
|
T40 |
6 |
| auto[1] |
auto[1] |
78 |
1 |
|
|
T33 |
6 |
|
T36 |
7 |
|
T40 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
74 |
1 |
|
|
T33 |
5 |
|
T36 |
4 |
|
T40 |
5 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T33 |
6 |
|
T36 |
7 |
|
T40 |
6 |
| auto[1] |
auto[0] |
58 |
1 |
|
|
T33 |
4 |
|
T36 |
2 |
|
T40 |
5 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T33 |
5 |
|
T36 |
7 |
|
T40 |
4 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
55 |
1 |
|
|
T33 |
6 |
|
T36 |
4 |
|
T40 |
4 |
| auto[0] |
auto[1] |
83 |
1 |
|
|
T33 |
5 |
|
T36 |
4 |
|
T40 |
11 |
| auto[1] |
auto[0] |
67 |
1 |
|
|
T33 |
4 |
|
T36 |
4 |
|
T177 |
4 |
| auto[1] |
auto[1] |
75 |
1 |
|
|
T33 |
5 |
|
T36 |
8 |
|
T40 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
60 |
1 |
|
|
T33 |
7 |
|
T36 |
7 |
|
T40 |
1 |
| auto[0] |
auto[1] |
69 |
1 |
|
|
T33 |
4 |
|
T36 |
4 |
|
T40 |
6 |
| auto[1] |
auto[0] |
81 |
1 |
|
|
T33 |
5 |
|
T36 |
4 |
|
T40 |
5 |
| auto[1] |
auto[1] |
70 |
1 |
|
|
T33 |
4 |
|
T36 |
5 |
|
T40 |
8 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
70 |
1 |
|
|
T33 |
6 |
|
T36 |
2 |
|
T40 |
4 |
| auto[0] |
auto[1] |
76 |
1 |
|
|
T33 |
5 |
|
T36 |
5 |
|
T40 |
4 |
| auto[1] |
auto[0] |
60 |
1 |
|
|
T33 |
4 |
|
T36 |
6 |
|
T40 |
6 |
| auto[1] |
auto[1] |
74 |
1 |
|
|
T33 |
5 |
|
T36 |
7 |
|
T40 |
6 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
138 |
1 |
|
|
T33 |
10 |
|
T36 |
11 |
|
T40 |
7 |
| auto[1] |
auto[1] |
142 |
1 |
|
|
T33 |
10 |
|
T36 |
9 |
|
T40 |
13 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
73 |
1 |
|
|
T33 |
5 |
|
T36 |
6 |
|
T40 |
4 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T33 |
4 |
|
T36 |
5 |
|
T40 |
2 |
| auto[1] |
auto[0] |
64 |
1 |
|
|
T33 |
5 |
|
T36 |
3 |
|
T40 |
6 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T33 |
6 |
|
T36 |
6 |
|
T40 |
8 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
137 |
1 |
|
|
T33 |
5 |
|
T36 |
8 |
|
T40 |
7 |
| auto[1] |
auto[1] |
143 |
1 |
|
|
T33 |
15 |
|
T36 |
12 |
|
T40 |
13 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
33 |
1 |
|
|
T40 |
12 |
|
T177 |
14 |
|
T152 |
7 |
| auto[1] |
27 |
1 |
|
|
T40 |
8 |
|
T177 |
6 |
|
T152 |
13 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
33 |
1 |
|
|
T40 |
10 |
|
T177 |
7 |
|
T152 |
16 |
| auto[1] |
27 |
1 |
|
|
T40 |
10 |
|
T177 |
13 |
|
T152 |
4 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
29 |
1 |
|
|
T40 |
8 |
|
T177 |
11 |
|
T152 |
10 |
| auto[1] |
31 |
1 |
|
|
T40 |
12 |
|
T177 |
9 |
|
T152 |
10 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
31 |
1 |
|
|
T40 |
12 |
|
T177 |
11 |
|
T152 |
8 |
| auto[1] |
29 |
1 |
|
|
T40 |
8 |
|
T177 |
9 |
|
T152 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
30 |
1 |
|
|
T40 |
11 |
|
T177 |
7 |
|
T152 |
12 |
| auto[1] |
30 |
1 |
|
|
T40 |
9 |
|
T177 |
13 |
|
T152 |
8 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
25 |
1 |
|
|
T40 |
6 |
|
T177 |
9 |
|
T152 |
10 |
| auto[1] |
35 |
1 |
|
|
T40 |
14 |
|
T177 |
11 |
|
T152 |
10 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
29 |
1 |
|
|
T40 |
9 |
|
T177 |
7 |
|
T152 |
13 |
| auto[1] |
31 |
1 |
|
|
T40 |
11 |
|
T177 |
13 |
|
T152 |
7 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
31 |
1 |
|
|
T40 |
10 |
|
T177 |
11 |
|
T152 |
10 |
| auto[1] |
29 |
1 |
|
|
T40 |
10 |
|
T177 |
9 |
|
T152 |
10 |