Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
16 |
1 |
|
|
T40 |
6 |
|
T177 |
10 |
| auto[1] |
24 |
1 |
|
|
T40 |
14 |
|
T177 |
10 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19 |
1 |
|
|
T40 |
8 |
|
T177 |
11 |
| auto[1] |
21 |
1 |
|
|
T40 |
12 |
|
T177 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18 |
1 |
|
|
T40 |
9 |
|
T177 |
9 |
| auto[1] |
22 |
1 |
|
|
T40 |
11 |
|
T177 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
25 |
1 |
|
|
T40 |
12 |
|
T177 |
13 |
| auto[1] |
15 |
1 |
|
|
T40 |
8 |
|
T177 |
7 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19 |
1 |
|
|
T40 |
13 |
|
T177 |
6 |
| auto[1] |
21 |
1 |
|
|
T40 |
7 |
|
T177 |
14 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T40 |
6 |
|
T177 |
6 |
| auto[1] |
28 |
1 |
|
|
T40 |
14 |
|
T177 |
14 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17 |
1 |
|
|
T40 |
11 |
|
T177 |
6 |
| auto[1] |
23 |
1 |
|
|
T40 |
9 |
|
T177 |
14 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20 |
1 |
|
|
T40 |
9 |
|
T177 |
11 |
| auto[1] |
20 |
1 |
|
|
T40 |
11 |
|
T177 |
9 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
14 |
1 |
|
|
T40 |
8 |
|
T177 |
6 |
| auto[1] |
26 |
1 |
|
|
T40 |
12 |
|
T177 |
14 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
26 |
1 |
|
|
T40 |
15 |
|
T177 |
11 |
| auto[1] |
14 |
1 |
|
|
T40 |
5 |
|
T177 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
18 |
1 |
|
|
T40 |
11 |
|
T177 |
7 |
| auto[1] |
22 |
1 |
|
|
T40 |
9 |
|
T177 |
13 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17 |
1 |
|
|
T40 |
9 |
|
T177 |
8 |
| auto[1] |
23 |
1 |
|
|
T40 |
11 |
|
T177 |
12 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
13 |
1 |
|
|
T40 |
7 |
|
T177 |
6 |
| auto[1] |
27 |
1 |
|
|
T40 |
13 |
|
T177 |
14 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
19 |
1 |
|
|
T40 |
8 |
|
T177 |
11 |
| auto[1] |
21 |
1 |
|
|
T40 |
12 |
|
T177 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
21 |
1 |
|
|
T40 |
11 |
|
T177 |
10 |
| auto[1] |
19 |
1 |
|
|
T40 |
9 |
|
T177 |
10 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
12 |
1 |
|
|
T40 |
8 |
|
T177 |
4 |
| auto[1] |
28 |
1 |
|
|
T40 |
12 |
|
T177 |
16 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
22 |
1 |
|
|
T40 |
13 |
|
T177 |
9 |
| auto[1] |
18 |
1 |
|
|
T40 |
7 |
|
T177 |
11 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
23 |
1 |
|
|
T40 |
14 |
|
T177 |
9 |
| auto[1] |
17 |
1 |
|
|
T40 |
6 |
|
T177 |
11 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
27 |
1 |
|
|
T40 |
14 |
|
T177 |
13 |
| auto[1] |
13 |
1 |
|
|
T40 |
6 |
|
T177 |
7 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20 |
1 |
|
|
T40 |
10 |
|
T177 |
10 |
| auto[1] |
20 |
1 |
|
|
T40 |
10 |
|
T177 |
10 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
20 |
1 |
|
|
T40 |
9 |
|
T177 |
11 |
| auto[1] |
20 |
1 |
|
|
T40 |
11 |
|
T177 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
15 |
1 |
|
|
T40 |
5 |
|
T177 |
10 |
| auto[1] |
25 |
1 |
|
|
T40 |
15 |
|
T177 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17 |
1 |
|
|
T40 |
7 |
|
T177 |
10 |
| auto[1] |
23 |
1 |
|
|
T40 |
13 |
|
T177 |
10 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
17 |
1 |
|
|
T40 |
9 |
|
T177 |
8 |
| auto[1] |
23 |
1 |
|
|
T40 |
11 |
|
T177 |
12 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
8 |
1 |
|
|
T40 |
5 |
|
T177 |
3 |
| auto[0] |
auto[1] |
13 |
1 |
|
|
T40 |
6 |
|
T177 |
7 |
| auto[1] |
auto[0] |
10 |
1 |
|
|
T40 |
4 |
|
T177 |
6 |
| auto[1] |
auto[1] |
9 |
1 |
|
|
T40 |
5 |
|
T177 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
7 |
1 |
|
|
T40 |
5 |
|
T177 |
2 |
| auto[0] |
auto[1] |
5 |
1 |
|
|
T40 |
3 |
|
T177 |
2 |
| auto[1] |
auto[0] |
18 |
1 |
|
|
T40 |
7 |
|
T177 |
11 |
| auto[1] |
auto[1] |
10 |
1 |
|
|
T40 |
5 |
|
T177 |
5 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
11 |
1 |
|
|
T40 |
8 |
|
T177 |
3 |
| auto[0] |
auto[1] |
11 |
1 |
|
|
T40 |
5 |
|
T177 |
6 |
| auto[1] |
auto[0] |
8 |
1 |
|
|
T40 |
5 |
|
T177 |
3 |
| auto[1] |
auto[1] |
10 |
1 |
|
|
T40 |
2 |
|
T177 |
8 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
8 |
1 |
|
|
T40 |
5 |
|
T177 |
3 |
| auto[0] |
auto[1] |
15 |
1 |
|
|
T40 |
9 |
|
T177 |
6 |
| auto[1] |
auto[0] |
4 |
1 |
|
|
T40 |
1 |
|
T177 |
3 |
| auto[1] |
auto[1] |
13 |
1 |
|
|
T40 |
5 |
|
T177 |
8 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
15 |
1 |
|
|
T40 |
9 |
|
T177 |
6 |
| auto[0] |
auto[1] |
12 |
1 |
|
|
T40 |
5 |
|
T177 |
7 |
| auto[1] |
auto[0] |
2 |
1 |
|
|
T40 |
2 |
|
- |
- |
| auto[1] |
auto[1] |
11 |
1 |
|
|
T40 |
4 |
|
T177 |
7 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
13 |
1 |
|
|
T40 |
6 |
|
T177 |
7 |
| auto[0] |
auto[1] |
7 |
1 |
|
|
T40 |
4 |
|
T177 |
3 |
| auto[1] |
auto[0] |
7 |
1 |
|
|
T40 |
3 |
|
T177 |
4 |
| auto[1] |
auto[1] |
13 |
1 |
|
|
T40 |
7 |
|
T177 |
6 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
8 |
1 |
|
|
T40 |
4 |
|
T177 |
4 |
| auto[0] |
auto[1] |
7 |
1 |
|
|
T40 |
1 |
|
T177 |
6 |
| auto[1] |
auto[0] |
18 |
1 |
|
|
T40 |
11 |
|
T177 |
7 |
| auto[1] |
auto[1] |
7 |
1 |
|
|
T40 |
4 |
|
T177 |
3 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
5 |
1 |
|
|
T40 |
3 |
|
T177 |
2 |
| auto[0] |
auto[1] |
12 |
1 |
|
|
T40 |
4 |
|
T177 |
8 |
| auto[1] |
auto[0] |
13 |
1 |
|
|
T40 |
8 |
|
T177 |
5 |
| auto[1] |
auto[1] |
10 |
1 |
|
|
T40 |
5 |
|
T177 |
5 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
4 |
1 |
|
|
T40 |
1 |
|
T177 |
3 |
| auto[0] |
auto[1] |
9 |
1 |
|
|
T40 |
6 |
|
T177 |
3 |
| auto[1] |
auto[0] |
12 |
1 |
|
|
T40 |
5 |
|
T177 |
7 |
| auto[1] |
auto[1] |
15 |
1 |
|
|
T40 |
8 |
|
T177 |
7 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
19 |
1 |
|
|
T40 |
8 |
|
T177 |
11 |
| auto[1] |
auto[1] |
21 |
1 |
|
|
T40 |
12 |
|
T177 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
6 |
1 |
|
|
T40 |
2 |
|
T177 |
4 |
| auto[0] |
auto[1] |
14 |
1 |
|
|
T40 |
7 |
|
T177 |
7 |
| auto[1] |
auto[0] |
8 |
1 |
|
|
T40 |
6 |
|
T177 |
2 |
| auto[1] |
auto[1] |
12 |
1 |
|
|
T40 |
5 |
|
T177 |
7 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
17 |
1 |
|
|
T40 |
9 |
|
T177 |
8 |
| auto[1] |
auto[1] |
23 |
1 |
|
|
T40 |
11 |
|
T177 |
12 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |