Unified Coverage Report :: Group :: tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_combo_precondition_det_cg

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_combo_precondition_det_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	83.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_precondition_det_cg1	66.67	1	100	1	64	64
sysrst_ctrl_combo_precondition_det_cg2	66.67	1	100	1	64	64
sysrst_ctrl_combo_precondition_det_cg0	100.00	1	100	1	64	64
sysrst_ctrl_combo_precondition_det_cg3	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_precondition_det_cg1

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.67	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_precondition_det_cg1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	1	2	66.67

Variables for Group Instance sysrst_ctrl_combo_precondition_det_cg1

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_precondition_timer	3	1	2	66.67	100	1	1	0

---

Group Instance : sysrst_ctrl_combo_precondition_det_cg2

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
66.67	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_precondition_det_cg2

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	1	2	66.67

Variables for Group Instance sysrst_ctrl_combo_precondition_det_cg2

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_precondition_timer	3	1	2	66.67	100	1	1	0

---

Group Instance : sysrst_ctrl_combo_precondition_det_cg0

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_precondition_det_cg0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance sysrst_ctrl_combo_precondition_det_cg0

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_precondition_timer	3	0	3	100.00	100	1	1	0

---

Group Instance : sysrst_ctrl_combo_precondition_det_cg3

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_precondition_det_cg3

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	3	0	3	100.00

Variables for Group Instance sysrst_ctrl_combo_precondition_det_cg3

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_precondition_timer	3	0	3	100.00	100	1	1	0

Summary for Variable cp_precondition_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_precondition_timer

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
max_range	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mid_range

15

1

T261

4

T370

11

-

-

min_range

373

1

T15

13

T35

3

T36

5

Summary for Variable cp_precondition_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_precondition_timer

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
mid_range	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

max_range

13

1

T87

6

T103

1

T361

5

min_range

377

1

T15

13

T35

3

T36

5

Summary for Variable cp_precondition_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_precondition_timer

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_range	12	1			T379	5		T383	7		-	-
mid_range	1	1			T276	1		-	-		-	-
min_range	383	1			T15	13		T35	3		T36	5

Summary for Variable cp_precondition_timer

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_precondition_timer

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
max_range	12	1			T394	1		T362	11		-	-
mid_range	6	1			T278	6		-	-		-	-
min_range	378	1			T15	13		T35	3		T36	5