Unified Coverage Report :: Group :: tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg

Group : tb.dut.u_sysrst_ctrl_cov_if::sysrst_ctrl_key_intr_status_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_cov_0/sysrst_ctrl_cov_if.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_key_intr_status_cg	100.00	1	100	1	64	64

---

Group Instance : sysrst_ctrl_key_intr_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_key_intr_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	28	0	28	100.00

Variables for Group Instance sysrst_ctrl_key_intr_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_h2l	2	0	2	100.00	100	1	1	2
cp_ac_present_l2h	2	0	2	100.00	100	1	1	2
cp_ec_rst_l_h2l	2	0	2	100.00	100	1	1	2
cp_ec_rst_l_l2h	2	0	2	100.00	100	1	1	2
cp_flash_wp_l_h2l	2	0	2	100.00	100	1	1	2
cp_flash_wp_l_l2h	2	0	2	100.00	100	1	1	2
cp_key0_in_h2l	2	0	2	100.00	100	1	1	2
cp_key0_in_l2h	2	0	2	100.00	100	1	1	2
cp_key1_in_h2l	2	0	2	100.00	100	1	1	2
cp_key1_in_l2h	2	0	2	100.00	100	1	1	2
cp_key2_in_h2l	2	0	2	100.00	100	1	1	2
cp_key2_in_l2h	2	0	2	100.00	100	1	1	2
cp_pwrb_h2l	2	0	2	100.00	100	1	1	2
cp_pwrb_l2h	2	0	2	100.00	100	1	1	2

Summary for Variable cp_ac_present_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

995

1

T3

6

T10

7

T31

6

auto[1]

111

1

T3

2

T31

2

T47

2

---

Summary for Variable cp_ac_present_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

964

1

T3

5

T10

5

T31

4

auto[1]

142

1

T3

3

T10

2

T31

4

---

Summary for Variable cp_ec_rst_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ec_rst_l_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

971

1

T3

6

T10

7

T31

8

auto[1]

135

1

T3

2

T48

2

T49

3

---

Summary for Variable cp_ec_rst_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ec_rst_l_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

995

1

T3

7

T10

7

T31

6

auto[1]

111

1

T3

1

T31

2

T43

1

---

Summary for Variable cp_flash_wp_l_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_flash_wp_l_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

979

1

T3

6

T10

7

T31

8

auto[1]

127

1

T3

2

T45

2

T47

2

---

Summary for Variable cp_flash_wp_l_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_flash_wp_l_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1006

1

T3

6

T10

6

T31

7

auto[1]

100

1

T3

2

T10

1

T31

1

---

Summary for Variable cp_key0_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T3

5

T10

4

T31

6

auto[1]

110

1

T3

3

T10

3

T31

2

---

Summary for Variable cp_key0_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

988

1

T3

4

T10

7

T31

8

auto[1]

118

1

T3

4

T47

2

T46

1

---

Summary for Variable cp_key1_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1003

1

T3

8

T10

5

T31

8

auto[1]

103

1

T10

2

T45

1

T43

3

---

Summary for Variable cp_key1_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

979

1

T3

8

T10

5

T31

4

auto[1]

127

1

T10

2

T31

4

T45

2

---

Summary for Variable cp_key2_in_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

979

1

T3

8

T10

7

T31

5

auto[1]

127

1

T31

3

T45

2

T47

1

---

Summary for Variable cp_key2_in_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

965

1

T3

4

T10

5

T31

6

auto[1]

141

1

T3

4

T10

2

T31

2

---

Summary for Variable cp_pwrb_h2l

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_h2l

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

996

1

T3

5

T10

4

T31

6

auto[1]

110

1

T3

3

T10

3

T31

2

---

Summary for Variable cp_pwrb_l2h

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_l2h

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

958

1

T3

4

T10

4

T31

8

auto[1]

148

1

T3

4

T10

3

T45

3