Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2015

1

T1

22

T15

60

T2

7

auto[1]

695

1

T1

9

T15

20

T2

3

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2081

1

T1

31

T15

80

T2

6

auto[1]

629

1

T2

4

T7

7

T9

7

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2088

1

T1

20

T15

40

T2

3

auto[1]

622

1

T1

11

T15

40

T2

7

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2096

1

T1

20

T15

80

T2

4

auto[1]

614

1

T1

11

T2

6

T7

12

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2501

1

T1

31

T15

80

T2

10

auto[1]

209

1

T36

4

T51

8

T87

4

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2471

1

T1

31

T15

80

T2

10

auto[1]

239

1

T35

3

T36

4

T51

22

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2479

1

T1

31

T15

80

T2

10

auto[1]

231

1

T53

4

T254

3

T257

11

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2455

1

T1

31

T15

40

T2

10

auto[1]

255

1

T15

40

T35

7

T51

4

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2533

1

T1

31

T15

80

T2

10

auto[1]

177

1

T35

3

T254

3

T258

13

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2026

1

T1

31

T15

80

T2

6

auto[1]

684

1

T2

4

T7

3

T54

4

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	*	--	--	2
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

865

1

T1

31

T2

10

T7

14

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

66

1

T257

7

T262

5

T263

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T258

13

T361

4

T358

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

13

1

T262

4

T278

5

T367

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

143

1

T15

40

T35

4

T257

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

22

1

T51

3

T359

2

T368

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

20

1

T369

1

T370

4

T371

8

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

5

1

T372

3

T363

2

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

90

1

T257

6

T261

2

T263

10

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

31

1

T258

6

T373

2

T369

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

23

1

T254

3

T374

9

T358

5

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

2

1

T270

1

T375

1

-

-

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

26

1

T257

5

T376

1

T377

5

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

105

1

T51

14

T52

2

T85

9

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

26

1

T36

4

T51

2

T87

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

15

1

T374

7

T372

5

T378

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

8

1

T379

3

T366

3

T368

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

6

1

T52

2

T364

2

T372

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

8

1

T35

3

T380

1

T381

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

23

1

T374

9

T351

1

T379

7

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

9

1

T382

2

T383

1

T363

6

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

5

1

T379

5

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

3

1

T384

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

1

1

T385

1

-

-

-

-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

138

1

T1

9

T12

13

T51

7

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

81

1

T87

4

T129

12

T262

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

80

1

T54

4

T269

5

T59

4

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

134

1

T1

11

T7

7

T42

11

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

40

1

T2

3

T51

7

T44

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

90

1

T85

9

T59

4

T189

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

26

1

T128

4

T255

2

T279

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

111

1

T1

11

T15

20

T35

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

62

1

T15

20

T261

2

T329

6

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

65

1

T36

4

T126

7

T52

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

23

1

T13

3

T52

1

T59

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

59

1

T2

3

T52

2

T167

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

34

1

T316

1

T361

4

T374

7

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

48

1

T12

1

T51

2

T269

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

17

1

T126

4

T44

1

T115

2

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

114

1

T12

12

T257

8

T158

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

108

1

T42

9

T257

5

T261

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

62

1

T9

4

T279

4

T272

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

30

1

T9

2

T42

1

T350

3

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

42

1

T7

4

T263

7

T386

5

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

23

1

T257

6

T237

1

T365

6

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

25

1

T257

7

T316

2

T361

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

7

1

T9

1

T350

1

T267

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

54

1

T31

6

T51

3

T59

5

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

28

1

T13

4

T129

2

T116

8

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

41

1

T2

4

T128

2

T44

1

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

9

1

T7

2

T35

4

T249

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

14

1

T139

1

T271

1

T352

5

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

4

1

T12

2

T59

1

T213

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

5

1

T126

1

T316

1

T387

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

2

1

T7

1

T388

1

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded