Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1186

1

T6

9

T19

8

T20

8

auto[1]

1132

1

T6

11

T19

12

T20

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

547

1

T6

5

T19

6

T20

5

from_0to1

550

1

T6

4

T19

7

T20

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1179

1

T6

13

T19

10

T20

11

auto[1]

1139

1

T6

7

T19

10

T20

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1153

1

T6

10

T19

8

T20

11

auto[1]

1165

1

T6

10

T19

12

T20

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T6

1

T20

1

T301

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T19

1

T177

1

T140

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T6

1

T177

2

T167

1

auto[0]

from_1to0

auto[1]

auto[1]

77

1

T40

2

T81

2

T177

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T6

1

T19

2

T40

1

auto[0]

from_0to1

auto[0]

auto[1]

90

1

T19

1

T20

2

T40

1

auto[0]

from_0to1

auto[1]

auto[0]

71

1

T40

2

T140

1

T398

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T6

1

T19

1

T140

1

auto[1]

from_1to0

auto[0]

auto[0]

62

1

T6

2

T19

1

T20

1

auto[1]

from_1to0

auto[0]

auto[1]

75

1

T40

2

T301

1

T140

1

auto[1]

from_1to0

auto[1]

auto[0]

75

1

T19

2

T20

2

T140

2

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T6

1

T19

2

T20

1

auto[1]

from_0to1

auto[0]

auto[0]

69

1

T19

1

T40

1

T177

3

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T6

2

T19

1

T81

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T20

2

T177

1

T140

3

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T19

1

T20

1

T81

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1165

1

T6

7

T19

9

T20

12

auto[1]

1153

1

T6

13

T19

11

T20

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

555

1

T6

4

T19

7

T20

5

from_0to1

555

1

T6

5

T19

6

T20

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1185

1

T6

9

T19

14

T20

10

auto[1]

1133

1

T6

11

T19

6

T20

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1184

1

T6

10

T19

11

T20

12

auto[1]

1134

1

T6

10

T19

9

T20

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

82

1

T19

1

T20

1

T40

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T19

1

T20

1

T301

1

auto[0]

from_1to0

auto[1]

auto[0]

73

1

T19

2

T81

1

T301

1

auto[0]

from_1to0

auto[1]

auto[1]

68

1

T19

1

T20

1

T140

3

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T6

1

T19

1

T20

1

auto[0]

from_0to1

auto[0]

auto[1]

76

1

T19

1

T20

1

T40

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T20

1

T40

1

T81

1

auto[0]

from_0to1

auto[1]

auto[1]

68

1

T20

1

T140

3

T167

3

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T6

1

T177

2

T167

5

auto[1]

from_1to0

auto[0]

auto[1]

67

1

T19

2

T20

1

T81

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T40

3

T81

1

T177

1

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T6

3

T20

1

T81

3

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T40

1

T81

2

T177

2

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T6

1

T19

2

T40

1

auto[1]

from_0to1

auto[1]

auto[0]

77

1

T6

2

T19

2

T20

1

auto[1]

from_0to1

auto[1]

auto[1]

75

1

T6

1

T20

1

T81

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T6

7

T19

11

T20

8

auto[1]

1163

1

T6

13

T19

9

T20

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

574

1

T6

5

T19

7

T20

4

from_0to1

581

1

T6

5

T19

6

T20

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1184

1

T6

10

T19

12

T20

8

auto[1]

1134

1

T6

10

T19

8

T20

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T6

8

T19

11

T20

13

auto[1]

1163

1

T6

12

T19

9

T20

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

76

1

T6

1

T19

1

T20

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T19

1

T177

1

T140

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T6

1

T40

1

T301

1

auto[0]

from_1to0

auto[1]

auto[1]

86

1

T40

1

T81

1

T177

1

auto[0]

from_0to1

auto[0]

auto[0]

76

1

T19

1

T40

2

T81

1

auto[0]

from_0to1

auto[0]

auto[1]

79

1

T6

1

T81

1

T167

3

auto[0]

from_0to1

auto[1]

auto[0]

67

1

T19

1

T20

2

T40

1

auto[0]

from_0to1

auto[1]

auto[1]

66

1

T6

1

T19

2

T20

1

auto[1]

from_1to0

auto[0]

auto[0]

86

1

T6

1

T19

1

T20

2

auto[1]

from_1to0

auto[0]

auto[1]

55

1

T19

2

T177

1

T167

1

auto[1]

from_1to0

auto[1]

auto[0]

86

1

T19

2

T81

2

T167

2

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T6

2

T20

1

T40

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T19

1

T167

1

T94

1

auto[1]

from_0to1

auto[0]

auto[1]

87

1

T6

1

T40

1

T177

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T6

1

T19

1

T20

2

auto[1]

from_0to1

auto[1]

auto[1]

68

1

T6

1

T81

1

T177

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1180

1

T6

10

T19

12

T20

11

auto[1]

1138

1

T6

10

T19

8

T20

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

575

1

T6

3

T19

5

T20

6

from_0to1

569

1

T6

3

T19

6

T20

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1159

1

T6

11

T19

11

T20

11

auto[1]

1159

1

T6

9

T19

9

T20

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1140

1

T6

10

T19

11

T20

12

auto[1]

1178

1

T6

10

T19

9

T20

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

81

1

T6

1

T20

1

T40

2

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T6

1

T19

2

T20

1

auto[0]

from_1to0

auto[1]

auto[0]

74

1

T20

1

T177

1

T167

1

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T6

1

T19

1

T20

1

auto[0]

from_0to1

auto[0]

auto[0]

66

1

T19

2

T20

2

T94

1

auto[0]

from_0to1

auto[0]

auto[1]

84

1

T20

1

T40

2

T81

1

auto[0]

from_0to1

auto[1]

auto[0]

82

1

T19

3

T20

1

T40

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T20

1

T40

1

T177

2

auto[1]

from_1to0

auto[0]

auto[0]

68

1

T19

1

T40

1

T177

1

auto[1]

from_1to0

auto[0]

auto[1]

72

1

T20

1

T81

2

T177

1

auto[1]

from_1to0

auto[1]

auto[0]

74

1

T40

1

T177

1

T140

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T19

1

T20

1

T177

1

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T6

1

T20

1

T167

1

auto[1]

from_0to1

auto[0]

auto[1]

73

1

T6

1

T40

1

T81

1

auto[1]

from_0to1

auto[1]

auto[0]

57

1

T19

1

T81

1

T312

1

auto[1]

from_0to1

auto[1]

auto[1]

78

1

T6

1

T20

1

T40

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1212

1

T6

13

T19

6

T20

9

auto[1]

1106

1

T6

7

T19

14

T20

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

565

1

T6

5

T19

5

T20

4

from_0to1

561

1

T6

5

T19

5

T20

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1180

1

T6

15

T19

10

T20

7

auto[1]

1138

1

T6

5

T19

10

T20

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1160

1

T6

9

T19

10

T20

10

auto[1]

1158

1

T6

11

T19

10

T20

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

70

1

T6

3

T81

1

T177

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T19

1

T20

1

T140

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T177

1

T301

1

T167

2

auto[0]

from_1to0

auto[1]

auto[1]

92

1

T19

1

T177

1

T301

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T40

2

T81

1

T140

1

auto[0]

from_0to1

auto[0]

auto[1]

72

1

T6

2

T81

2

T177

2

auto[0]

from_0to1

auto[1]

auto[0]

79

1

T167

3

T312

2

T398

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T6

1

T20

2

T167

1

auto[1]

from_1to0

auto[0]

auto[0]

63

1

T6

1

T19

2

T81

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T6

1

T20

2

T40

1

auto[1]

from_1to0

auto[1]

auto[0]

61

1

T19

1

T40

3

T301

1

auto[1]

from_1to0

auto[1]

auto[1]

74

1

T20

1

T40

1

T81

2

auto[1]

from_0to1

auto[0]

auto[0]

78

1

T6

1

T19

1

T20

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T19

1

T177

1

T301

1

auto[1]

from_0to1

auto[1]

auto[0]

63

1

T19

2

T20

1

T40

1

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T6

1

T19

1

T301

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1206

1

T6

11

T19

12

T20

13

auto[1]

1112

1

T6

9

T19

8

T20

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

565

1

T6

7

T19

4

T20

6

from_0to1

565

1

T6

6

T19

4

T20

6

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1155

1

T6

11

T19

11

T20

10

auto[1]

1163

1

T6

9

T19

9

T20

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1139

1

T6

8

T19

5

T20

13

auto[1]

1179

1

T6

12

T19

15

T20

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T6

1

T20

2

T81

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T6

1

T19

1

T20

1

auto[0]

from_1to0

auto[1]

auto[0]

81

1

T19

1

T20

1

T40

1

auto[0]

from_1to0

auto[1]

auto[1]

86

1

T6

1

T40

2

T81

1

auto[0]

from_0to1

auto[0]

auto[0]

68

1

T19

1

T20

2

T81

1

auto[0]

from_0to1

auto[0]

auto[1]

88

1

T6

2

T20

1

T81

1

auto[0]

from_0to1

auto[1]

auto[0]

60

1

T6

1

T20

1

T40

2

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T19

1

T81

1

T177

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T6

1

T20

1

T301

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T6

2

T177

1

T140

1

auto[1]

from_1to0

auto[1]

auto[0]

64

1

T6

1

T40

1

T81

1

auto[1]

from_1to0

auto[1]

auto[1]

76

1

T19

2

T20

1

T40

1

auto[1]

from_0to1

auto[0]

auto[0]

72

1

T20

1

T40

1

T301

1

auto[1]

from_0to1

auto[0]

auto[1]

66

1

T6

1

T19

1

T40

1

auto[1]

from_0to1

auto[1]

auto[0]

68

1

T6

1

T20

1

T40

2

auto[1]

from_0to1

auto[1]

auto[1]

80

1

T6

1

T19

1

T177

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1141

1

T6

13

T19

13

T20

13

auto[1]

1177

1

T6

7

T19

7

T20

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

564

1

T6

5

T19

5

T20

6

from_0to1

558

1

T6

4

T19

5

T20

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1128

1

T6

7

T19

9

T20

10

auto[1]

1190

1

T6

13

T19

11

T20

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1151

1

T6

11

T19

13

T20

10

auto[1]

1167

1

T6

9

T19

7

T20

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

48

1

T6

1

T19

1

T20

1

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T6

1

T20

1

T81

1

auto[0]

from_1to0

auto[1]

auto[0]

78

1

T20

2

T40

2

T140

1

auto[0]

from_1to0

auto[1]

auto[1]

74

1

T6

2

T19

2

T20

1

auto[0]

from_0to1

auto[0]

auto[0]

69

1

T19

1

T177

1

T167

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T20

2

T81

3

T301

1

auto[0]

from_0to1

auto[1]

auto[0]

77

1

T6

1

T19

2

T20

1

auto[0]

from_0to1

auto[1]

auto[1]

74

1

T6

2

T19

1

T40

1

auto[1]

from_1to0

auto[0]

auto[0]

71

1

T19

1

T81

1

T177

1

auto[1]

from_1to0

auto[0]

auto[1]

78

1

T40

1

T81

1

T301

1

auto[1]

from_1to0

auto[1]

auto[0]

76

1

T6

1

T177

3

T167

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T19

1

T20

1

T167

4

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T19

1

T40

1

T140

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T81

1

T177

1

T167

4

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T6

1

T20

1

T40

1

auto[1]

from_0to1

auto[1]

auto[1]

65

1

T20

1

T301

1

T140

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1138

1

T6

12

T19

15

T20

8

auto[1]

1180

1

T6

8

T19

5

T20

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

555

1

T6

5

T19

5

T20

4

from_0to1

553

1

T6

5

T19

4

T20

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1161

1

T6

7

T19

11

T20

14

auto[1]

1157

1

T6

13

T19

9

T20

6

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1190

1

T6

15

T19

12

T20

11

auto[1]

1128

1

T6

5

T19

8

T20

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

72

1

T6

1

T177

1

T140

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T19

4

T20

1

T40

1

auto[0]

from_1to0

auto[1]

auto[0]

71

1

T6

1

T81

2

T301

1

auto[0]

from_1to0

auto[1]

auto[1]

59

1

T20

1

T40

1

T81

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T19

1

T40

1

T177

1

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T19

1

T301

2

T140

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T6

1

T19

1

T81

1

auto[0]

from_0to1

auto[1]

auto[1]

73

1

T6

1

T20

1

T81

1

auto[1]

from_1to0

auto[0]

auto[0]

70

1

T6

1

T19

1

T40

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T20

2

T398

1

T399

1

auto[1]

from_1to0

auto[1]

auto[0]

81

1

T6

1

T81

3

T140

2

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T6

1

T40

1

T177

1

auto[1]

from_0to1

auto[0]

auto[0]

77

1

T20

2

T40

2

T81

1

auto[1]

from_0to1

auto[0]

auto[1]

70

1

T6

1

T20

1

T81

1

auto[1]

from_0to1

auto[1]

auto[0]

56

1

T6

1

T40

1

T177

1

auto[1]

from_0to1

auto[1]

auto[1]

71

1

T6

1

T19

1

T40

1