Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	152640	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

117161

1

T4

26

T5

16

T6

43

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	138424	1			T4	22		T5	35		T6	62
values[0x0]	64985	1			T4	16		T6	28		T23	1
values[0x1]	66392	1			T4	6		T5	1		T6	33

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	123833	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

145968

1

T4

26

T5

17

T6

58

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	992	1			T4	2		T6	1		T1	3
valid_sources[0x01]	960	1			T1	3		T15	2		T20	1
valid_sources[0x02]	846	1			T4	1		T1	5		T15	4
valid_sources[0x03]	1098	1			T6	2		T1	5		T15	5
valid_sources[0x04]	1238	1			T6	1		T25	2		T1	1
valid_sources[0x05]	1018	1			T1	3		T15	6		T30	4
valid_sources[0x06]	948	1			T6	1		T15	2		T19	2
valid_sources[0x07]	1240	1			T15	5		T30	1		T7	3
valid_sources[0x08]	811	1			T1	2		T15	3		T30	1
valid_sources[0x09]	998	1			T15	6		T19	1		T30	2
valid_sources[0x0a]	952	1			T6	2		T1	4		T15	2
valid_sources[0x0b]	1005	1			T1	2		T15	5		T20	1
valid_sources[0x0c]	1648	1			T4	1		T6	1		T15	3
valid_sources[0x0d]	933	1			T4	4		T1	4		T74	1
valid_sources[0x0e]	835	1			T6	1		T1	2		T15	6
valid_sources[0x0f]	839	1			T1	3		T15	2		T20	1
valid_sources[0x10]	881	1			T6	7		T1	4		T15	11
valid_sources[0x11]	870	1			T1	3		T15	7		T3	1
valid_sources[0x12]	998	1			T1	3		T15	5		T19	1
valid_sources[0x13]	1032	1			T1	3		T15	10		T22	4
valid_sources[0x14]	820	1			T15	5		T40	10		T7	1
valid_sources[0x15]	1072	1			T1	1		T15	2		T20	2
valid_sources[0x16]	934	1			T1	1		T15	6		T7	4
valid_sources[0x17]	959	1			T1	1		T15	2		T20	1
valid_sources[0x18]	781	1			T1	2		T15	2		T20	1
valid_sources[0x19]	755	1			T1	2		T15	6		T30	3
valid_sources[0x1a]	1074	1			T1	1		T15	5		T7	2
valid_sources[0x1b]	832	1			T6	1		T1	1		T15	7
valid_sources[0x1c]	793	1			T1	2		T15	6		T19	2
valid_sources[0x1d]	839	1			T1	2		T15	3		T20	1
valid_sources[0x1e]	937	1			T6	4		T1	3		T15	5
valid_sources[0x1f]	930	1			T6	1		T15	3		T7	3
valid_sources[0x20]	882	1			T1	3		T15	4		T20	1
valid_sources[0x21]	926	1			T1	2		T15	10		T21	1
valid_sources[0x22]	1414	1			T1	1		T15	4		T20	2
valid_sources[0x23]	809	1			T1	2		T15	4		T30	1
valid_sources[0x24]	1085	1			T1	1		T15	7		T30	1
valid_sources[0x25]	951	1			T1	2		T15	5		T20	1
valid_sources[0x26]	975	1			T1	4		T15	5		T7	2
valid_sources[0x27]	961	1			T6	1		T1	1		T15	3
valid_sources[0x28]	796	1			T4	1		T1	1		T15	4
valid_sources[0x29]	1134	1			T25	3		T15	9		T7	2
valid_sources[0x2a]	925	1			T1	4		T15	7		T20	1
valid_sources[0x2b]	1168	1			T6	2		T1	6		T15	5
valid_sources[0x2c]	955	1			T1	3		T15	3		T19	2
valid_sources[0x2d]	894	1			T1	1		T15	5		T30	1
valid_sources[0x2e]	1552	1			T6	2		T24	6		T1	2
valid_sources[0x2f]	868	1			T6	3		T1	2		T15	9
valid_sources[0x30]	894	1			T6	1		T15	1		T30	4
valid_sources[0x31]	1446	1			T1	2		T15	5		T21	1
valid_sources[0x32]	930	1			T6	1		T20	1		T30	2
valid_sources[0x33]	1013	1			T15	4		T20	1		T30	2
valid_sources[0x34]	1045	1			T1	1		T15	1		T30	1
valid_sources[0x35]	805	1			T1	2		T15	3		T20	2
valid_sources[0x36]	842	1			T6	1		T1	1		T15	4
valid_sources[0x37]	876	1			T15	4		T20	1		T7	3
valid_sources[0x38]	1007	1			T1	4		T15	2		T20	2
valid_sources[0x39]	2814	1			T6	1		T15	4		T20	1
valid_sources[0x3a]	1010	1			T1	4		T15	9		T20	1
valid_sources[0x3b]	883	1			T23	2		T1	2		T15	5
valid_sources[0x3c]	820	1			T1	1		T14	1		T15	3
valid_sources[0x3d]	852	1			T1	5		T15	2		T30	3
valid_sources[0x3e]	989	1			T1	3		T15	8		T30	1
valid_sources[0x3f]	924	1			T1	6		T15	5		T20	1
valid_sources[0x40]	2068	1			T1	2		T15	4		T7	3
valid_sources[0x41]	1700	1			T1	2		T15	4		T30	3
valid_sources[0x42]	869	1			T1	5		T15	7		T20	1
valid_sources[0x43]	938	1			T1	5		T15	2		T19	1
valid_sources[0x44]	1206	1			T1	3		T15	5		T20	1
valid_sources[0x45]	924	1			T1	4		T15	8		T19	1
valid_sources[0x46]	876	1			T1	1		T15	6		T7	1
valid_sources[0x47]	892	1			T4	4		T1	7		T15	1
valid_sources[0x48]	800	1			T1	2		T15	5		T19	1
valid_sources[0x49]	897	1			T1	2		T15	6		T19	1
valid_sources[0x4a]	1077	1			T6	1		T1	8		T15	6
valid_sources[0x4b]	704	1			T1	1		T15	1		T20	1
valid_sources[0x4c]	998	1			T6	1		T1	1		T15	5
valid_sources[0x4d]	2324	1			T1	5		T15	3		T20	1
valid_sources[0x4e]	957	1			T6	1		T1	8		T15	3
valid_sources[0x4f]	1628	1			T1	3		T15	6		T20	1
valid_sources[0x50]	1028	1			T6	1		T1	2		T15	5
valid_sources[0x51]	965	1			T5	36		T6	2		T1	2
valid_sources[0x52]	687	1			T4	2		T1	7		T15	6
valid_sources[0x53]	883	1			T1	4		T15	7		T20	1
valid_sources[0x54]	932	1			T6	1		T1	2		T15	6
valid_sources[0x55]	1105	1			T6	1		T1	4		T15	5
valid_sources[0x56]	1662	1			T1	6		T15	3		T30	1
valid_sources[0x57]	923	1			T6	1		T1	4		T15	10
valid_sources[0x58]	1297	1			T1	3		T15	4		T19	2
valid_sources[0x59]	774	1			T1	3		T15	8		T30	1
valid_sources[0x5a]	880	1			T4	1		T15	2		T19	1
valid_sources[0x5b]	822	1			T1	1		T15	5		T17	1
valid_sources[0x5c]	1013	1			T6	2		T1	3		T15	2
valid_sources[0x5d]	1375	1			T6	2		T25	1		T1	3
valid_sources[0x5e]	1671	1			T1	5		T15	3		T30	4
valid_sources[0x5f]	917	1			T6	1		T1	1		T15	5
valid_sources[0x60]	772	1			T1	2		T15	3		T20	1
valid_sources[0x61]	1434	1			T1	5		T15	10		T19	1
valid_sources[0x62]	898	1			T1	1		T15	4		T20	1
valid_sources[0x63]	1055	1			T1	4		T15	3		T20	2
valid_sources[0x64]	810	1			T4	3		T1	4		T15	7
valid_sources[0x65]	1185	1			T4	5		T1	1		T15	3
valid_sources[0x66]	927	1			T1	1		T15	7		T19	1
valid_sources[0x67]	2249	1			T1	3		T15	2		T30	1
valid_sources[0x68]	1087	1			T1	3		T15	4		T30	1
valid_sources[0x69]	997	1			T1	1		T15	3		T7	1
valid_sources[0x6a]	989	1			T6	1		T1	10		T15	6
valid_sources[0x6b]	790	1			T1	2		T15	2		T20	2
valid_sources[0x6c]	912	1			T1	3		T15	2		T20	2
valid_sources[0x6d]	878	1			T6	1		T1	9		T15	2
valid_sources[0x6e]	958	1			T1	1		T15	4		T19	2
valid_sources[0x6f]	902	1			T1	2		T15	9		T19	1
valid_sources[0x70]	805	1			T1	2		T15	7		T21	2
valid_sources[0x71]	1227	1			T1	3		T15	3		T74	1
valid_sources[0x72]	783	1			T6	1		T1	2		T15	2
valid_sources[0x73]	805	1			T1	3		T15	4		T7	1
valid_sources[0x74]	989	1			T1	1		T15	8		T20	1
valid_sources[0x75]	1188	1			T1	3		T15	3		T19	1
valid_sources[0x76]	838	1			T1	1		T15	11		T20	1
valid_sources[0x77]	968	1			T4	2		T1	3		T15	2
valid_sources[0x78]	918	1			T1	5		T15	11		T84	3
valid_sources[0x79]	1195	1			T1	3		T14	1		T15	7
valid_sources[0x7a]	1010	1			T1	8		T15	5		T30	3
valid_sources[0x7b]	969	1			T23	1		T1	4		T15	3
valid_sources[0x7c]	921	1			T1	4		T15	5		T19	2
valid_sources[0x7d]	996	1			T1	4		T15	4		T30	1
valid_sources[0x7e]	1399	1			T6	1		T1	6		T15	4
valid_sources[0x7f]	1039	1			T4	3		T1	2		T15	6
valid_sources[0x80]	981	1			T1	1		T15	4		T19	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

63318

1

T4

13

T5

16

T6

26

values[0x0]

all_enables

biggest_size

31606

1

T4

11

T6

12

T25

3

values[0x1]

all_enables

biggest_size

22237

1

T4

2

T6

5

T24

1