Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1224719374	11129	0	0
auto_block_debounce_ctl_rd_A	1224719374	1782	0	0
auto_block_out_ctl_rd_A	1224719374	2309	0	0
com_det_ctl_0_rd_A	1224719374	3647	0	0
com_det_ctl_1_rd_A	1224719374	3770	0	0
com_det_ctl_2_rd_A	1224719374	3803	0	0
com_det_ctl_3_rd_A	1224719374	3759	0	0
com_out_ctl_0_rd_A	1224719374	4094	0	0
com_out_ctl_1_rd_A	1224719374	4216	0	0
com_out_ctl_2_rd_A	1224719374	4304	0	0
com_out_ctl_3_rd_A	1224719374	4394	0	0
com_pre_det_ctl_0_rd_A	1224719374	1141	0	0
com_pre_det_ctl_1_rd_A	1224719374	1291	0	0
com_pre_det_ctl_2_rd_A	1224719374	1073	0	0
com_pre_det_ctl_3_rd_A	1224719374	1267	0	0
com_pre_sel_ctl_0_rd_A	1224719374	4401	0	0
com_pre_sel_ctl_1_rd_A	1224719374	4437	0	0
com_pre_sel_ctl_2_rd_A	1224719374	4483	0	0
com_pre_sel_ctl_3_rd_A	1224719374	4589	0	0
com_sel_ctl_0_rd_A	1224719374	4332	0	0
com_sel_ctl_1_rd_A	1224719374	4268	0	0
com_sel_ctl_2_rd_A	1224719374	4397	0	0
com_sel_ctl_3_rd_A	1224719374	4435	0	0
ec_rst_ctl_rd_A	1224719374	2595	0	0
intr_enable_rd_A	1224719374	1848	0	0
key_intr_ctl_rd_A	1224719374	3475	0	0
key_intr_debounce_ctl_rd_A	1224719374	1165	0	0
key_invert_ctl_rd_A	1224719374	4597	0	0
pin_allowed_ctl_rd_A	1224719374	4987	0	0
pin_out_ctl_rd_A	1224719374	3971	0	0
pin_out_value_rd_A	1224719374	3658	0	0
regwen_rd_A	1224719374	1442	0	0
ulp_ac_debounce_ctl_rd_A	1224719374	1458	0	0
ulp_ctl_rd_A	1224719374	1448	0	0
ulp_lid_debounce_ctl_rd_A	1224719374	1402	0	0
ulp_pwrb_debounce_ctl_rd_A	1224719374	1346	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	11129	0	0
T43	236643	0	0	0
T46	299756	9	0	0
T47	227294	7	0	0
T52	133206	0	0	0
T53	163274	0	0	0
T69	219679	0	0	0
T80	0	11	0	0
T82	263727	0	0	0
T94	0	16	0	0
T115	0	4	0	0
T131	0	7	0	0
T155	0	16	0	0
T158	0	8	0	0
T167	0	6	0	0
T171	24894	0	0	0
T269	827273	0	0	0
T300	0	5	0	0
T301	25472	0	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	1782	0	0
T29	54261	0	0	0
T46	0	26	0	0
T56	81623	15	0	0
T57	83188	0	0	0
T80	0	22	0	0
T105	0	12	0	0
T109	0	8	0	0
T131	0	37	0	0
T156	0	9	0	0
T185	0	44	0	0
T214	0	23	0	0
T302	0	8	0	0
T303	106785	0	0	0
T304	48917	0	0	0
T305	115319	0	0	0
T306	359282	0	0	0
T307	205773	0	0	0
T308	167103	0	0	0
T309	130765	0	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	2309	0	0
T29	54261	0	0	0
T46	0	38	0	0
T56	81623	9	0	0
T57	83188	0	0	0
T80	0	13	0	0
T105	0	49	0	0
T109	0	11	0	0
T131	0	38	0	0
T156	0	4	0	0
T185	0	41	0	0
T214	0	10	0	0
T302	0	18	0	0
T303	106785	0	0	0
T304	48917	0	0	0
T305	115319	0	0	0
T306	359282	0	0	0
T307	205773	0	0	0
T308	167103	0	0	0
T309	130765	0	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	3647	0	0
T7	113429	67	0	0
T9	0	74	0	0
T12	0	21	0	0
T31	0	72	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	47	0	0
T41	204976	0	0	0
T46	0	27	0	0
T53	0	45	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	18	0	0
T126	0	50	0	0
T269	0	56	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	3770	0	0
T7	113429	54	0	0
T9	0	53	0	0
T12	0	28	0	0
T31	0	48	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	43	0	0
T41	204976	0	0	0
T46	0	28	0	0
T53	0	32	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	18	0	0
T126	0	74	0	0
T269	0	66	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	3803	0	0
T7	113429	85	0	0
T9	0	87	0	0
T12	0	49	0	0
T31	0	68	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	55	0	0
T41	204976	0	0	0
T46	0	35	0	0
T53	0	59	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	15	0	0
T126	0	65	0	0
T269	0	70	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	3759	0	0
T7	113429	90	0	0
T9	0	67	0	0
T12	0	33	0	0
T31	0	79	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	43	0	0
T41	204976	0	0	0
T46	0	24	0	0
T53	0	39	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	9	0	0
T126	0	87	0	0
T269	0	62	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4094	0	0
T7	113429	69	0	0
T9	0	51	0	0
T12	0	38	0	0
T31	0	36	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	40	0	0
T41	204976	0	0	0
T46	0	34	0	0
T53	0	31	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	9	0	0
T126	0	64	0	0
T269	0	47	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4216	0	0
T7	113429	73	0	0
T9	0	74	0	0
T12	0	45	0	0
T31	0	80	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	67	0	0
T41	204976	0	0	0
T46	0	35	0	0
T53	0	37	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	16	0	0
T126	0	87	0	0
T269	0	60	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4304	0	0
T7	113429	72	0	0
T9	0	72	0	0
T12	0	39	0	0
T31	0	46	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	67	0	0
T41	204976	0	0	0
T46	0	30	0	0
T53	0	36	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	22	0	0
T126	0	79	0	0
T269	0	67	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4394	0	0
T7	113429	61	0	0
T9	0	89	0	0
T12	0	42	0	0
T31	0	93	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	57	0	0
T41	204976	0	0	0
T46	0	34	0	0
T53	0	45	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	11	0	0
T126	0	97	0	0
T269	0	84	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	1141	0	0
T43	236643	0	0	0
T46	299756	30	0	0
T48	215426	0	0	0
T53	163274	0	0	0
T69	219679	0	0	0
T70	54384	0	0	0
T80	0	20	0	0
T82	263727	0	0	0
T105	0	17	0	0
T119	0	11	0	0
T131	0	14	0	0
T141	0	20	0	0
T163	0	5	0	0
T171	24894	0	0	0
T172	574796	0	0	0
T173	261070	0	0	0
T185	0	42	0	0
T302	0	11	0	0
T310	0	14	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	1291	0	0
T43	236643	0	0	0
T46	299756	27	0	0
T48	215426	0	0	0
T53	163274	0	0	0
T69	219679	0	0	0
T70	54384	0	0	0
T80	0	9	0	0
T82	263727	0	0	0
T105	0	23	0	0
T119	0	10	0	0
T131	0	34	0	0
T141	0	36	0	0
T163	0	12	0	0
T171	24894	0	0	0
T172	574796	0	0	0
T173	261070	0	0	0
T185	0	22	0	0
T302	0	7	0	0
T310	0	19	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	1073	0	0
T43	236643	0	0	0
T46	299756	27	0	0
T48	215426	0	0	0
T53	163274	0	0	0
T69	219679	0	0	0
T70	54384	0	0	0
T80	0	8	0	0
T82	263727	0	0	0
T105	0	26	0	0
T119	0	7	0	0
T131	0	23	0	0
T141	0	25	0	0
T163	0	5	0	0
T171	24894	0	0	0
T172	574796	0	0	0
T173	261070	0	0	0
T185	0	36	0	0
T302	0	5	0	0
T310	0	22	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	1267	0	0
T43	236643	0	0	0
T46	299756	38	0	0
T48	215426	0	0	0
T53	163274	0	0	0
T69	219679	0	0	0
T70	54384	0	0	0
T80	0	13	0	0
T82	263727	0	0	0
T105	0	12	0	0
T119	0	12	0	0
T131	0	27	0	0
T141	0	25	0	0
T163	0	22	0	0
T171	24894	0	0	0
T172	574796	0	0	0
T173	261070	0	0	0
T185	0	53	0	0
T302	0	8	0	0
T310	0	27	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4401	0	0
T7	113429	63	0	0
T9	0	68	0	0
T12	0	51	0	0
T31	0	80	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	65	0	0
T41	204976	0	0	0
T46	0	45	0	0
T53	0	39	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	9	0	0
T126	0	65	0	0
T269	0	75	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4437	0	0
T7	113429	74	0	0
T9	0	53	0	0
T12	0	47	0	0
T31	0	65	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	40	0	0
T41	204976	0	0	0
T46	0	28	0	0
T53	0	32	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	10	0	0
T126	0	64	0	0
T269	0	61	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4483	0	0
T7	113429	89	0	0
T9	0	79	0	0
T12	0	45	0	0
T31	0	59	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	31	0	0
T41	204976	0	0	0
T46	0	37	0	0
T53	0	40	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	11	0	0
T126	0	59	0	0
T269	0	62	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4589	0	0
T7	113429	43	0	0
T9	0	68	0	0
T12	0	25	0	0
T31	0	62	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	53	0	0
T41	204976	0	0	0
T46	0	40	0	0
T53	0	38	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	5	0	0
T126	0	78	0	0
T269	0	60	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4332	0	0
T7	113429	49	0	0
T9	0	75	0	0
T12	0	42	0	0
T31	0	79	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	53	0	0
T41	204976	0	0	0
T46	0	37	0	0
T53	0	42	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	19	0	0
T126	0	72	0	0
T269	0	60	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4268	0	0
T7	113429	66	0	0
T9	0	58	0	0
T12	0	19	0	0
T31	0	80	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	62	0	0
T41	204976	0	0	0
T46	0	42	0	0
T53	0	31	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	7	0	0
T126	0	66	0	0
T269	0	68	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4397	0	0
T7	113429	79	0	0
T9	0	94	0	0
T12	0	40	0	0
T31	0	62	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	33	0	0
T41	204976	0	0	0
T46	0	25	0	0
T53	0	62	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	13	0	0
T126	0	101	0	0
T269	0	80	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4435	0	0
T7	113429	77	0	0
T9	0	82	0	0
T12	0	22	0	0
T31	0	85	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	31	0	0
T41	204976	0	0	0
T46	0	36	0	0
T53	0	42	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	20	0	0
T126	0	82	0	0
T269	0	65	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	2595	0	0
T7	113429	46	0	0
T9	0	13	0	0
T12	0	24	0	0
T31	0	28	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T36	0	20	0	0
T41	204976	0	0	0
T46	0	36	0	0
T53	0	9	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T65	57999	0	0	0
T75	60317	0	0	0
T80	0	21	0	0
T126	0	40	0	0
T269	0	23	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	1848	0	0
T43	236643	0	0	0
T46	299756	76	0	0
T48	215426	0	0	0
T53	163274	0	0	0
T69	219679	0	0	0
T70	54384	0	0	0
T80	0	36	0	0
T82	263727	0	0	0
T105	0	9	0	0
T131	0	43	0	0
T133	0	17	0	0
T141	0	28	0	0
T163	0	17	0	0
T171	24894	0	0	0
T172	574796	0	0	0
T173	261070	0	0	0
T185	0	49	0	0
T302	0	8	0	0
T311	0	7	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	3475	0	0
T36	580372	0	0	0
T43	0	3	0	0
T45	49027	4	0	0
T46	0	34	0	0
T48	0	6	0	0
T50	0	5	0	0
T51	176801	0	0	0
T80	0	8	0	0
T108	217554	0	0	0
T124	120498	0	0	0
T125	47046	0	0	0
T126	107586	0	0	0
T127	227735	0	0	0
T131	0	37	0	0
T152	0	1	0	0
T177	125684	0	0	0
T185	0	39	0	0
T230	0	10	0	0
T259	41149	0	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	1165	0	0
T43	236643	0	0	0
T46	299756	34	0	0
T48	215426	0	0	0
T53	163274	0	0	0
T69	219679	0	0	0
T70	54384	0	0	0
T80	0	14	0	0
T82	263727	0	0	0
T105	0	22	0	0
T119	0	12	0	0
T131	0	29	0	0
T141	0	45	0	0
T163	0	15	0	0
T171	24894	0	0	0
T172	574796	0	0	0
T173	261070	0	0	0
T185	0	26	0	0
T302	0	4	0	0
T310	0	26	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4597	0	0
T7	113429	0	0	0
T32	162879	0	0	0
T33	160872	0	0	0
T41	204976	0	0	0
T46	0	25	0	0
T54	153354	0	0	0
T62	70936	0	0	0
T63	97348	0	0	0
T64	60332	0	0	0
T74	15348	41	0	0
T75	60317	0	0	0
T77	0	86	0	0
T80	0	69	0	0
T131	0	131	0	0
T185	0	28	0	0
T312	0	67	0	0
T313	0	54	0	0
T314	0	57	0	0
T315	0	27	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	4987	0	0
T1	175157	0	0	0
T6	248916	46	0	0
T14	105927	0	0	0
T15	160900	0	0	0
T16	80949	0	0	0
T17	73639	0	0	0
T18	71747	0	0	0
T23	202809	0	0	0
T24	156213	0	0	0
T25	195317	0	0	0
T46	0	38	0	0
T80	0	12	0	0
T131	0	32	0	0
T133	0	27	0	0
T177	0	26	0	0
T185	0	30	0	0
T302	0	8	0	0
T312	0	87	0	0
T316	0	85	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	3971	0	0
T1	175157	0	0	0
T6	248916	28	0	0
T14	105927	0	0	0
T15	160900	0	0	0
T16	80949	0	0	0
T17	73639	0	0	0
T18	71747	0	0	0
T23	202809	0	0	0
T24	156213	0	0	0
T25	195317	0	0	0
T46	0	44	0	0
T80	0	12	0	0
T131	0	33	0	0
T133	0	66	0	0
T177	0	62	0	0
T185	0	38	0	0
T302	0	14	0	0
T312	0	62	0	0
T316	0	67	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	3658	0	0
T1	175157	0	0	0
T6	248916	48	0	0
T14	105927	0	0	0
T15	160900	0	0	0
T16	80949	0	0	0
T17	73639	0	0	0
T18	71747	0	0	0
T23	202809	0	0	0
T24	156213	0	0	0
T25	195317	0	0	0
T46	0	19	0	0
T80	0	18	0	0
T131	0	29	0	0
T133	0	36	0	0
T177	0	50	0	0
T185	0	54	0	0
T302	0	9	0	0
T312	0	62	0	0
T316	0	60	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	1442	0	0
T43	236643	0	0	0
T46	299756	33	0	0
T48	215426	0	0	0
T53	163274	0	0	0
T69	219679	0	0	0
T70	54384	0	0	0
T80	0	17	0	0
T82	263727	0	0	0
T105	0	16	0	0
T119	0	8	0	0
T131	0	26	0	0
T141	0	19	0	0
T163	0	11	0	0
T171	24894	0	0	0
T172	574796	0	0	0
T173	261070	0	0	0
T185	0	26	0	0
T302	0	17	0	0
T310	0	24	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	1458	0	0
T11	220641	0	0	0
T12	479305	0	0	0
T13	829393	0	0	0
T29	0	11	0	0
T34	82057	0	0	0
T35	516638	0	0	0
T42	151166	0	0	0
T46	0	42	0	0
T68	654226	1	0	0
T80	0	16	0	0
T90	0	13	0	0
T91	0	1	0	0
T121	68951	0	0	0
T122	98961	0	0	0
T130	0	9	0	0
T131	0	40	0	0
T132	0	3	0	0
T144	38700	0	0	0
T317	0	9	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	1448	0	0
T11	220641	0	0	0
T12	479305	0	0	0
T13	829393	0	0	0
T29	0	12	0	0
T34	82057	0	0	0
T35	516638	0	0	0
T42	151166	0	0	0
T46	0	39	0	0
T68	654226	8	0	0
T80	0	22	0	0
T90	0	14	0	0
T121	68951	0	0	0
T122	98961	0	0	0
T130	0	3	0	0
T131	0	50	0	0
T132	0	9	0	0
T144	38700	0	0	0
T185	0	41	0	0
T317	0	11	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	1402	0	0
T11	220641	0	0	0
T12	479305	0	0	0
T13	829393	0	0	0
T29	0	21	0	0
T34	82057	0	0	0
T35	516638	0	0	0
T42	151166	0	0	0
T46	0	34	0	0
T68	654226	7	0	0
T80	0	7	0	0
T90	0	8	0	0
T91	0	1	0	0
T121	68951	0	0	0
T122	98961	0	0	0
T130	0	11	0	0
T131	0	34	0	0
T132	0	11	0	0
T144	38700	0	0	0
T317	0	16	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1224719374	1346	0	0
T11	220641	0	0	0
T12	479305	0	0	0
T13	829393	0	0	0
T29	0	3	0	0
T34	82057	0	0	0
T35	516638	0	0	0
T42	151166	0	0	0
T46	0	40	0	0
T68	654226	4	0	0
T80	0	14	0	0
T90	0	10	0	0
T121	68951	0	0	0
T122	98961	0	0	0
T130	0	9	0	0
T131	0	33	0	0
T132	0	11	0	0
T144	38700	0	0	0
T185	0	45	0	0
T317	0	20	0	0