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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.92 98.81 96.71 100.00 96.15 98.30 99.42 89.03


Total test records in report: 915
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T798 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1443715494 Jul 21 06:33:15 PM PDT 24 Jul 21 06:33:22 PM PDT 24 2013646014 ps
T799 /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3173917046 Jul 21 06:33:28 PM PDT 24 Jul 21 06:33:37 PM PDT 24 2008084783 ps
T27 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1803066813 Jul 21 06:33:22 PM PDT 24 Jul 21 06:33:27 PM PDT 24 2120893671 ps
T800 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3473486616 Jul 21 06:33:09 PM PDT 24 Jul 21 06:33:17 PM PDT 24 2010072270 ps
T801 /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.2056590456 Jul 21 06:33:25 PM PDT 24 Jul 21 06:33:32 PM PDT 24 2012173662 ps
T28 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2389779521 Jul 21 06:33:01 PM PDT 24 Jul 21 06:33:06 PM PDT 24 2638057590 ps
T29 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.4016714738 Jul 21 06:33:01 PM PDT 24 Jul 21 06:33:07 PM PDT 24 2163029840 ps
T802 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1051741987 Jul 21 06:33:05 PM PDT 24 Jul 21 06:33:09 PM PDT 24 2062617305 ps
T260 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1493914282 Jul 21 06:33:14 PM PDT 24 Jul 21 06:34:55 PM PDT 24 42396314658 ps
T803 /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.298681707 Jul 21 06:33:27 PM PDT 24 Jul 21 06:33:31 PM PDT 24 2039653598 ps
T804 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1909679807 Jul 21 06:33:15 PM PDT 24 Jul 21 06:33:17 PM PDT 24 2069588868 ps
T805 /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2637116428 Jul 21 06:33:28 PM PDT 24 Jul 21 06:33:33 PM PDT 24 2036067769 ps
T270 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.465081711 Jul 21 06:33:01 PM PDT 24 Jul 21 06:33:09 PM PDT 24 2721755248 ps
T806 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2431332315 Jul 21 06:33:03 PM PDT 24 Jul 21 06:33:12 PM PDT 24 2014250691 ps
T268 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1228899144 Jul 21 06:33:15 PM PDT 24 Jul 21 06:33:23 PM PDT 24 2057886982 ps
T269 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3309832976 Jul 21 06:33:08 PM PDT 24 Jul 21 06:33:13 PM PDT 24 2077209210 ps
T261 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3173324844 Jul 21 06:33:21 PM PDT 24 Jul 21 06:34:47 PM PDT 24 42505870130 ps
T807 /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1561796912 Jul 21 06:33:19 PM PDT 24 Jul 21 06:33:26 PM PDT 24 2012517823 ps
T265 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2010089637 Jul 21 06:33:13 PM PDT 24 Jul 21 06:34:17 PM PDT 24 42512886071 ps
T262 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3843864347 Jul 21 06:33:02 PM PDT 24 Jul 21 06:33:11 PM PDT 24 2034399428 ps
T808 /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.20091030 Jul 21 06:33:28 PM PDT 24 Jul 21 06:33:36 PM PDT 24 2017224483 ps
T316 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1176727056 Jul 21 06:33:06 PM PDT 24 Jul 21 06:33:16 PM PDT 24 6046616913 ps
T266 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1662258159 Jul 21 06:33:21 PM PDT 24 Jul 21 06:33:28 PM PDT 24 2188202393 ps
T809 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3656066004 Jul 21 06:33:21 PM PDT 24 Jul 21 06:33:26 PM PDT 24 2076601440 ps
T17 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4204209015 Jul 21 06:33:19 PM PDT 24 Jul 21 06:33:59 PM PDT 24 8685794180 ps
T280 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3251593852 Jul 21 06:33:20 PM PDT 24 Jul 21 06:33:34 PM PDT 24 22682207064 ps
T267 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.418165094 Jul 21 06:33:04 PM PDT 24 Jul 21 06:33:13 PM PDT 24 2065533434 ps
T810 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3876541104 Jul 21 06:33:00 PM PDT 24 Jul 21 06:33:05 PM PDT 24 2029267021 ps
T276 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1063585892 Jul 21 06:33:03 PM PDT 24 Jul 21 06:33:34 PM PDT 24 42495413591 ps
T281 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.182563541 Jul 21 06:32:56 PM PDT 24 Jul 21 06:33:54 PM PDT 24 22216067131 ps
T329 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2858713180 Jul 21 06:33:03 PM PDT 24 Jul 21 06:33:08 PM PDT 24 2066659673 ps
T811 /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3849938395 Jul 21 06:33:27 PM PDT 24 Jul 21 06:33:32 PM PDT 24 2022788124 ps
T317 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.955227591 Jul 21 06:33:22 PM PDT 24 Jul 21 06:33:31 PM PDT 24 2049478205 ps
T318 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.563451975 Jul 21 06:33:02 PM PDT 24 Jul 21 06:36:30 PM PDT 24 37643069885 ps
T282 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1727428873 Jul 21 06:33:09 PM PDT 24 Jul 21 06:33:43 PM PDT 24 42798185440 ps
T319 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2453928898 Jul 21 06:33:02 PM PDT 24 Jul 21 06:34:03 PM PDT 24 22715254230 ps
T331 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1363717883 Jul 21 06:33:00 PM PDT 24 Jul 21 06:33:06 PM PDT 24 4082396674 ps
T812 /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2141767009 Jul 21 06:33:29 PM PDT 24 Jul 21 06:33:37 PM PDT 24 2012093443 ps
T274 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2532879467 Jul 21 06:33:19 PM PDT 24 Jul 21 06:33:36 PM PDT 24 22397308758 ps
T277 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.3795456937 Jul 21 06:33:20 PM PDT 24 Jul 21 06:33:33 PM PDT 24 22726471502 ps
T284 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1781287653 Jul 21 06:33:01 PM PDT 24 Jul 21 06:33:31 PM PDT 24 42535465440 ps
T813 /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.701300830 Jul 21 06:33:26 PM PDT 24 Jul 21 06:33:30 PM PDT 24 2044964707 ps
T18 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3509435465 Jul 21 06:33:18 PM PDT 24 Jul 21 06:33:32 PM PDT 24 4948245108 ps
T330 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3811330103 Jul 21 06:33:14 PM PDT 24 Jul 21 06:33:17 PM PDT 24 2140105838 ps
T272 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2236465724 Jul 21 06:32:58 PM PDT 24 Jul 21 06:33:03 PM PDT 24 2097140599 ps
T19 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.780209822 Jul 21 06:33:05 PM PDT 24 Jul 21 06:33:11 PM PDT 24 7211498140 ps
T814 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1362988085 Jul 21 06:33:16 PM PDT 24 Jul 21 06:33:21 PM PDT 24 2165253438 ps
T815 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1462739047 Jul 21 06:33:08 PM PDT 24 Jul 21 06:33:13 PM PDT 24 2188487874 ps
T365 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2032309663 Jul 21 06:33:08 PM PDT 24 Jul 21 06:34:11 PM PDT 24 42526791500 ps
T320 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2308357586 Jul 21 06:33:00 PM PDT 24 Jul 21 06:33:05 PM PDT 24 2143773921 ps
T816 /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1244006469 Jul 21 06:33:21 PM PDT 24 Jul 21 06:33:29 PM PDT 24 2009810498 ps
T271 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3891080992 Jul 21 06:33:14 PM PDT 24 Jul 21 06:33:20 PM PDT 24 2047611661 ps
T817 /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2872534085 Jul 21 06:33:28 PM PDT 24 Jul 21 06:33:34 PM PDT 24 2020522120 ps
T273 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2827518604 Jul 21 06:33:07 PM PDT 24 Jul 21 06:33:14 PM PDT 24 2059307967 ps
T321 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3369296340 Jul 21 06:33:24 PM PDT 24 Jul 21 06:33:28 PM PDT 24 2071054791 ps
T278 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.4078187196 Jul 21 06:33:00 PM PDT 24 Jul 21 06:33:08 PM PDT 24 2192271784 ps
T283 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3294441911 Jul 21 06:33:08 PM PDT 24 Jul 21 06:33:25 PM PDT 24 23177303143 ps
T322 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.697153897 Jul 21 06:33:04 PM PDT 24 Jul 21 06:33:46 PM PDT 24 35739671388 ps
T818 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3954663270 Jul 21 06:33:22 PM PDT 24 Jul 21 06:33:27 PM PDT 24 2154051715 ps
T323 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2325473127 Jul 21 06:33:21 PM PDT 24 Jul 21 06:33:26 PM PDT 24 2077113676 ps
T819 /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1208080209 Jul 21 06:33:26 PM PDT 24 Jul 21 06:33:32 PM PDT 24 2011435461 ps
T820 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2252406736 Jul 21 06:33:02 PM PDT 24 Jul 21 06:33:09 PM PDT 24 2697492017 ps
T821 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3965682261 Jul 21 06:33:09 PM PDT 24 Jul 21 06:33:14 PM PDT 24 2075800152 ps
T822 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3056009317 Jul 21 06:32:59 PM PDT 24 Jul 21 06:33:04 PM PDT 24 2552797820 ps
T285 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2051249651 Jul 21 06:33:13 PM PDT 24 Jul 21 06:33:18 PM PDT 24 2085045905 ps
T823 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.4009357940 Jul 21 06:33:21 PM PDT 24 Jul 21 06:33:30 PM PDT 24 2013788803 ps
T824 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3370092739 Jul 21 06:33:20 PM PDT 24 Jul 21 06:33:26 PM PDT 24 2012484189 ps
T825 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2265581257 Jul 21 06:33:07 PM PDT 24 Jul 21 06:33:12 PM PDT 24 2526500453 ps
T826 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2011241446 Jul 21 06:33:14 PM PDT 24 Jul 21 06:33:19 PM PDT 24 2018865548 ps
T827 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.930817601 Jul 21 06:33:20 PM PDT 24 Jul 21 06:33:29 PM PDT 24 2049439245 ps
T828 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3716401335 Jul 21 06:33:21 PM PDT 24 Jul 21 06:33:27 PM PDT 24 2123627459 ps
T829 /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.938709193 Jul 21 06:33:30 PM PDT 24 Jul 21 06:33:38 PM PDT 24 2010482939 ps
T830 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.930343392 Jul 21 06:33:08 PM PDT 24 Jul 21 06:33:18 PM PDT 24 7803095964 ps
T831 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1671052323 Jul 21 06:33:08 PM PDT 24 Jul 21 06:33:14 PM PDT 24 4706451557 ps
T832 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.221678096 Jul 21 06:33:14 PM PDT 24 Jul 21 06:33:32 PM PDT 24 22274847282 ps
T833 /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.760352317 Jul 21 06:33:21 PM PDT 24 Jul 21 06:33:26 PM PDT 24 2052105529 ps
T834 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1877789066 Jul 21 06:33:01 PM PDT 24 Jul 21 06:33:06 PM PDT 24 2045624180 ps
T835 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2332855756 Jul 21 06:33:06 PM PDT 24 Jul 21 06:35:27 PM PDT 24 39497261372 ps
T324 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1412605197 Jul 21 06:33:15 PM PDT 24 Jul 21 06:33:19 PM PDT 24 2113631864 ps
T836 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1111123905 Jul 21 06:33:18 PM PDT 24 Jul 21 06:33:22 PM PDT 24 2047252657 ps
T837 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1049510640 Jul 21 06:33:03 PM PDT 24 Jul 21 06:33:08 PM PDT 24 2106202593 ps
T838 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.4106016006 Jul 21 06:33:07 PM PDT 24 Jul 21 06:33:15 PM PDT 24 2013808503 ps
T327 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.214251563 Jul 21 06:33:09 PM PDT 24 Jul 21 06:33:18 PM PDT 24 2054364175 ps
T839 /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3678671572 Jul 21 06:33:25 PM PDT 24 Jul 21 06:33:30 PM PDT 24 2024138840 ps
T840 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2603747616 Jul 21 06:32:58 PM PDT 24 Jul 21 06:33:02 PM PDT 24 2078036344 ps
T841 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.805744530 Jul 21 06:33:08 PM PDT 24 Jul 21 06:33:15 PM PDT 24 7651277627 ps
T842 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.156679248 Jul 21 06:33:00 PM PDT 24 Jul 21 06:33:05 PM PDT 24 2573767806 ps
T843 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3355442136 Jul 21 06:33:23 PM PDT 24 Jul 21 06:33:28 PM PDT 24 2108449846 ps
T844 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.903747848 Jul 21 06:33:05 PM PDT 24 Jul 21 06:33:14 PM PDT 24 2103144458 ps
T845 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3976346859 Jul 21 06:33:09 PM PDT 24 Jul 21 06:33:14 PM PDT 24 2201774383 ps
T846 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.118395230 Jul 21 06:33:21 PM PDT 24 Jul 21 06:33:29 PM PDT 24 2012683152 ps
T847 /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3617097288 Jul 21 06:33:21 PM PDT 24 Jul 21 06:33:29 PM PDT 24 2008882020 ps
T848 /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.937082812 Jul 21 06:33:28 PM PDT 24 Jul 21 06:33:36 PM PDT 24 2011319049 ps
T849 /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1919130349 Jul 21 06:33:19 PM PDT 24 Jul 21 06:33:25 PM PDT 24 2013687721 ps
T850 /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3455584079 Jul 21 06:33:23 PM PDT 24 Jul 21 06:33:55 PM PDT 24 9081414429 ps
T851 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3821526364 Jul 21 06:33:05 PM PDT 24 Jul 21 06:33:10 PM PDT 24 2020626547 ps
T852 /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3597470832 Jul 21 06:33:29 PM PDT 24 Jul 21 06:33:38 PM PDT 24 2014573849 ps
T853 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2075708509 Jul 21 06:33:22 PM PDT 24 Jul 21 06:33:31 PM PDT 24 4400364543 ps
T854 /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2203499524 Jul 21 06:33:27 PM PDT 24 Jul 21 06:33:31 PM PDT 24 2146677756 ps
T855 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3316951289 Jul 21 06:33:22 PM PDT 24 Jul 21 06:33:36 PM PDT 24 4650242229 ps
T856 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.900293715 Jul 21 06:33:08 PM PDT 24 Jul 21 06:33:14 PM PDT 24 2435045280 ps
T857 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2984268371 Jul 21 06:33:07 PM PDT 24 Jul 21 06:34:05 PM PDT 24 22261875245 ps
T858 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.944991183 Jul 21 06:33:15 PM PDT 24 Jul 21 06:33:18 PM PDT 24 2128887897 ps
T328 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3371607599 Jul 21 06:33:14 PM PDT 24 Jul 21 06:33:18 PM PDT 24 2072872831 ps
T859 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3132110310 Jul 21 06:33:08 PM PDT 24 Jul 21 06:33:17 PM PDT 24 2023553201 ps
T860 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.4071711962 Jul 21 06:33:23 PM PDT 24 Jul 21 06:33:29 PM PDT 24 2023937928 ps
T861 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1905270730 Jul 21 06:33:13 PM PDT 24 Jul 21 06:33:15 PM PDT 24 2581485132 ps
T862 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2993879177 Jul 21 06:33:23 PM PDT 24 Jul 21 06:33:31 PM PDT 24 2061967860 ps
T325 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.1206583858 Jul 21 06:33:00 PM PDT 24 Jul 21 06:33:12 PM PDT 24 2386731988 ps
T863 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2898021433 Jul 21 06:33:13 PM PDT 24 Jul 21 06:33:19 PM PDT 24 2159009116 ps
T864 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2793542634 Jul 21 06:33:06 PM PDT 24 Jul 21 06:33:11 PM PDT 24 4677765059 ps
T326 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3706236947 Jul 21 06:33:01 PM PDT 24 Jul 21 06:33:09 PM PDT 24 3109700507 ps
T865 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1182139985 Jul 21 06:33:06 PM PDT 24 Jul 21 06:33:10 PM PDT 24 2045860236 ps
T866 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2260766079 Jul 21 06:33:14 PM PDT 24 Jul 21 06:33:31 PM PDT 24 22417803055 ps
T867 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3062198702 Jul 21 06:33:03 PM PDT 24 Jul 21 06:33:28 PM PDT 24 8395018196 ps
T868 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2801881286 Jul 21 06:33:05 PM PDT 24 Jul 21 06:33:14 PM PDT 24 9206531154 ps
T279 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.13855841 Jul 21 06:33:07 PM PDT 24 Jul 21 06:33:15 PM PDT 24 2038894729 ps
T869 /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2345856222 Jul 21 06:33:19 PM PDT 24 Jul 21 06:33:25 PM PDT 24 2246907968 ps
T870 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2108343515 Jul 21 06:33:07 PM PDT 24 Jul 21 06:33:11 PM PDT 24 2141986229 ps
T871 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1424158462 Jul 21 06:33:04 PM PDT 24 Jul 21 06:33:11 PM PDT 24 6074103977 ps
T872 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3086166316 Jul 21 06:33:02 PM PDT 24 Jul 21 06:33:06 PM PDT 24 2060286921 ps
T873 /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.59685085 Jul 21 06:33:22 PM PDT 24 Jul 21 06:33:26 PM PDT 24 2032877778 ps
T874 /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.531049734 Jul 21 06:33:23 PM PDT 24 Jul 21 06:33:28 PM PDT 24 2017606859 ps
T875 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3370395253 Jul 21 06:33:13 PM PDT 24 Jul 21 06:33:16 PM PDT 24 2014382193 ps
T876 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.1109538490 Jul 21 06:33:08 PM PDT 24 Jul 21 06:33:15 PM PDT 24 2050061337 ps
T877 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1543683818 Jul 21 06:33:14 PM PDT 24 Jul 21 06:33:18 PM PDT 24 2502240495 ps
T364 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1231775410 Jul 21 06:33:16 PM PDT 24 Jul 21 06:33:47 PM PDT 24 42795766972 ps
T878 /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2646149854 Jul 21 06:33:04 PM PDT 24 Jul 21 06:33:12 PM PDT 24 2052786761 ps
T879 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.759283460 Jul 21 06:33:06 PM PDT 24 Jul 21 06:33:11 PM PDT 24 9026269566 ps
T880 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3543871485 Jul 21 06:33:21 PM PDT 24 Jul 21 06:33:27 PM PDT 24 2080422090 ps
T881 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.224135125 Jul 21 06:33:08 PM PDT 24 Jul 21 06:33:18 PM PDT 24 2052267279 ps
T882 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.647327263 Jul 21 06:33:01 PM PDT 24 Jul 21 06:33:08 PM PDT 24 2138857786 ps
T883 /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.990120426 Jul 21 06:33:23 PM PDT 24 Jul 21 06:33:26 PM PDT 24 2206343422 ps
T884 /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.139559214 Jul 21 06:33:27 PM PDT 24 Jul 21 06:33:32 PM PDT 24 2026753177 ps
T885 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3439974291 Jul 21 06:33:13 PM PDT 24 Jul 21 06:33:19 PM PDT 24 4969769836 ps
T886 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3861183035 Jul 21 06:33:07 PM PDT 24 Jul 21 06:33:11 PM PDT 24 2046464570 ps
T887 /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.137430049 Jul 21 06:33:06 PM PDT 24 Jul 21 06:33:09 PM PDT 24 2039655027 ps
T888 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.995397473 Jul 21 06:33:01 PM PDT 24 Jul 21 06:33:07 PM PDT 24 5012827140 ps
T889 /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.954661837 Jul 21 06:33:21 PM PDT 24 Jul 21 06:33:25 PM PDT 24 2097895236 ps
T890 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.704128308 Jul 21 06:33:12 PM PDT 24 Jul 21 06:33:27 PM PDT 24 22279856429 ps
T891 /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1246425032 Jul 21 06:33:25 PM PDT 24 Jul 21 06:33:29 PM PDT 24 2045422446 ps
T892 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2976538902 Jul 21 06:33:06 PM PDT 24 Jul 21 06:33:14 PM PDT 24 2055703207 ps
T893 /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3323775745 Jul 21 06:33:03 PM PDT 24 Jul 21 06:34:58 PM PDT 24 42456595906 ps
T894 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3050668275 Jul 21 06:32:58 PM PDT 24 Jul 21 06:33:03 PM PDT 24 4066212913 ps
T895 /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3692283999 Jul 21 06:33:07 PM PDT 24 Jul 21 06:33:15 PM PDT 24 2048674998 ps
T896 /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2362178432 Jul 21 06:33:26 PM PDT 24 Jul 21 06:33:33 PM PDT 24 2012051994 ps
T897 /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.423045524 Jul 21 06:33:14 PM PDT 24 Jul 21 06:33:23 PM PDT 24 9142291799 ps
T898 /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3863738225 Jul 21 06:33:23 PM PDT 24 Jul 21 06:33:28 PM PDT 24 2017339393 ps
T899 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1817793899 Jul 21 06:33:02 PM PDT 24 Jul 21 06:33:10 PM PDT 24 2039331602 ps
T900 /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3025117836 Jul 21 06:33:26 PM PDT 24 Jul 21 06:33:34 PM PDT 24 2013556821 ps
T901 /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.4911933 Jul 21 06:33:19 PM PDT 24 Jul 21 06:33:26 PM PDT 24 2112529376 ps
T902 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2708223060 Jul 21 06:32:58 PM PDT 24 Jul 21 06:33:29 PM PDT 24 42489941456 ps
T903 /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3262665317 Jul 21 06:33:00 PM PDT 24 Jul 21 06:33:09 PM PDT 24 2035061703 ps
T904 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.872730728 Jul 21 06:33:02 PM PDT 24 Jul 21 06:34:07 PM PDT 24 22235255161 ps
T905 /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2277039582 Jul 21 06:33:20 PM PDT 24 Jul 21 06:33:55 PM PDT 24 9460314801 ps
T906 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.638492459 Jul 21 06:33:08 PM PDT 24 Jul 21 06:33:14 PM PDT 24 2022118899 ps
T907 /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1149712071 Jul 21 06:33:02 PM PDT 24 Jul 21 06:33:11 PM PDT 24 2143672502 ps
T908 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2824923860 Jul 21 06:33:00 PM PDT 24 Jul 21 06:35:29 PM PDT 24 39634729624 ps
T909 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3540967620 Jul 21 06:32:56 PM PDT 24 Jul 21 06:33:16 PM PDT 24 7196760628 ps
T910 /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1597577709 Jul 21 06:33:00 PM PDT 24 Jul 21 06:33:08 PM PDT 24 6054018098 ps
T911 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1971974683 Jul 21 06:33:14 PM PDT 24 Jul 21 06:33:27 PM PDT 24 8633342421 ps
T912 /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2867470953 Jul 21 06:33:22 PM PDT 24 Jul 21 06:33:27 PM PDT 24 3085160023 ps
T913 /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2050366183 Jul 21 06:33:09 PM PDT 24 Jul 21 06:33:28 PM PDT 24 5935975058 ps
T914 /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1669360588 Jul 21 06:33:25 PM PDT 24 Jul 21 06:33:33 PM PDT 24 2017191873 ps
T915 /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1282232322 Jul 21 06:33:19 PM PDT 24 Jul 21 06:33:26 PM PDT 24 2015972819 ps

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all.380724280
Short name T1
Test name
Test status
Simulation time 211597208275 ps
CPU time 582.59 seconds
Started Jul 21 06:37:58 PM PDT 24
Finished Jul 21 06:47:41 PM PDT 24
Peak memory 201756 kb
Host smart-e848c643-3b8d-42e9-99d8-fd4520f2d7c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380724280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_str
ess_all.380724280
Directory /workspace/8.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2854437610
Short name T20
Test name
Test status
Simulation time 41133128300 ps
CPU time 108.89 seconds
Started Jul 21 06:37:44 PM PDT 24
Finished Jul 21 06:39:34 PM PDT 24
Peak memory 201600 kb
Host smart-861d6cb6-dd30-48aa-81c5-3d0e7821b0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854437610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.2854437610
Directory /workspace/1.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1029734268
Short name T10
Test name
Test status
Simulation time 27008179294 ps
CPU time 53.89 seconds
Started Jul 21 06:38:09 PM PDT 24
Finished Jul 21 06:39:04 PM PDT 24
Peak memory 210192 kb
Host smart-b7443ba1-0678-4417-b636-ae238bb41be5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1029734268 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.1029734268
Directory /workspace/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2795096850
Short name T37
Test name
Test status
Simulation time 1372948142180 ps
CPU time 89.99 seconds
Started Jul 21 06:38:12 PM PDT 24
Finished Jul 21 06:39:43 PM PDT 24
Peak memory 210212 kb
Host smart-c024e4fb-1aab-45c1-b385-7c3a5d197a64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795096850 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.2795096850
Directory /workspace/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.872077887
Short name T26
Test name
Test status
Simulation time 70512914077 ps
CPU time 60.94 seconds
Started Jul 21 06:39:42 PM PDT 24
Finished Jul 21 06:40:44 PM PDT 24
Peak memory 201924 kb
Host smart-9079fcc9-c270-4ba1-94be-c0cf27ea0f6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872077887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_wi
th_pre_cond.872077887
Directory /workspace/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1493914282
Short name T260
Test name
Test status
Simulation time 42396314658 ps
CPU time 99.97 seconds
Started Jul 21 06:33:14 PM PDT 24
Finished Jul 21 06:34:55 PM PDT 24
Peak memory 202256 kb
Host smart-68648d46-5294-4819-bd64-055352331a4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493914282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_tl_intg_err.1493914282
Directory /workspace/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3451345648
Short name T170
Test name
Test status
Simulation time 612453453597 ps
CPU time 41.96 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:38:45 PM PDT 24
Peak memory 210380 kb
Host smart-bd585487-02e1-4f9b-a71a-b28bfd301610
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451345648 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3451345648
Directory /workspace/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2294782728
Short name T36
Test name
Test status
Simulation time 41316117644 ps
CPU time 107.5 seconds
Started Jul 21 06:38:27 PM PDT 24
Finished Jul 21 06:40:15 PM PDT 24
Peak memory 218300 kb
Host smart-37f7a92d-5abc-49f5-86b5-0cb81c446e0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294782728 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.2294782728
Directory /workspace/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1614891232
Short name T77
Test name
Test status
Simulation time 64774371685 ps
CPU time 78.13 seconds
Started Jul 21 06:37:36 PM PDT 24
Finished Jul 21 06:38:56 PM PDT 24
Peak memory 218348 kb
Host smart-f6bfdc38-285d-477d-8e0c-c45ca4102809
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614891232 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.1614891232
Directory /workspace/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_edge_detect.953190545
Short name T169
Test name
Test status
Simulation time 3536303956 ps
CPU time 7.02 seconds
Started Jul 21 06:38:19 PM PDT 24
Finished Jul 21 06:38:26 PM PDT 24
Peak memory 201528 kb
Host smart-ab37a58e-4a70-4fb9-a9f7-157421f035c8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953190545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctr
l_edge_detect.953190545
Directory /workspace/17.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2627208841
Short name T237
Test name
Test status
Simulation time 214863509671 ps
CPU time 291.27 seconds
Started Jul 21 06:39:35 PM PDT 24
Finished Jul 21 06:44:27 PM PDT 24
Peak memory 201844 kb
Host smart-38ab0eae-5d6e-4f94-bed2-d765da40798c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627208841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_w
ith_pre_cond.2627208841
Directory /workspace/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2390769534
Short name T146
Test name
Test status
Simulation time 98035245698 ps
CPU time 60.67 seconds
Started Jul 21 06:37:45 PM PDT 24
Finished Jul 21 06:38:46 PM PDT 24
Peak memory 210252 kb
Host smart-c637dff4-9841-4a9b-8fa3-f3c3f9124e1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390769534 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.2390769534
Directory /workspace/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_edge_detect.1260499984
Short name T206
Test name
Test status
Simulation time 4193338484 ps
CPU time 9.03 seconds
Started Jul 21 06:38:47 PM PDT 24
Finished Jul 21 06:38:57 PM PDT 24
Peak memory 201568 kb
Host smart-f2b28f95-e0a3-4089-aece-d29c1afd38cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260499984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ct
rl_edge_detect.1260499984
Directory /workspace/31.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3555372347
Short name T84
Test name
Test status
Simulation time 80353519249 ps
CPU time 19.73 seconds
Started Jul 21 06:38:34 PM PDT 24
Finished Jul 21 06:38:55 PM PDT 24
Peak memory 210124 kb
Host smart-c18a5247-02ed-4480-8b73-e226246ea83e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555372347 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.3555372347
Directory /workspace/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_stress_all.1852351336
Short name T81
Test name
Test status
Simulation time 14351670891 ps
CPU time 24.01 seconds
Started Jul 21 06:37:49 PM PDT 24
Finished Jul 21 06:38:14 PM PDT 24
Peak memory 201448 kb
Host smart-f8e14a8a-1529-4ee6-8267-787f80e5ed0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852351336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_st
ress_all.1852351336
Directory /workspace/2.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_sec_cm.3683078081
Short name T50
Test name
Test status
Simulation time 22212696600 ps
CPU time 6.93 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:38:00 PM PDT 24
Peak memory 220560 kb
Host smart-03db6c4b-ac4d-47c1-89fa-19e9aa848266
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3683078081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.3683078081
Directory /workspace/3.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_stress_all.2886265808
Short name T97
Test name
Test status
Simulation time 323160425557 ps
CPU time 98.12 seconds
Started Jul 21 06:38:59 PM PDT 24
Finished Jul 21 06:40:38 PM PDT 24
Peak memory 201840 kb
Host smart-c3fe0412-5947-4599-8e93-a5a3ca9d33fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886265808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_s
tress_all.2886265808
Directory /workspace/37.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2207602119
Short name T95
Test name
Test status
Simulation time 63872935895 ps
CPU time 86.75 seconds
Started Jul 21 06:39:41 PM PDT 24
Finished Jul 21 06:41:09 PM PDT 24
Peak memory 201908 kb
Host smart-132eee4d-b59d-4c29-959e-576a4046de29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207602119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_w
ith_pre_cond.2207602119
Directory /workspace/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2729664145
Short name T78
Test name
Test status
Simulation time 147781227870 ps
CPU time 286.33 seconds
Started Jul 21 06:37:50 PM PDT 24
Finished Jul 21 06:42:38 PM PDT 24
Peak memory 210236 kb
Host smart-19e48004-58c2-4f6a-b37f-d845bcf5191d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729664145 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.2729664145
Directory /workspace/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.563451975
Short name T318
Test name
Test status
Simulation time 37643069885 ps
CPU time 205.53 seconds
Started Jul 21 06:33:02 PM PDT 24
Finished Jul 21 06:36:30 PM PDT 24
Peak memory 202224 kb
Host smart-43500f7d-0b36-4222-8bf9-dec2b6dc4f30
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563451975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_bit_bash.563451975
Directory /workspace/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3560092950
Short name T241
Test name
Test status
Simulation time 96760378503 ps
CPU time 145.96 seconds
Started Jul 21 06:39:36 PM PDT 24
Finished Jul 21 06:42:03 PM PDT 24
Peak memory 201828 kb
Host smart-fff9e59c-e1c7-46fd-b58f-ee3b0520d43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560092950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_w
ith_pre_cond.3560092950
Directory /workspace/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2929427186
Short name T90
Test name
Test status
Simulation time 5167344360 ps
CPU time 1.95 seconds
Started Jul 21 06:39:00 PM PDT 24
Finished Jul 21 06:39:02 PM PDT 24
Peak memory 201536 kb
Host smart-236fb274-1a50-4370-8995-e2061a5db073
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929427186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ultra_low_pwr.2929427186
Directory /workspace/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.42089320
Short name T80
Test name
Test status
Simulation time 113066508289 ps
CPU time 71.99 seconds
Started Jul 21 06:38:53 PM PDT 24
Finished Jul 21 06:40:06 PM PDT 24
Peak memory 218328 kb
Host smart-c1efbe4d-1f46-4e2e-a657-a049a3b50178
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42089320 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.42089320
Directory /workspace/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3843864347
Short name T262
Test name
Test status
Simulation time 2034399428 ps
CPU time 6.68 seconds
Started Jul 21 06:33:02 PM PDT 24
Finished Jul 21 06:33:11 PM PDT 24
Peak memory 202060 kb
Host smart-c20e32a9-7f18-4b9b-b439-a83923fe990c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843864347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_error
s.3843864347
Directory /workspace/3.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.213647273
Short name T75
Test name
Test status
Simulation time 111885745570 ps
CPU time 62.84 seconds
Started Jul 21 06:37:48 PM PDT 24
Finished Jul 21 06:38:52 PM PDT 24
Peak memory 202008 kb
Host smart-d7cbec79-ad06-4e8f-bd13-76db84d715fe
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213647273 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.213647273
Directory /workspace/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect.3390944422
Short name T3
Test name
Test status
Simulation time 199236346825 ps
CPU time 134.76 seconds
Started Jul 21 06:38:30 PM PDT 24
Finished Jul 21 06:40:46 PM PDT 24
Peak memory 201776 kb
Host smart-8fd263c9-d5ff-4bd7-9f63-43924ab7855d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390944422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_c
trl_combo_detect.3390944422
Directory /workspace/22.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_edge_detect.3069400919
Short name T163
Test name
Test status
Simulation time 1518407661730 ps
CPU time 1314.81 seconds
Started Jul 21 06:39:03 PM PDT 24
Finished Jul 21 07:00:59 PM PDT 24
Peak memory 201576 kb
Host smart-f040a921-6eeb-4438-98c3-7b6659820ebe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069400919 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_edge_detect.3069400919
Directory /workspace/38.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_edge_detect.3222509121
Short name T218
Test name
Test status
Simulation time 3639517127 ps
CPU time 2.94 seconds
Started Jul 21 06:37:37 PM PDT 24
Finished Jul 21 06:37:41 PM PDT 24
Peak memory 201544 kb
Host smart-6d7b3d25-bf11-43cc-8633-8efdeb4bf383
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222509121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctr
l_edge_detect.3222509121
Directory /workspace/1.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2690746145
Short name T200
Test name
Test status
Simulation time 82080890491 ps
CPU time 204.68 seconds
Started Jul 21 06:37:55 PM PDT 24
Finished Jul 21 06:41:21 PM PDT 24
Peak memory 201972 kb
Host smart-f07bff37-378e-44ef-bbcf-7f4d074eab9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690746145 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_wi
th_pre_cond.2690746145
Directory /workspace/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all.232788254
Short name T332
Test name
Test status
Simulation time 138192543846 ps
CPU time 180.13 seconds
Started Jul 21 06:38:52 PM PDT 24
Finished Jul 21 06:41:53 PM PDT 24
Peak memory 201744 kb
Host smart-944d4597-b560-4495-82ca-46fefe5c7af7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232788254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_st
ress_all.232788254
Directory /workspace/33.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_alert_test.1979899044
Short name T309
Test name
Test status
Simulation time 2010962009 ps
CPU time 5.85 seconds
Started Jul 21 06:38:02 PM PDT 24
Finished Jul 21 06:38:09 PM PDT 24
Peak memory 201524 kb
Host smart-c94d0488-756a-4278-a7ec-52d910d7c202
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979899044 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_te
st.1979899044
Directory /workspace/11.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4204209015
Short name T17
Test name
Test status
Simulation time 8685794180 ps
CPU time 38.63 seconds
Started Jul 21 06:33:19 PM PDT 24
Finished Jul 21 06:33:59 PM PDT 24
Peak memory 202184 kb
Host smart-7198c87c-05fe-45ac-9e39-49c004305d96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204209015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_same_csr_outstanding.4204209015
Directory /workspace/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.205599332
Short name T354
Test name
Test status
Simulation time 134803560070 ps
CPU time 349.24 seconds
Started Jul 21 06:39:36 PM PDT 24
Finished Jul 21 06:45:26 PM PDT 24
Peak memory 201856 kb
Host smart-f81252c8-78e4-4007-a3f7-6fd33ca3a533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205599332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_wi
th_pre_cond.205599332
Directory /workspace/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect.446258193
Short name T33
Test name
Test status
Simulation time 130713479449 ps
CPU time 18.28 seconds
Started Jul 21 06:38:28 PM PDT 24
Finished Jul 21 06:38:47 PM PDT 24
Peak memory 201772 kb
Host smart-b755f037-b120-445c-afff-3eb21325dcb5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446258193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ct
rl_combo_detect.446258193
Directory /workspace/23.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.673462617
Short name T76
Test name
Test status
Simulation time 143222608387 ps
CPU time 88.47 seconds
Started Jul 21 06:38:19 PM PDT 24
Finished Jul 21 06:39:48 PM PDT 24
Peak memory 218288 kb
Host smart-ff18ddbc-221f-470a-9822-2a1478e4c1b3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673462617 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.673462617
Directory /workspace/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1251545713
Short name T746
Test name
Test status
Simulation time 186518184424 ps
CPU time 67.61 seconds
Started Jul 21 06:38:10 PM PDT 24
Finished Jul 21 06:39:18 PM PDT 24
Peak memory 201828 kb
Host smart-4382642e-7171-495c-a706-903835d626a0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251545713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_combo_detect.1251545713
Directory /workspace/14.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2300455814
Short name T345
Test name
Test status
Simulation time 92573145564 ps
CPU time 235.93 seconds
Started Jul 21 06:38:52 PM PDT 24
Finished Jul 21 06:42:49 PM PDT 24
Peak memory 201888 kb
Host smart-b17ffdb3-2075-4b43-9a2e-cffc7c59b418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300455814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_w
ith_pre_cond.2300455814
Directory /workspace/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1231775410
Short name T364
Test name
Test status
Simulation time 42795766972 ps
CPU time 29.88 seconds
Started Jul 21 06:33:16 PM PDT 24
Finished Jul 21 06:33:47 PM PDT 24
Peak memory 202200 kb
Host smart-081b384f-a3b7-401f-8197-e0b78520f5e8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231775410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_tl_intg_err.1231775410
Directory /workspace/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3120229643
Short name T343
Test name
Test status
Simulation time 78497931812 ps
CPU time 197.32 seconds
Started Jul 21 06:39:35 PM PDT 24
Finished Jul 21 06:42:53 PM PDT 24
Peak memory 201920 kb
Host smart-2479cda5-6673-45f5-9384-6653c71fd3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120229643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_w
ith_pre_cond.3120229643
Directory /workspace/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.89059082
Short name T30
Test name
Test status
Simulation time 100350195638 ps
CPU time 118.32 seconds
Started Jul 21 06:38:35 PM PDT 24
Finished Jul 21 06:40:34 PM PDT 24
Peak memory 214548 kb
Host smart-b2913e4e-9f62-4ea9-ba03-d48705a49d3d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89059082 -assert no
postproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.89059082
Directory /workspace/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.4078187196
Short name T278
Test name
Test status
Simulation time 2192271784 ps
CPU time 4.93 seconds
Started Jul 21 06:33:00 PM PDT 24
Finished Jul 21 06:33:08 PM PDT 24
Peak memory 202216 kb
Host smart-86f4ff80-4f62-421f-86e1-d10d8ba8bd69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078187196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_error
s.4078187196
Directory /workspace/0.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3513169905
Short name T43
Test name
Test status
Simulation time 183239465492 ps
CPU time 479.95 seconds
Started Jul 21 06:38:05 PM PDT 24
Finished Jul 21 06:46:06 PM PDT 24
Peak memory 201852 kb
Host smart-ddbe4bdf-7bf7-42a8-b485-ae11c8464f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513169905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_w
ith_pre_cond.3513169905
Directory /workspace/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect.508159130
Short name T361
Test name
Test status
Simulation time 64224218288 ps
CPU time 99.67 seconds
Started Jul 21 06:38:08 PM PDT 24
Finished Jul 21 06:39:48 PM PDT 24
Peak memory 201816 kb
Host smart-f78616d4-3108-4cd7-93ed-e6e0bcca2093
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508159130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_combo_detect.508159130
Directory /workspace/16.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect.749267692
Short name T363
Test name
Test status
Simulation time 63251314247 ps
CPU time 77.32 seconds
Started Jul 21 06:39:28 PM PDT 24
Finished Jul 21 06:40:45 PM PDT 24
Peak memory 201072 kb
Host smart-075ba33e-4f76-423b-a5e4-4371701b713d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749267692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_combo_detect.749267692
Directory /workspace/46.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.4099069261
Short name T346
Test name
Test status
Simulation time 87944825106 ps
CPU time 58.25 seconds
Started Jul 21 06:39:32 PM PDT 24
Finished Jul 21 06:40:30 PM PDT 24
Peak memory 201880 kb
Host smart-9956adcd-2af9-4401-a920-4ee64b27dabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099069261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_w
ith_pre_cond.4099069261
Directory /workspace/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1450364008
Short name T79
Test name
Test status
Simulation time 49858501744 ps
CPU time 107.78 seconds
Started Jul 21 06:39:40 PM PDT 24
Finished Jul 21 06:41:28 PM PDT 24
Peak memory 201768 kb
Host smart-867099ec-8e31-4427-aa84-b1c6761a51e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450364008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_w
ith_pre_cond.1450364008
Directory /workspace/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3309832976
Short name T269
Test name
Test status
Simulation time 2077209210 ps
CPU time 2.09 seconds
Started Jul 21 06:33:08 PM PDT 24
Finished Jul 21 06:33:13 PM PDT 24
Peak memory 201856 kb
Host smart-dbd4c45d-6383-4f0e-9529-42ac02e8520d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309832976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_
rw.3309832976
Directory /workspace/10.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2777350373
Short name T47
Test name
Test status
Simulation time 3747028579 ps
CPU time 10.61 seconds
Started Jul 21 06:37:44 PM PDT 24
Finished Jul 21 06:37:56 PM PDT 24
Peak memory 201656 kb
Host smart-6350e0e0-fe98-4e7b-954e-274c3fca9bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777350373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.2777350373
Directory /workspace/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect.2868405396
Short name T360
Test name
Test status
Simulation time 106764885743 ps
CPU time 70.39 seconds
Started Jul 21 06:38:12 PM PDT 24
Finished Jul 21 06:39:24 PM PDT 24
Peak memory 201808 kb
Host smart-c1aa6927-875c-4f05-9805-36d07abf94aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868405396 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_combo_detect.2868405396
Directory /workspace/13.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.4242475546
Short name T565
Test name
Test status
Simulation time 4290068853998 ps
CPU time 794.38 seconds
Started Jul 21 06:38:14 PM PDT 24
Finished Jul 21 06:51:29 PM PDT 24
Peak memory 201540 kb
Host smart-d890e178-359b-4d9b-be4f-08f4eefe3fcb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242475546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_ultra_low_pwr.4242475546
Directory /workspace/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1406475748
Short name T356
Test name
Test status
Simulation time 61474513263 ps
CPU time 38.26 seconds
Started Jul 21 06:38:24 PM PDT 24
Finished Jul 21 06:39:03 PM PDT 24
Peak memory 201788 kb
Host smart-10f7adcc-39e8-4c9d-88ef-23a18495d109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406475748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_w
ith_pre_cond.1406475748
Directory /workspace/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.171551215
Short name T153
Test name
Test status
Simulation time 94810689475 ps
CPU time 48.89 seconds
Started Jul 21 06:38:25 PM PDT 24
Finished Jul 21 06:39:14 PM PDT 24
Peak memory 201812 kb
Host smart-cad68d4b-f3b9-4b54-b285-e38cdfcf0b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171551215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_wi
th_pre_cond.171551215
Directory /workspace/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2575817860
Short name T369
Test name
Test status
Simulation time 100689088376 ps
CPU time 66.07 seconds
Started Jul 21 06:39:12 PM PDT 24
Finished Jul 21 06:40:18 PM PDT 24
Peak memory 201912 kb
Host smart-b77149e9-0e57-45f1-9a6d-68dde67199a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575817860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_w
ith_pre_cond.2575817860
Directory /workspace/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.4114593367
Short name T82
Test name
Test status
Simulation time 67222414753 ps
CPU time 44.1 seconds
Started Jul 21 06:39:44 PM PDT 24
Finished Jul 21 06:40:29 PM PDT 24
Peak memory 201872 kb
Host smart-9b8fa78b-b02c-4e09-8e41-bfebc23badab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114593367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_w
ith_pre_cond.4114593367
Directory /workspace/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.448469916
Short name T358
Test name
Test status
Simulation time 164276564359 ps
CPU time 107.6 seconds
Started Jul 21 06:39:36 PM PDT 24
Finished Jul 21 06:41:25 PM PDT 24
Peak memory 201824 kb
Host smart-523ce1a5-e368-4ae9-9330-2e8bb8ba8aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448469916 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_wi
th_pre_cond.448469916
Directory /workspace/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.156679248
Short name T842
Test name
Test status
Simulation time 2573767806 ps
CPU time 1.55 seconds
Started Jul 21 06:33:00 PM PDT 24
Finished Jul 21 06:33:05 PM PDT 24
Peak memory 202096 kb
Host smart-95bd6b0e-e35d-4d61-ad16-bbd805e46b21
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156679248 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_mem_rw_with_rand_reset.156679248
Directory /workspace/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_feature_disable.4039643741
Short name T58
Test name
Test status
Simulation time 37535082153 ps
CPU time 94.6 seconds
Started Jul 21 06:37:37 PM PDT 24
Finished Jul 21 06:39:12 PM PDT 24
Peak memory 201608 kb
Host smart-e1d9989f-5606-406c-acaa-a7c74efa3abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039643741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.4039643741
Directory /workspace/0.sysrst_ctrl_feature_disable/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3667607504
Short name T236
Test name
Test status
Simulation time 96980711362 ps
CPU time 119.34 seconds
Started Jul 21 06:37:48 PM PDT 24
Finished Jul 21 06:39:48 PM PDT 24
Peak memory 201876 kb
Host smart-460bf5ac-0764-46f8-86be-545d8d917f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667607504 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_wi
th_pre_cond.3667607504
Directory /workspace/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3766668202
Short name T249
Test name
Test status
Simulation time 65081553042 ps
CPU time 87.81 seconds
Started Jul 21 06:38:03 PM PDT 24
Finished Jul 21 06:39:32 PM PDT 24
Peak memory 201960 kb
Host smart-cd5cb0df-9532-46ca-a18b-1f7a6018db97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766668202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_w
ith_pre_cond.3766668202
Directory /workspace/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3056009317
Short name T822
Test name
Test status
Simulation time 2552797820 ps
CPU time 2.98 seconds
Started Jul 21 06:32:59 PM PDT 24
Finished Jul 21 06:33:04 PM PDT 24
Peak memory 202120 kb
Host smart-67260679-ea4d-4ae5-bfa5-705794347e73
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056009317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_aliasing.3056009317
Directory /workspace/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2824923860
Short name T908
Test name
Test status
Simulation time 39634729624 ps
CPU time 145.95 seconds
Started Jul 21 06:33:00 PM PDT 24
Finished Jul 21 06:35:29 PM PDT 24
Peak memory 202188 kb
Host smart-7a10e258-2328-4065-ab3c-fb3026964749
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824923860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_bit_bash.2824923860
Directory /workspace/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1363717883
Short name T331
Test name
Test status
Simulation time 4082396674 ps
CPU time 2.23 seconds
Started Jul 21 06:33:00 PM PDT 24
Finished Jul 21 06:33:06 PM PDT 24
Peak memory 201992 kb
Host smart-fec3c3cc-8bf8-4e2c-999e-56a298510d19
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363717883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl
_csr_hw_reset.1363717883
Directory /workspace/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2603747616
Short name T840
Test name
Test status
Simulation time 2078036344 ps
CPU time 2.11 seconds
Started Jul 21 06:32:58 PM PDT 24
Finished Jul 21 06:33:02 PM PDT 24
Peak memory 201800 kb
Host smart-c0aaaa7c-065e-483e-be73-63b88e77b69a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603747616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_r
w.2603747616
Directory /workspace/0.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3876541104
Short name T810
Test name
Test status
Simulation time 2029267021 ps
CPU time 2.05 seconds
Started Jul 21 06:33:00 PM PDT 24
Finished Jul 21 06:33:05 PM PDT 24
Peak memory 201796 kb
Host smart-fd7ad51f-6d24-4f04-b3ef-96d078cd7b8c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876541104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_tes
t.3876541104
Directory /workspace/0.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3540967620
Short name T909
Test name
Test status
Simulation time 7196760628 ps
CPU time 19.2 seconds
Started Jul 21 06:32:56 PM PDT 24
Finished Jul 21 06:33:16 PM PDT 24
Peak memory 202228 kb
Host smart-9e2a272c-e9c4-486c-a100-f0c1ee58855a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540967620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_same_csr_outstanding.3540967620
Directory /workspace/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2708223060
Short name T902
Test name
Test status
Simulation time 42489941456 ps
CPU time 28.82 seconds
Started Jul 21 06:32:58 PM PDT 24
Finished Jul 21 06:33:29 PM PDT 24
Peak memory 202252 kb
Host smart-08a3b985-7f2d-4d44-9a33-f4c6b637d381
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708223060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_tl_intg_err.2708223060
Directory /workspace/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3706236947
Short name T326
Test name
Test status
Simulation time 3109700507 ps
CPU time 4.94 seconds
Started Jul 21 06:33:01 PM PDT 24
Finished Jul 21 06:33:09 PM PDT 24
Peak memory 202068 kb
Host smart-7ae1db42-f01f-40f1-814a-993250dddb03
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3706236947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_aliasing.3706236947
Directory /workspace/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.697153897
Short name T322
Test name
Test status
Simulation time 35739671388 ps
CPU time 40.07 seconds
Started Jul 21 06:33:04 PM PDT 24
Finished Jul 21 06:33:46 PM PDT 24
Peak memory 202216 kb
Host smart-5078fd36-5799-43ed-b817-a509812a317c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697153897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_
csr_bit_bash.697153897
Directory /workspace/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3050668275
Short name T894
Test name
Test status
Simulation time 4066212913 ps
CPU time 2.66 seconds
Started Jul 21 06:32:58 PM PDT 24
Finished Jul 21 06:33:03 PM PDT 24
Peak memory 201924 kb
Host smart-09b85281-9e95-416b-8981-6dd43e139d4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050668275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl
_csr_hw_reset.3050668275
Directory /workspace/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1149712071
Short name T907
Test name
Test status
Simulation time 2143672502 ps
CPU time 6.63 seconds
Started Jul 21 06:33:02 PM PDT 24
Finished Jul 21 06:33:11 PM PDT 24
Peak memory 201960 kb
Host smart-3d9494e1-7b24-4b26-b1b5-2b25e99507d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149712071 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1149712071
Directory /workspace/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2308357586
Short name T320
Test name
Test status
Simulation time 2143773921 ps
CPU time 1.92 seconds
Started Jul 21 06:33:00 PM PDT 24
Finished Jul 21 06:33:05 PM PDT 24
Peak memory 201840 kb
Host smart-a23763a0-2fc1-43fb-97a1-a258082e8407
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308357586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_r
w.2308357586
Directory /workspace/1.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1877789066
Short name T834
Test name
Test status
Simulation time 2045624180 ps
CPU time 1.74 seconds
Started Jul 21 06:33:01 PM PDT 24
Finished Jul 21 06:33:06 PM PDT 24
Peak memory 201636 kb
Host smart-2f199468-de0f-482b-952d-b96b53ca97ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877789066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_tes
t.1877789066
Directory /workspace/1.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2801881286
Short name T868
Test name
Test status
Simulation time 9206531154 ps
CPU time 7.48 seconds
Started Jul 21 06:33:05 PM PDT 24
Finished Jul 21 06:33:14 PM PDT 24
Peak memory 202220 kb
Host smart-69e45769-d0b3-40b0-a1f9-40308c312ef0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801881286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_same_csr_outstanding.2801881286
Directory /workspace/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2236465724
Short name T272
Test name
Test status
Simulation time 2097140599 ps
CPU time 3.11 seconds
Started Jul 21 06:32:58 PM PDT 24
Finished Jul 21 06:33:03 PM PDT 24
Peak memory 202228 kb
Host smart-3d22ffee-2914-4150-8948-a0aa638eff8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236465724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_error
s.2236465724
Directory /workspace/1.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.182563541
Short name T281
Test name
Test status
Simulation time 22216067131 ps
CPU time 57.15 seconds
Started Jul 21 06:32:56 PM PDT 24
Finished Jul 21 06:33:54 PM PDT 24
Peak memory 202200 kb
Host smart-34463cff-6a55-4ce0-8359-bc640f474e1b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182563541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_tl_intg_err.182563541
Directory /workspace/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3965682261
Short name T821
Test name
Test status
Simulation time 2075800152 ps
CPU time 2.85 seconds
Started Jul 21 06:33:09 PM PDT 24
Finished Jul 21 06:33:14 PM PDT 24
Peak memory 201856 kb
Host smart-315597dd-46e9-4ac3-a1cb-09870dccc9af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965682261 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3965682261
Directory /workspace/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1182139985
Short name T865
Test name
Test status
Simulation time 2045860236 ps
CPU time 1.79 seconds
Started Jul 21 06:33:06 PM PDT 24
Finished Jul 21 06:33:10 PM PDT 24
Peak memory 201780 kb
Host smart-85ab994f-1dd1-44d8-ae69-63797e05be53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182139985 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_te
st.1182139985
Directory /workspace/10.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.805744530
Short name T841
Test name
Test status
Simulation time 7651277627 ps
CPU time 4.97 seconds
Started Jul 21 06:33:08 PM PDT 24
Finished Jul 21 06:33:15 PM PDT 24
Peak memory 202328 kb
Host smart-7646dd58-b025-44a2-9a5c-4c57ec4df02e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805744530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.sysrst_ctrl_same_csr_outstanding.805744530
Directory /workspace/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3132110310
Short name T859
Test name
Test status
Simulation time 2023553201 ps
CPU time 6.29 seconds
Started Jul 21 06:33:08 PM PDT 24
Finished Jul 21 06:33:17 PM PDT 24
Peak memory 202048 kb
Host smart-014ff6c6-bf03-43f8-9cd9-5a320ba0683b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132110310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_erro
rs.3132110310
Directory /workspace/10.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3294441911
Short name T283
Test name
Test status
Simulation time 23177303143 ps
CPU time 14.73 seconds
Started Jul 21 06:33:08 PM PDT 24
Finished Jul 21 06:33:25 PM PDT 24
Peak memory 202228 kb
Host smart-63065ee4-5c4f-4f9a-8ade-08e087dad2ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294441911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_tl_intg_err.3294441911
Directory /workspace/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.944991183
Short name T858
Test name
Test status
Simulation time 2128887897 ps
CPU time 2.17 seconds
Started Jul 21 06:33:15 PM PDT 24
Finished Jul 21 06:33:18 PM PDT 24
Peak memory 201932 kb
Host smart-04223620-2b52-4ac5-aa9b-5b1e6f21a3ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944991183 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_mem_rw_with_rand_reset.944991183
Directory /workspace/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3543871485
Short name T880
Test name
Test status
Simulation time 2080422090 ps
CPU time 3.55 seconds
Started Jul 21 06:33:21 PM PDT 24
Finished Jul 21 06:33:27 PM PDT 24
Peak memory 201880 kb
Host smart-e79ca250-fc05-425d-b5c7-7acc3c1f6c1f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543871485 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_
rw.3543871485
Directory /workspace/11.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.638492459
Short name T906
Test name
Test status
Simulation time 2022118899 ps
CPU time 3.1 seconds
Started Jul 21 06:33:08 PM PDT 24
Finished Jul 21 06:33:14 PM PDT 24
Peak memory 201660 kb
Host smart-1be0db32-afd1-4671-ac0f-4007bb7fab02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638492459 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_tes
t.638492459
Directory /workspace/11.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1971974683
Short name T911
Test name
Test status
Simulation time 8633342421 ps
CPU time 11.75 seconds
Started Jul 21 06:33:14 PM PDT 24
Finished Jul 21 06:33:27 PM PDT 24
Peak memory 202224 kb
Host smart-6698ee56-a512-4ea6-8099-58ec75bce2cf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971974683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_same_csr_outstanding.1971974683
Directory /workspace/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2827518604
Short name T273
Test name
Test status
Simulation time 2059307967 ps
CPU time 3.97 seconds
Started Jul 21 06:33:07 PM PDT 24
Finished Jul 21 06:33:14 PM PDT 24
Peak memory 202236 kb
Host smart-d2ee27ec-a44e-413f-a0e3-2d843410b292
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827518604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_erro
rs.2827518604
Directory /workspace/11.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2898021433
Short name T863
Test name
Test status
Simulation time 2159009116 ps
CPU time 4.26 seconds
Started Jul 21 06:33:13 PM PDT 24
Finished Jul 21 06:33:19 PM PDT 24
Peak memory 202300 kb
Host smart-179df499-8014-4de3-86c5-308e917bca77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898021433 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2898021433
Directory /workspace/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1228899144
Short name T268
Test name
Test status
Simulation time 2057886982 ps
CPU time 5.91 seconds
Started Jul 21 06:33:15 PM PDT 24
Finished Jul 21 06:33:23 PM PDT 24
Peak memory 201880 kb
Host smart-c3f0e5bd-b574-42b6-89f0-93d19719e92e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228899144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_
rw.1228899144
Directory /workspace/12.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1909679807
Short name T804
Test name
Test status
Simulation time 2069588868 ps
CPU time 1.13 seconds
Started Jul 21 06:33:15 PM PDT 24
Finished Jul 21 06:33:17 PM PDT 24
Peak memory 201688 kb
Host smart-262cbab1-5eb2-42d3-b792-35c6f2392b9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909679807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_te
st.1909679807
Directory /workspace/12.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3439974291
Short name T885
Test name
Test status
Simulation time 4969769836 ps
CPU time 4.29 seconds
Started Jul 21 06:33:13 PM PDT 24
Finished Jul 21 06:33:19 PM PDT 24
Peak memory 202148 kb
Host smart-a10b37e3-ac44-4b29-b724-0920053ae7c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439974291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_same_csr_outstanding.3439974291
Directory /workspace/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2867470953
Short name T912
Test name
Test status
Simulation time 3085160023 ps
CPU time 2.41 seconds
Started Jul 21 06:33:22 PM PDT 24
Finished Jul 21 06:33:27 PM PDT 24
Peak memory 202164 kb
Host smart-30a6e551-7c7c-4e94-9c68-45ff372e0264
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867470953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_erro
rs.2867470953
Directory /workspace/12.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.221678096
Short name T832
Test name
Test status
Simulation time 22274847282 ps
CPU time 16.19 seconds
Started Jul 21 06:33:14 PM PDT 24
Finished Jul 21 06:33:32 PM PDT 24
Peak memory 202228 kb
Host smart-f454eda5-a240-4a54-bb66-fb007449ee17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221678096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_tl_intg_err.221678096
Directory /workspace/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1362988085
Short name T814
Test name
Test status
Simulation time 2165253438 ps
CPU time 4.38 seconds
Started Jul 21 06:33:16 PM PDT 24
Finished Jul 21 06:33:21 PM PDT 24
Peak memory 202284 kb
Host smart-94b22cc8-e920-4997-a8ec-c9ffd2d82b90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362988085 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1362988085
Directory /workspace/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3371607599
Short name T328
Test name
Test status
Simulation time 2072872831 ps
CPU time 3.48 seconds
Started Jul 21 06:33:14 PM PDT 24
Finished Jul 21 06:33:18 PM PDT 24
Peak memory 201920 kb
Host smart-3efe3191-0a58-4d38-9b8f-ab4443c9a4e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371607599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_
rw.3371607599
Directory /workspace/13.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3370395253
Short name T875
Test name
Test status
Simulation time 2014382193 ps
CPU time 3.39 seconds
Started Jul 21 06:33:13 PM PDT 24
Finished Jul 21 06:33:16 PM PDT 24
Peak memory 201784 kb
Host smart-1e1c4194-7ca1-4fa5-8ed1-6271771fbf66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370395253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_te
st.3370395253
Directory /workspace/13.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2277039582
Short name T905
Test name
Test status
Simulation time 9460314801 ps
CPU time 32.15 seconds
Started Jul 21 06:33:20 PM PDT 24
Finished Jul 21 06:33:55 PM PDT 24
Peak memory 202228 kb
Host smart-b34d592d-0d24-43d1-8bd1-f62a95ce86f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277039582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_same_csr_outstanding.2277039582
Directory /workspace/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2051249651
Short name T285
Test name
Test status
Simulation time 2085045905 ps
CPU time 3.88 seconds
Started Jul 21 06:33:13 PM PDT 24
Finished Jul 21 06:33:18 PM PDT 24
Peak memory 202092 kb
Host smart-ba335292-a5bd-4e97-bcb3-3c807a8d3bca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051249651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_erro
rs.2051249651
Directory /workspace/13.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.704128308
Short name T890
Test name
Test status
Simulation time 22279856429 ps
CPU time 14.95 seconds
Started Jul 21 06:33:12 PM PDT 24
Finished Jul 21 06:33:27 PM PDT 24
Peak memory 202296 kb
Host smart-d28475fd-0244-484e-aa26-12d363ae4dba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704128308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_c
trl_tl_intg_err.704128308
Directory /workspace/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1803066813
Short name T27
Test name
Test status
Simulation time 2120893671 ps
CPU time 2.32 seconds
Started Jul 21 06:33:22 PM PDT 24
Finished Jul 21 06:33:27 PM PDT 24
Peak memory 201932 kb
Host smart-1b81f3f7-bcf0-4d3a-b158-ef2fc0de3125
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803066813 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1803066813
Directory /workspace/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1412605197
Short name T324
Test name
Test status
Simulation time 2113631864 ps
CPU time 2.13 seconds
Started Jul 21 06:33:15 PM PDT 24
Finished Jul 21 06:33:19 PM PDT 24
Peak memory 201908 kb
Host smart-870a7cb9-c768-440c-9d0b-b25ac6437829
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412605197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_
rw.1412605197
Directory /workspace/14.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1443715494
Short name T798
Test name
Test status
Simulation time 2013646014 ps
CPU time 5.72 seconds
Started Jul 21 06:33:15 PM PDT 24
Finished Jul 21 06:33:22 PM PDT 24
Peak memory 201776 kb
Host smart-e0d5457b-68ec-4dab-802b-940e55b73ab5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443715494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_te
st.1443715494
Directory /workspace/14.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.423045524
Short name T897
Test name
Test status
Simulation time 9142291799 ps
CPU time 7.12 seconds
Started Jul 21 06:33:14 PM PDT 24
Finished Jul 21 06:33:23 PM PDT 24
Peak memory 202288 kb
Host smart-b7e18082-a861-416c-9a10-fee74d88b952
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423045524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.sysrst_ctrl_same_csr_outstanding.423045524
Directory /workspace/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1543683818
Short name T877
Test name
Test status
Simulation time 2502240495 ps
CPU time 2.47 seconds
Started Jul 21 06:33:14 PM PDT 24
Finished Jul 21 06:33:18 PM PDT 24
Peak memory 202228 kb
Host smart-407e8bcc-c272-4dcf-94f2-d76a137dc079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543683818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_erro
rs.1543683818
Directory /workspace/14.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2010089637
Short name T265
Test name
Test status
Simulation time 42512886071 ps
CPU time 63.35 seconds
Started Jul 21 06:33:13 PM PDT 24
Finished Jul 21 06:34:17 PM PDT 24
Peak memory 202204 kb
Host smart-5c850700-fda9-4c54-9f3e-55562035ef48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010089637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_
ctrl_tl_intg_err.2010089637
Directory /workspace/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3656066004
Short name T809
Test name
Test status
Simulation time 2076601440 ps
CPU time 2.1 seconds
Started Jul 21 06:33:21 PM PDT 24
Finished Jul 21 06:33:26 PM PDT 24
Peak memory 201932 kb
Host smart-83603d1d-87ee-48bd-84bd-4be8bf438055
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656066004 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3656066004
Directory /workspace/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.955227591
Short name T317
Test name
Test status
Simulation time 2049478205 ps
CPU time 5.86 seconds
Started Jul 21 06:33:22 PM PDT 24
Finished Jul 21 06:33:31 PM PDT 24
Peak memory 201788 kb
Host smart-fca749ab-ebb1-4238-bb86-f1313fb0b17a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955227591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_r
w.955227591
Directory /workspace/15.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2011241446
Short name T826
Test name
Test status
Simulation time 2018865548 ps
CPU time 3.09 seconds
Started Jul 21 06:33:14 PM PDT 24
Finished Jul 21 06:33:19 PM PDT 24
Peak memory 201608 kb
Host smart-b7f81317-bca3-4fa5-aaf0-3b99cb96b5ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011241446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_te
st.2011241446
Directory /workspace/15.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3891080992
Short name T271
Test name
Test status
Simulation time 2047611661 ps
CPU time 4.06 seconds
Started Jul 21 06:33:14 PM PDT 24
Finished Jul 21 06:33:20 PM PDT 24
Peak memory 202024 kb
Host smart-995851ef-2945-4312-a0fa-7d14c894f2a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891080992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_erro
rs.3891080992
Directory /workspace/15.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3954663270
Short name T818
Test name
Test status
Simulation time 2154051715 ps
CPU time 3.2 seconds
Started Jul 21 06:33:22 PM PDT 24
Finished Jul 21 06:33:27 PM PDT 24
Peak memory 202268 kb
Host smart-9b2ab847-6953-4794-9f42-c350a3efe930
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954663270 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3954663270
Directory /workspace/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2325473127
Short name T323
Test name
Test status
Simulation time 2077113676 ps
CPU time 2.06 seconds
Started Jul 21 06:33:21 PM PDT 24
Finished Jul 21 06:33:26 PM PDT 24
Peak memory 201928 kb
Host smart-cf318251-c4ad-4775-a5d9-b20b89ec294b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325473127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_
rw.2325473127
Directory /workspace/16.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3370092739
Short name T824
Test name
Test status
Simulation time 2012484189 ps
CPU time 5.66 seconds
Started Jul 21 06:33:20 PM PDT 24
Finished Jul 21 06:33:26 PM PDT 24
Peak memory 201644 kb
Host smart-267b8cbf-fe6f-4403-9094-691679bd21d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370092739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_te
st.3370092739
Directory /workspace/16.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3455584079
Short name T850
Test name
Test status
Simulation time 9081414429 ps
CPU time 29.96 seconds
Started Jul 21 06:33:23 PM PDT 24
Finished Jul 21 06:33:55 PM PDT 24
Peak memory 202232 kb
Host smart-66dc1612-7b50-4e41-88f2-ffe13e6b648a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455584079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_same_csr_outstanding.3455584079
Directory /workspace/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1662258159
Short name T266
Test name
Test status
Simulation time 2188202393 ps
CPU time 4.25 seconds
Started Jul 21 06:33:21 PM PDT 24
Finished Jul 21 06:33:28 PM PDT 24
Peak memory 202204 kb
Host smart-88e55fbb-91cd-44e4-858a-bb470ec83845
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662258159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_erro
rs.1662258159
Directory /workspace/16.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3173324844
Short name T261
Test name
Test status
Simulation time 42505870130 ps
CPU time 83.25 seconds
Started Jul 21 06:33:21 PM PDT 24
Finished Jul 21 06:34:47 PM PDT 24
Peak memory 202176 kb
Host smart-437c4c1b-f10b-4563-9c21-2905ee062ac5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173324844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_tl_intg_err.3173324844
Directory /workspace/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.4911933
Short name T901
Test name
Test status
Simulation time 2112529376 ps
CPU time 6.6 seconds
Started Jul 21 06:33:19 PM PDT 24
Finished Jul 21 06:33:26 PM PDT 24
Peak memory 201924 kb
Host smart-da9638e0-5fee-41bd-ad46-3a81a33a2ac4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4911933 -assert nopostproc +UVM_TESTNAME=sy
srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_mem_rw_with_rand_reset.4911933
Directory /workspace/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2993879177
Short name T862
Test name
Test status
Simulation time 2061967860 ps
CPU time 5.77 seconds
Started Jul 21 06:33:23 PM PDT 24
Finished Jul 21 06:33:31 PM PDT 24
Peak memory 201812 kb
Host smart-1b4da1f8-2fdb-4793-9752-7451342dd7a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993879177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_
rw.2993879177
Directory /workspace/17.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.4071711962
Short name T860
Test name
Test status
Simulation time 2023937928 ps
CPU time 3 seconds
Started Jul 21 06:33:23 PM PDT 24
Finished Jul 21 06:33:29 PM PDT 24
Peak memory 201640 kb
Host smart-a0ba572b-ce9d-488a-921c-5a772d4669e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071711962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_te
st.4071711962
Directory /workspace/17.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2075708509
Short name T853
Test name
Test status
Simulation time 4400364543 ps
CPU time 6.42 seconds
Started Jul 21 06:33:22 PM PDT 24
Finished Jul 21 06:33:31 PM PDT 24
Peak memory 202004 kb
Host smart-645a0859-9a83-400b-bb17-36eb9c7f9d5e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075708509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
7.sysrst_ctrl_same_csr_outstanding.2075708509
Directory /workspace/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1111123905
Short name T836
Test name
Test status
Simulation time 2047252657 ps
CPU time 3.86 seconds
Started Jul 21 06:33:18 PM PDT 24
Finished Jul 21 06:33:22 PM PDT 24
Peak memory 202032 kb
Host smart-f157b529-85b2-49c8-83d7-205158f05893
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111123905 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_erro
rs.1111123905
Directory /workspace/17.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3251593852
Short name T280
Test name
Test status
Simulation time 22682207064 ps
CPU time 11.39 seconds
Started Jul 21 06:33:20 PM PDT 24
Finished Jul 21 06:33:34 PM PDT 24
Peak memory 202228 kb
Host smart-bccccf62-48b8-44ec-a03e-8c42604c81b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251593852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_tl_intg_err.3251593852
Directory /workspace/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.930817601
Short name T827
Test name
Test status
Simulation time 2049439245 ps
CPU time 6.28 seconds
Started Jul 21 06:33:20 PM PDT 24
Finished Jul 21 06:33:29 PM PDT 24
Peak memory 201832 kb
Host smart-4cbdc4ba-f684-4267-9ed3-3f8e8c9d57d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930817601 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_mem_rw_with_rand_reset.930817601
Directory /workspace/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3355442136
Short name T843
Test name
Test status
Simulation time 2108449846 ps
CPU time 2.09 seconds
Started Jul 21 06:33:23 PM PDT 24
Finished Jul 21 06:33:28 PM PDT 24
Peak memory 201880 kb
Host smart-5d161c4d-c9fa-442b-b83f-3f9fc5c41437
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355442136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_
rw.3355442136
Directory /workspace/18.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.118395230
Short name T846
Test name
Test status
Simulation time 2012683152 ps
CPU time 5.66 seconds
Started Jul 21 06:33:21 PM PDT 24
Finished Jul 21 06:33:29 PM PDT 24
Peak memory 201516 kb
Host smart-ab563209-2058-43cd-8784-454a1bb0470f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118395230 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_tes
t.118395230
Directory /workspace/18.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3509435465
Short name T18
Test name
Test status
Simulation time 4948245108 ps
CPU time 12.68 seconds
Started Jul 21 06:33:18 PM PDT 24
Finished Jul 21 06:33:32 PM PDT 24
Peak memory 202216 kb
Host smart-cd6663f8-02a3-4b98-8766-a292058cc569
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509435465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_same_csr_outstanding.3509435465
Directory /workspace/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2345856222
Short name T869
Test name
Test status
Simulation time 2246907968 ps
CPU time 5.39 seconds
Started Jul 21 06:33:19 PM PDT 24
Finished Jul 21 06:33:25 PM PDT 24
Peak memory 202280 kb
Host smart-10259fba-6930-44eb-9cfb-075ac6368e74
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345856222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_erro
rs.2345856222
Directory /workspace/18.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2532879467
Short name T274
Test name
Test status
Simulation time 22397308758 ps
CPU time 15.6 seconds
Started Jul 21 06:33:19 PM PDT 24
Finished Jul 21 06:33:36 PM PDT 24
Peak memory 202268 kb
Host smart-01d1c2a2-5430-43a9-94c7-e1b2c4a60f22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532879467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_tl_intg_err.2532879467
Directory /workspace/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.990120426
Short name T883
Test name
Test status
Simulation time 2206343422 ps
CPU time 1.45 seconds
Started Jul 21 06:33:23 PM PDT 24
Finished Jul 21 06:33:26 PM PDT 24
Peak memory 202052 kb
Host smart-1b0fe35c-7e14-4aaa-b038-2b73716e556b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990120426 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_mem_rw_with_rand_reset.990120426
Directory /workspace/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3369296340
Short name T321
Test name
Test status
Simulation time 2071054791 ps
CPU time 2.11 seconds
Started Jul 21 06:33:24 PM PDT 24
Finished Jul 21 06:33:28 PM PDT 24
Peak memory 201788 kb
Host smart-d391593f-4b02-42aa-a4ee-278868bacfa3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369296340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_
rw.3369296340
Directory /workspace/19.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.4009357940
Short name T823
Test name
Test status
Simulation time 2013788803 ps
CPU time 5.68 seconds
Started Jul 21 06:33:21 PM PDT 24
Finished Jul 21 06:33:30 PM PDT 24
Peak memory 201616 kb
Host smart-0624245b-bcbe-4515-9da5-2f1ce46c09b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009357940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_te
st.4009357940
Directory /workspace/19.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3316951289
Short name T855
Test name
Test status
Simulation time 4650242229 ps
CPU time 11.42 seconds
Started Jul 21 06:33:22 PM PDT 24
Finished Jul 21 06:33:36 PM PDT 24
Peak memory 202000 kb
Host smart-71150339-c89b-4404-9b1d-d2ed9c914cd0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316951289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_same_csr_outstanding.3316951289
Directory /workspace/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3716401335
Short name T828
Test name
Test status
Simulation time 2123627459 ps
CPU time 3.13 seconds
Started Jul 21 06:33:21 PM PDT 24
Finished Jul 21 06:33:27 PM PDT 24
Peak memory 202076 kb
Host smart-4b9ced9a-c3cd-47d4-a52e-4c8751cd2a55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716401335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_erro
rs.3716401335
Directory /workspace/19.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.3795456937
Short name T277
Test name
Test status
Simulation time 22726471502 ps
CPU time 12.08 seconds
Started Jul 21 06:33:20 PM PDT 24
Finished Jul 21 06:33:33 PM PDT 24
Peak memory 202200 kb
Host smart-2fecd67d-a1b2-41c7-8c53-698d2174ff07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795456937 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_tl_intg_err.3795456937
Directory /workspace/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.1206583858
Short name T325
Test name
Test status
Simulation time 2386731988 ps
CPU time 8.41 seconds
Started Jul 21 06:33:00 PM PDT 24
Finished Jul 21 06:33:12 PM PDT 24
Peak memory 202244 kb
Host smart-f1801df8-cb14-4ab3-8387-61833de841d1
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206583858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_aliasing.1206583858
Directory /workspace/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2453928898
Short name T319
Test name
Test status
Simulation time 22715254230 ps
CPU time 58.24 seconds
Started Jul 21 06:33:02 PM PDT 24
Finished Jul 21 06:34:03 PM PDT 24
Peak memory 202252 kb
Host smart-364a0b1a-06b4-43e0-9032-6b24dd3e185e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453928898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_bit_bash.2453928898
Directory /workspace/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1176727056
Short name T316
Test name
Test status
Simulation time 6046616913 ps
CPU time 7.38 seconds
Started Jul 21 06:33:06 PM PDT 24
Finished Jul 21 06:33:16 PM PDT 24
Peak memory 201916 kb
Host smart-bb64f502-83fb-4dc2-9be2-f90b606ea970
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176727056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl
_csr_hw_reset.1176727056
Directory /workspace/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2389779521
Short name T28
Test name
Test status
Simulation time 2638057590 ps
CPU time 1.54 seconds
Started Jul 21 06:33:01 PM PDT 24
Finished Jul 21 06:33:06 PM PDT 24
Peak memory 210376 kb
Host smart-8d722480-7e71-4bf6-9558-2c7272daad36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389779521 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2389779521
Directory /workspace/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2646149854
Short name T878
Test name
Test status
Simulation time 2052786761 ps
CPU time 5.91 seconds
Started Jul 21 06:33:04 PM PDT 24
Finished Jul 21 06:33:12 PM PDT 24
Peak memory 201920 kb
Host smart-b33514b5-62ba-40d2-a195-e29b9cfb2678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646149854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_r
w.2646149854
Directory /workspace/2.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2431332315
Short name T806
Test name
Test status
Simulation time 2014250691 ps
CPU time 5.74 seconds
Started Jul 21 06:33:03 PM PDT 24
Finished Jul 21 06:33:12 PM PDT 24
Peak memory 201740 kb
Host smart-02629f46-5bcc-4ccc-ac93-d0afa23f3759
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431332315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_tes
t.2431332315
Directory /workspace/2.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3062198702
Short name T867
Test name
Test status
Simulation time 8395018196 ps
CPU time 22.6 seconds
Started Jul 21 06:33:03 PM PDT 24
Finished Jul 21 06:33:28 PM PDT 24
Peak memory 202220 kb
Host smart-b0171614-c228-4181-8bb7-06f51500bf1d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062198702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_same_csr_outstanding.3062198702
Directory /workspace/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.900293715
Short name T856
Test name
Test status
Simulation time 2435045280 ps
CPU time 3.41 seconds
Started Jul 21 06:33:08 PM PDT 24
Finished Jul 21 06:33:14 PM PDT 24
Peak memory 202268 kb
Host smart-6f6dd0ff-1054-4205-86a0-a2ab2d7dab92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900293715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors
.900293715
Directory /workspace/2.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1781287653
Short name T284
Test name
Test status
Simulation time 42535465440 ps
CPU time 27.05 seconds
Started Jul 21 06:33:01 PM PDT 24
Finished Jul 21 06:33:31 PM PDT 24
Peak memory 202256 kb
Host smart-34543083-223f-486d-a669-5ed5e8eef5cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781287653 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_tl_intg_err.1781287653
Directory /workspace/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.531049734
Short name T874
Test name
Test status
Simulation time 2017606859 ps
CPU time 3.25 seconds
Started Jul 21 06:33:23 PM PDT 24
Finished Jul 21 06:33:28 PM PDT 24
Peak memory 201648 kb
Host smart-5561ebf3-1a6b-4a95-a4a4-0ed604135460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531049734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_tes
t.531049734
Directory /workspace/20.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1561796912
Short name T807
Test name
Test status
Simulation time 2012517823 ps
CPU time 5.52 seconds
Started Jul 21 06:33:19 PM PDT 24
Finished Jul 21 06:33:26 PM PDT 24
Peak memory 201624 kb
Host smart-19737283-6f51-4cc2-a203-18c4319dfe4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561796912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_te
st.1561796912
Directory /workspace/21.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1244006469
Short name T816
Test name
Test status
Simulation time 2009810498 ps
CPU time 5.62 seconds
Started Jul 21 06:33:21 PM PDT 24
Finished Jul 21 06:33:29 PM PDT 24
Peak memory 201592 kb
Host smart-e79d1782-7156-42c4-9e70-195c6044889a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244006469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_te
st.1244006469
Directory /workspace/22.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.59685085
Short name T873
Test name
Test status
Simulation time 2032877778 ps
CPU time 1.92 seconds
Started Jul 21 06:33:22 PM PDT 24
Finished Jul 21 06:33:26 PM PDT 24
Peak memory 201688 kb
Host smart-f2816b8b-3d1d-4504-b31c-cf92e0f4640f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59685085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test
.59685085
Directory /workspace/23.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.760352317
Short name T833
Test name
Test status
Simulation time 2052105529 ps
CPU time 1.74 seconds
Started Jul 21 06:33:21 PM PDT 24
Finished Jul 21 06:33:26 PM PDT 24
Peak memory 201780 kb
Host smart-2adaafd2-22f5-4595-b4a0-b47c6aafde8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760352317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_tes
t.760352317
Directory /workspace/24.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1282232322
Short name T915
Test name
Test status
Simulation time 2015972819 ps
CPU time 5.51 seconds
Started Jul 21 06:33:19 PM PDT 24
Finished Jul 21 06:33:26 PM PDT 24
Peak memory 201676 kb
Host smart-e9fa3a6e-6973-4692-ac58-8fb9b3714d3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282232322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_te
st.1282232322
Directory /workspace/25.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3617097288
Short name T847
Test name
Test status
Simulation time 2008882020 ps
CPU time 6.2 seconds
Started Jul 21 06:33:21 PM PDT 24
Finished Jul 21 06:33:29 PM PDT 24
Peak memory 201536 kb
Host smart-9194b312-03c7-4b75-b6c1-7114b8cdfa27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617097288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_te
st.3617097288
Directory /workspace/26.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3863738225
Short name T898
Test name
Test status
Simulation time 2017339393 ps
CPU time 3.14 seconds
Started Jul 21 06:33:23 PM PDT 24
Finished Jul 21 06:33:28 PM PDT 24
Peak memory 201612 kb
Host smart-97a8018f-a38f-4f07-9620-0ba992cba2ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863738225 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_te
st.3863738225
Directory /workspace/27.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1919130349
Short name T849
Test name
Test status
Simulation time 2013687721 ps
CPU time 5.51 seconds
Started Jul 21 06:33:19 PM PDT 24
Finished Jul 21 06:33:25 PM PDT 24
Peak memory 201576 kb
Host smart-813667e5-f85d-4ab7-bd35-497e0cd70984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919130349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_te
st.1919130349
Directory /workspace/28.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.954661837
Short name T889
Test name
Test status
Simulation time 2097895236 ps
CPU time 0.96 seconds
Started Jul 21 06:33:21 PM PDT 24
Finished Jul 21 06:33:25 PM PDT 24
Peak memory 201628 kb
Host smart-f98d3847-630a-49be-a0e8-0870625ed098
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954661837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_tes
t.954661837
Directory /workspace/29.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.465081711
Short name T270
Test name
Test status
Simulation time 2721755248 ps
CPU time 5.63 seconds
Started Jul 21 06:33:01 PM PDT 24
Finished Jul 21 06:33:09 PM PDT 24
Peak memory 202188 kb
Host smart-51078b11-b054-488d-ae88-2e959cebe20e
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465081711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_
csr_aliasing.465081711
Directory /workspace/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1424158462
Short name T871
Test name
Test status
Simulation time 6074103977 ps
CPU time 4.39 seconds
Started Jul 21 06:33:04 PM PDT 24
Finished Jul 21 06:33:11 PM PDT 24
Peak memory 201924 kb
Host smart-a79f709f-cd75-4a24-a6b3-4789d08cdf4d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424158462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl
_csr_hw_reset.1424158462
Directory /workspace/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.647327263
Short name T882
Test name
Test status
Simulation time 2138857786 ps
CPU time 3.56 seconds
Started Jul 21 06:33:01 PM PDT 24
Finished Jul 21 06:33:08 PM PDT 24
Peak memory 202144 kb
Host smart-46a1a10d-70ca-4c42-9018-313b550741db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647327263 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to
p.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_mem_rw_with_rand_reset.647327263
Directory /workspace/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1817793899
Short name T899
Test name
Test status
Simulation time 2039331602 ps
CPU time 5.84 seconds
Started Jul 21 06:33:02 PM PDT 24
Finished Jul 21 06:33:10 PM PDT 24
Peak memory 201880 kb
Host smart-b00d90a3-a607-48eb-9c92-a981332345f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817793899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_r
w.1817793899
Directory /workspace/3.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3086166316
Short name T872
Test name
Test status
Simulation time 2060286921 ps
CPU time 1.22 seconds
Started Jul 21 06:33:02 PM PDT 24
Finished Jul 21 06:33:06 PM PDT 24
Peak memory 201788 kb
Host smart-3aeb07bf-8901-4985-9836-c7642e2104f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086166316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_tes
t.3086166316
Directory /workspace/3.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.780209822
Short name T19
Test name
Test status
Simulation time 7211498140 ps
CPU time 4.22 seconds
Started Jul 21 06:33:05 PM PDT 24
Finished Jul 21 06:33:11 PM PDT 24
Peak memory 202196 kb
Host smart-fa204786-04f8-46c4-8b49-524cb88328d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780209822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
sysrst_ctrl_same_csr_outstanding.780209822
Directory /workspace/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1063585892
Short name T276
Test name
Test status
Simulation time 42495413591 ps
CPU time 28.34 seconds
Started Jul 21 06:33:03 PM PDT 24
Finished Jul 21 06:33:34 PM PDT 24
Peak memory 202208 kb
Host smart-1264788e-4bec-45ae-9816-839afffc0519
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063585892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_tl_intg_err.1063585892
Directory /workspace/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2637116428
Short name T805
Test name
Test status
Simulation time 2036067769 ps
CPU time 1.9 seconds
Started Jul 21 06:33:28 PM PDT 24
Finished Jul 21 06:33:33 PM PDT 24
Peak memory 201636 kb
Host smart-a93bb0eb-ea40-4676-a5f2-1173431f9d48
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637116428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_te
st.2637116428
Directory /workspace/30.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2141767009
Short name T812
Test name
Test status
Simulation time 2012093443 ps
CPU time 5.59 seconds
Started Jul 21 06:33:29 PM PDT 24
Finished Jul 21 06:33:37 PM PDT 24
Peak memory 201620 kb
Host smart-1b01fcff-20bf-4840-afcf-6a21ea73bba0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141767009 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_te
st.2141767009
Directory /workspace/31.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3678671572
Short name T839
Test name
Test status
Simulation time 2024138840 ps
CPU time 3.18 seconds
Started Jul 21 06:33:25 PM PDT 24
Finished Jul 21 06:33:30 PM PDT 24
Peak memory 201776 kb
Host smart-1f459783-dda5-4210-b83c-64de9725427f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678671572 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_te
st.3678671572
Directory /workspace/32.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1208080209
Short name T819
Test name
Test status
Simulation time 2011435461 ps
CPU time 4.06 seconds
Started Jul 21 06:33:26 PM PDT 24
Finished Jul 21 06:33:32 PM PDT 24
Peak memory 201616 kb
Host smart-d1945ed5-1e83-4d91-8e32-1adf8205d7a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208080209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_te
st.1208080209
Directory /workspace/33.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3597470832
Short name T852
Test name
Test status
Simulation time 2014573849 ps
CPU time 5.62 seconds
Started Jul 21 06:33:29 PM PDT 24
Finished Jul 21 06:33:38 PM PDT 24
Peak memory 201792 kb
Host smart-f05905bf-dc1d-448d-b110-11243d0ab1d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597470832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_te
st.3597470832
Directory /workspace/34.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2362178432
Short name T896
Test name
Test status
Simulation time 2012051994 ps
CPU time 5.47 seconds
Started Jul 21 06:33:26 PM PDT 24
Finished Jul 21 06:33:33 PM PDT 24
Peak memory 201736 kb
Host smart-49f0a609-3feb-4c20-b150-c0a929bac7a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362178432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_te
st.2362178432
Directory /workspace/35.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1669360588
Short name T914
Test name
Test status
Simulation time 2017191873 ps
CPU time 5.56 seconds
Started Jul 21 06:33:25 PM PDT 24
Finished Jul 21 06:33:33 PM PDT 24
Peak memory 201604 kb
Host smart-b6076eac-2124-49ce-bf6b-e82c7ec8bd2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669360588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_te
st.1669360588
Directory /workspace/36.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.937082812
Short name T848
Test name
Test status
Simulation time 2011319049 ps
CPU time 5.35 seconds
Started Jul 21 06:33:28 PM PDT 24
Finished Jul 21 06:33:36 PM PDT 24
Peak memory 201780 kb
Host smart-3c387102-106a-4b96-b3cf-ddf7deeed12b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937082812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_tes
t.937082812
Directory /workspace/37.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.701300830
Short name T813
Test name
Test status
Simulation time 2044964707 ps
CPU time 2.01 seconds
Started Jul 21 06:33:26 PM PDT 24
Finished Jul 21 06:33:30 PM PDT 24
Peak memory 201812 kb
Host smart-e9c65482-4111-4199-b362-1e1f7f95f1ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701300830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_tes
t.701300830
Directory /workspace/38.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.2203499524
Short name T854
Test name
Test status
Simulation time 2146677756 ps
CPU time 1.01 seconds
Started Jul 21 06:33:27 PM PDT 24
Finished Jul 21 06:33:31 PM PDT 24
Peak memory 201696 kb
Host smart-f26a932f-0fae-40c8-b0f3-9decee0f5cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203499524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_te
st.2203499524
Directory /workspace/39.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.2252406736
Short name T820
Test name
Test status
Simulation time 2697492017 ps
CPU time 4 seconds
Started Jul 21 06:33:02 PM PDT 24
Finished Jul 21 06:33:09 PM PDT 24
Peak memory 202144 kb
Host smart-fa072c30-ddbb-4c95-aec3-5bef91567996
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252406736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_aliasing.2252406736
Directory /workspace/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2332855756
Short name T835
Test name
Test status
Simulation time 39497261372 ps
CPU time 138.88 seconds
Started Jul 21 06:33:06 PM PDT 24
Finished Jul 21 06:35:27 PM PDT 24
Peak memory 202176 kb
Host smart-55aeca3a-8766-4d82-aca3-4855bdad9de3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332855756 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_bit_bash.2332855756
Directory /workspace/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1597577709
Short name T910
Test name
Test status
Simulation time 6054018098 ps
CPU time 4.62 seconds
Started Jul 21 06:33:00 PM PDT 24
Finished Jul 21 06:33:08 PM PDT 24
Peak memory 202040 kb
Host smart-74c3038f-b053-4da7-96bb-746a9114d030
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597577709 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl
_csr_hw_reset.1597577709
Directory /workspace/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.4016714738
Short name T29
Test name
Test status
Simulation time 2163029840 ps
CPU time 2.29 seconds
Started Jul 21 06:33:01 PM PDT 24
Finished Jul 21 06:33:07 PM PDT 24
Peak memory 202164 kb
Host smart-285941de-1ecd-4c85-8408-0e7f3256e460
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016714738 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_mem_rw_with_rand_reset.4016714738
Directory /workspace/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.2858713180
Short name T329
Test name
Test status
Simulation time 2066659673 ps
CPU time 2.06 seconds
Started Jul 21 06:33:03 PM PDT 24
Finished Jul 21 06:33:08 PM PDT 24
Peak memory 201764 kb
Host smart-75b2fea3-1d9a-440c-a30b-22d8ec5b8f09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858713180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_r
w.2858713180
Directory /workspace/4.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.3821526364
Short name T851
Test name
Test status
Simulation time 2020626547 ps
CPU time 3.26 seconds
Started Jul 21 06:33:05 PM PDT 24
Finished Jul 21 06:33:10 PM PDT 24
Peak memory 201672 kb
Host smart-c964d1c7-4922-4c64-ad1c-b993bded8536
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821526364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_tes
t.3821526364
Directory /workspace/4.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.930343392
Short name T830
Test name
Test status
Simulation time 7803095964 ps
CPU time 7.93 seconds
Started Jul 21 06:33:08 PM PDT 24
Finished Jul 21 06:33:18 PM PDT 24
Peak memory 202164 kb
Host smart-7f7ec2b2-d4bb-4052-a659-f671b12056bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930343392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
sysrst_ctrl_same_csr_outstanding.930343392
Directory /workspace/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.13855841
Short name T279
Test name
Test status
Simulation time 2038894729 ps
CPU time 6.12 seconds
Started Jul 21 06:33:07 PM PDT 24
Finished Jul 21 06:33:15 PM PDT 24
Peak memory 202000 kb
Host smart-62cea667-9b02-4ba2-9b3a-013d2a0450cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13855841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.13855841
Directory /workspace/4.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.872730728
Short name T904
Test name
Test status
Simulation time 22235255161 ps
CPU time 62.66 seconds
Started Jul 21 06:33:02 PM PDT 24
Finished Jul 21 06:34:07 PM PDT 24
Peak memory 202248 kb
Host smart-2053a0c5-5e6f-41e4-aaf4-164e869d0be9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872730728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_tl_intg_err.872730728
Directory /workspace/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.298681707
Short name T803
Test name
Test status
Simulation time 2039653598 ps
CPU time 1.48 seconds
Started Jul 21 06:33:27 PM PDT 24
Finished Jul 21 06:33:31 PM PDT 24
Peak memory 201632 kb
Host smart-c536de9b-1a13-4f92-8318-371753a024d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298681707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_tes
t.298681707
Directory /workspace/40.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.3025117836
Short name T900
Test name
Test status
Simulation time 2013556821 ps
CPU time 5.96 seconds
Started Jul 21 06:33:26 PM PDT 24
Finished Jul 21 06:33:34 PM PDT 24
Peak memory 201716 kb
Host smart-1b39c0ba-1c3c-461a-8721-d39b9457fbd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025117836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_te
st.3025117836
Directory /workspace/41.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.2872534085
Short name T817
Test name
Test status
Simulation time 2020522120 ps
CPU time 3.3 seconds
Started Jul 21 06:33:28 PM PDT 24
Finished Jul 21 06:33:34 PM PDT 24
Peak memory 201604 kb
Host smart-7838db25-1224-43f5-9e40-9f56868682e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872534085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_te
st.2872534085
Directory /workspace/42.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.2056590456
Short name T801
Test name
Test status
Simulation time 2012173662 ps
CPU time 5.33 seconds
Started Jul 21 06:33:25 PM PDT 24
Finished Jul 21 06:33:32 PM PDT 24
Peak memory 201648 kb
Host smart-22aa355b-62a5-4ffe-89a9-e517662eb5c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056590456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_te
st.2056590456
Directory /workspace/43.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1246425032
Short name T891
Test name
Test status
Simulation time 2045422446 ps
CPU time 1.9 seconds
Started Jul 21 06:33:25 PM PDT 24
Finished Jul 21 06:33:29 PM PDT 24
Peak memory 201588 kb
Host smart-2f601a42-5a8f-4513-85a2-324e9c278e3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246425032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_te
st.1246425032
Directory /workspace/44.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3849938395
Short name T811
Test name
Test status
Simulation time 2022788124 ps
CPU time 3.11 seconds
Started Jul 21 06:33:27 PM PDT 24
Finished Jul 21 06:33:32 PM PDT 24
Peak memory 201676 kb
Host smart-7cf8b86d-9b13-451f-9d88-7a563bab7bac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849938395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_te
st.3849938395
Directory /workspace/45.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.139559214
Short name T884
Test name
Test status
Simulation time 2026753177 ps
CPU time 3.15 seconds
Started Jul 21 06:33:27 PM PDT 24
Finished Jul 21 06:33:32 PM PDT 24
Peak memory 201628 kb
Host smart-c0a7eab3-3e29-4f86-82ad-3fad3966c071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139559214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_tes
t.139559214
Directory /workspace/46.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.3173917046
Short name T799
Test name
Test status
Simulation time 2008084783 ps
CPU time 5.7 seconds
Started Jul 21 06:33:28 PM PDT 24
Finished Jul 21 06:33:37 PM PDT 24
Peak memory 201672 kb
Host smart-c6455d8f-3377-4365-bb4b-8ba3f5523370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173917046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_te
st.3173917046
Directory /workspace/47.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.20091030
Short name T808
Test name
Test status
Simulation time 2017224483 ps
CPU time 5.5 seconds
Started Jul 21 06:33:28 PM PDT 24
Finished Jul 21 06:33:36 PM PDT 24
Peak memory 201608 kb
Host smart-bcf6a654-f67a-46a1-8b61-e877dd4c2c8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20091030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test
.20091030
Directory /workspace/48.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.938709193
Short name T829
Test name
Test status
Simulation time 2010482939 ps
CPU time 5.77 seconds
Started Jul 21 06:33:30 PM PDT 24
Finished Jul 21 06:33:38 PM PDT 24
Peak memory 201664 kb
Host smart-0351606d-673f-4930-a793-d7ef88d4257d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938709193 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_tes
t.938709193
Directory /workspace/49.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1049510640
Short name T837
Test name
Test status
Simulation time 2106202593 ps
CPU time 2.42 seconds
Started Jul 21 06:33:03 PM PDT 24
Finished Jul 21 06:33:08 PM PDT 24
Peak memory 217348 kb
Host smart-bc4755c1-1ffd-4518-bef9-d30264377a54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049510640 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_mem_rw_with_rand_reset.1049510640
Directory /workspace/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.3262665317
Short name T903
Test name
Test status
Simulation time 2035061703 ps
CPU time 5.34 seconds
Started Jul 21 06:33:00 PM PDT 24
Finished Jul 21 06:33:09 PM PDT 24
Peak memory 201844 kb
Host smart-da4d71ce-bbef-4e10-8d62-bba27192b2a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262665317 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_r
w.3262665317
Directory /workspace/5.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1051741987
Short name T802
Test name
Test status
Simulation time 2062617305 ps
CPU time 1.42 seconds
Started Jul 21 06:33:05 PM PDT 24
Finished Jul 21 06:33:09 PM PDT 24
Peak memory 201796 kb
Host smart-140f362e-69f6-448a-9b34-6771e67785cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051741987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_tes
t.1051741987
Directory /workspace/5.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.995397473
Short name T888
Test name
Test status
Simulation time 5012827140 ps
CPU time 2.46 seconds
Started Jul 21 06:33:01 PM PDT 24
Finished Jul 21 06:33:07 PM PDT 24
Peak memory 202236 kb
Host smart-741ee80e-b098-4610-9b0d-aefed17a36c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995397473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
sysrst_ctrl_same_csr_outstanding.995397473
Directory /workspace/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.418165094
Short name T267
Test name
Test status
Simulation time 2065533434 ps
CPU time 6.96 seconds
Started Jul 21 06:33:04 PM PDT 24
Finished Jul 21 06:33:13 PM PDT 24
Peak memory 202068 kb
Host smart-3c7133c8-6a91-4689-8ac9-28304e17a520
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418165094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors
.418165094
Directory /workspace/5.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.2984268371
Short name T857
Test name
Test status
Simulation time 22261875245 ps
CPU time 56.07 seconds
Started Jul 21 06:33:07 PM PDT 24
Finished Jul 21 06:34:05 PM PDT 24
Peak memory 202108 kb
Host smart-a78d1548-fb9f-484c-89b0-2aefab0305c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984268371 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_tl_intg_err.2984268371
Directory /workspace/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1905270730
Short name T861
Test name
Test status
Simulation time 2581485132 ps
CPU time 1.61 seconds
Started Jul 21 06:33:13 PM PDT 24
Finished Jul 21 06:33:15 PM PDT 24
Peak memory 218056 kb
Host smart-a3803164-0c07-4fc4-b750-5e853197438c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905270730 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_mem_rw_with_rand_reset.1905270730
Directory /workspace/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.214251563
Short name T327
Test name
Test status
Simulation time 2054364175 ps
CPU time 6.04 seconds
Started Jul 21 06:33:09 PM PDT 24
Finished Jul 21 06:33:18 PM PDT 24
Peak memory 201820 kb
Host smart-0ae77161-a2be-4042-b660-4550e270ab8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214251563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw
.214251563
Directory /workspace/6.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3473486616
Short name T800
Test name
Test status
Simulation time 2010072270 ps
CPU time 5.76 seconds
Started Jul 21 06:33:09 PM PDT 24
Finished Jul 21 06:33:17 PM PDT 24
Peak memory 201608 kb
Host smart-532950ab-b73a-4336-8cff-9c460b9fd0f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473486616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_tes
t.3473486616
Directory /workspace/6.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.1671052323
Short name T831
Test name
Test status
Simulation time 4706451557 ps
CPU time 3.81 seconds
Started Jul 21 06:33:08 PM PDT 24
Finished Jul 21 06:33:14 PM PDT 24
Peak memory 201952 kb
Host smart-73a40459-95fc-4627-8765-0a844bd29ca4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671052323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6
.sysrst_ctrl_same_csr_outstanding.1671052323
Directory /workspace/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.903747848
Short name T844
Test name
Test status
Simulation time 2103144458 ps
CPU time 7.5 seconds
Started Jul 21 06:33:05 PM PDT 24
Finished Jul 21 06:33:14 PM PDT 24
Peak memory 202040 kb
Host smart-08d38b16-16c8-490a-8f12-3649c487fe98
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903747848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors
.903747848
Directory /workspace/6.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.3323775745
Short name T893
Test name
Test status
Simulation time 42456595906 ps
CPU time 113.03 seconds
Started Jul 21 06:33:03 PM PDT 24
Finished Jul 21 06:34:58 PM PDT 24
Peak memory 202168 kb
Host smart-9658f92a-41c4-42f1-990e-822ebb72ab2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323775745 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_tl_intg_err.3323775745
Directory /workspace/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3976346859
Short name T845
Test name
Test status
Simulation time 2201774383 ps
CPU time 2.44 seconds
Started Jul 21 06:33:09 PM PDT 24
Finished Jul 21 06:33:14 PM PDT 24
Peak memory 202028 kb
Host smart-2bf6e29e-197b-4a36-bedf-1a3a4463eb04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976346859 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_mem_rw_with_rand_reset.3976346859
Directory /workspace/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.1109538490
Short name T876
Test name
Test status
Simulation time 2050061337 ps
CPU time 3.47 seconds
Started Jul 21 06:33:08 PM PDT 24
Finished Jul 21 06:33:15 PM PDT 24
Peak memory 201920 kb
Host smart-0ab61878-4090-48a9-b4dc-cba845230057
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109538490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_r
w.1109538490
Directory /workspace/7.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.4106016006
Short name T838
Test name
Test status
Simulation time 2013808503 ps
CPU time 5.82 seconds
Started Jul 21 06:33:07 PM PDT 24
Finished Jul 21 06:33:15 PM PDT 24
Peak memory 201756 kb
Host smart-2e9a1d72-e672-405e-af2e-d08493a52d34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106016006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_tes
t.4106016006
Directory /workspace/7.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.2050366183
Short name T913
Test name
Test status
Simulation time 5935975058 ps
CPU time 16.06 seconds
Started Jul 21 06:33:09 PM PDT 24
Finished Jul 21 06:33:28 PM PDT 24
Peak memory 202056 kb
Host smart-5d9b1bc8-6a28-4c8d-8b47-ef37f81e7c0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050366183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_same_csr_outstanding.2050366183
Directory /workspace/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.224135125
Short name T881
Test name
Test status
Simulation time 2052267279 ps
CPU time 7.2 seconds
Started Jul 21 06:33:08 PM PDT 24
Finished Jul 21 06:33:18 PM PDT 24
Peak memory 202100 kb
Host smart-85af632b-c06b-4998-8f71-c0533575d01a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224135125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors
.224135125
Directory /workspace/7.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.2032309663
Short name T365
Test name
Test status
Simulation time 42526791500 ps
CPU time 60.1 seconds
Started Jul 21 06:33:08 PM PDT 24
Finished Jul 21 06:34:11 PM PDT 24
Peak memory 202284 kb
Host smart-f8af3220-50e0-4b04-bc33-00bd48d55244
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032309663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_tl_intg_err.2032309663
Directory /workspace/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2976538902
Short name T892
Test name
Test status
Simulation time 2055703207 ps
CPU time 6.1 seconds
Started Jul 21 06:33:06 PM PDT 24
Finished Jul 21 06:33:14 PM PDT 24
Peak memory 201920 kb
Host smart-7fc84d92-4080-44b9-972f-ec40a323669d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976538902 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2976538902
Directory /workspace/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3811330103
Short name T330
Test name
Test status
Simulation time 2140105838 ps
CPU time 1.82 seconds
Started Jul 21 06:33:14 PM PDT 24
Finished Jul 21 06:33:17 PM PDT 24
Peak memory 201528 kb
Host smart-f1304a77-551b-4829-8dd9-65482a3ab922
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811330103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_r
w.3811330103
Directory /workspace/8.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2108343515
Short name T870
Test name
Test status
Simulation time 2141986229 ps
CPU time 1 seconds
Started Jul 21 06:33:07 PM PDT 24
Finished Jul 21 06:33:11 PM PDT 24
Peak memory 201656 kb
Host smart-01142512-4b95-4741-89bb-901322bb4bce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108343515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_tes
t.2108343515
Directory /workspace/8.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.2793542634
Short name T864
Test name
Test status
Simulation time 4677765059 ps
CPU time 2.26 seconds
Started Jul 21 06:33:06 PM PDT 24
Finished Jul 21 06:33:11 PM PDT 24
Peak memory 202004 kb
Host smart-5a1695c2-2eb3-4cda-af63-d6a9c595fe96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793542634 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SE
Q=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_same_csr_outstanding.2793542634
Directory /workspace/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3692283999
Short name T895
Test name
Test status
Simulation time 2048674998 ps
CPU time 6.18 seconds
Started Jul 21 06:33:07 PM PDT 24
Finished Jul 21 06:33:15 PM PDT 24
Peak memory 202204 kb
Host smart-c1cdb634-f31e-4dae-8c20-bf8a4c25f244
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692283999 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_error
s.3692283999
Directory /workspace/8.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.1727428873
Short name T282
Test name
Test status
Simulation time 42798185440 ps
CPU time 31.83 seconds
Started Jul 21 06:33:09 PM PDT 24
Finished Jul 21 06:33:43 PM PDT 24
Peak memory 202112 kb
Host smart-df4bab30-6ec4-435b-b8fd-e7adc1904fbd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727428873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_tl_intg_err.1727428873
Directory /workspace/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1462739047
Short name T815
Test name
Test status
Simulation time 2188487874 ps
CPU time 3.1 seconds
Started Jul 21 06:33:08 PM PDT 24
Finished Jul 21 06:33:13 PM PDT 24
Peak memory 201992 kb
Host smart-0ce712eb-7bb3-4491-9af5-2de4c8250ba1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462739047 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_t
op.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1462739047
Directory /workspace/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3861183035
Short name T886
Test name
Test status
Simulation time 2046464570 ps
CPU time 2.12 seconds
Started Jul 21 06:33:07 PM PDT 24
Finished Jul 21 06:33:11 PM PDT 24
Peak memory 201908 kb
Host smart-8f15d66a-30c3-4f7d-91b3-f1207c206e57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861183035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_r
w.3861183035
Directory /workspace/9.sysrst_ctrl_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.137430049
Short name T887
Test name
Test status
Simulation time 2039655027 ps
CPU time 1.84 seconds
Started Jul 21 06:33:06 PM PDT 24
Finished Jul 21 06:33:09 PM PDT 24
Peak memory 201664 kb
Host smart-813de2de-daed-412e-83d4-2365a6c6a863
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137430049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test
.137430049
Directory /workspace/9.sysrst_ctrl_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.759283460
Short name T879
Test name
Test status
Simulation time 9026269566 ps
CPU time 2.78 seconds
Started Jul 21 06:33:06 PM PDT 24
Finished Jul 21 06:33:11 PM PDT 24
Peak memory 202248 kb
Host smart-019eea75-e39a-4591-9d82-34d1639c7c32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759283460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ
=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
sysrst_ctrl_same_csr_outstanding.759283460
Directory /workspace/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.2265581257
Short name T825
Test name
Test status
Simulation time 2526500453 ps
CPU time 2.47 seconds
Started Jul 21 06:33:07 PM PDT 24
Finished Jul 21 06:33:12 PM PDT 24
Peak memory 202164 kb
Host smart-a77c7ce0-e96b-4914-b4fe-f739c9e2c013
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265581257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_error
s.2265581257
Directory /workspace/9.sysrst_ctrl_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.2260766079
Short name T866
Test name
Test status
Simulation time 22417803055 ps
CPU time 15.83 seconds
Started Jul 21 06:33:14 PM PDT 24
Finished Jul 21 06:33:31 PM PDT 24
Peak memory 201900 kb
Host smart-bb06be06-4101-472d-ac68-18b07df9e263
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260766079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_
ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_c
trl_tl_intg_err.2260766079
Directory /workspace/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_alert_test.1540376256
Short name T522
Test name
Test status
Simulation time 2058553246 ps
CPU time 1.09 seconds
Started Jul 21 06:37:36 PM PDT 24
Finished Jul 21 06:37:38 PM PDT 24
Peak memory 201552 kb
Host smart-3f0bc11b-ec2e-4980-94e1-bf2d2bd987de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540376256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_tes
t.1540376256
Directory /workspace/0.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect.288566001
Short name T748
Test name
Test status
Simulation time 87655587511 ps
CPU time 57.46 seconds
Started Jul 21 06:37:35 PM PDT 24
Finished Jul 21 06:38:33 PM PDT 24
Peak memory 201828 kb
Host smart-53783c91-f1be-438d-a493-c99848e6a9eb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288566001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_combo_detect.288566001
Directory /workspace/0.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.798104639
Short name T530
Test name
Test status
Simulation time 2415062087 ps
CPU time 2.3 seconds
Started Jul 21 06:37:31 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 201516 kb
Host smart-88dc11ab-08bb-4965-bbff-4b0b2b5a273c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798104639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.798104639
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.400812256
Short name T215
Test name
Test status
Simulation time 2336692724 ps
CPU time 2.18 seconds
Started Jul 21 06:37:31 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 201560 kb
Host smart-bbd0d2c8-ca4a-4fbf-9494-4aa94d716413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400812256 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_
cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_det
ect_ec_rst_with_pre_cond.400812256
Directory /workspace/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.3504170055
Short name T256
Test name
Test status
Simulation time 27096823950 ps
CPU time 16.38 seconds
Started Jul 21 06:37:42 PM PDT 24
Finished Jul 21 06:37:59 PM PDT 24
Peak memory 201856 kb
Host smart-b68e8cd8-9594-4b6e-b3d3-d7c312733dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504170055 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_wi
th_pre_cond.3504170055
Directory /workspace/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.263454802
Short name T457
Test name
Test status
Simulation time 4287697510 ps
CPU time 3.26 seconds
Started Jul 21 06:37:30 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 201516 kb
Host smart-5ad7f4a4-7fec-4c0c-be31-5b7c1fafd198
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263454802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ct
rl_ec_pwr_on_rst.263454802
Directory /workspace/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_edge_detect.1603079851
Short name T217
Test name
Test status
Simulation time 3216620197 ps
CPU time 8.45 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:38:02 PM PDT 24
Peak memory 201528 kb
Host smart-929a66d6-222c-444a-8d6c-3c51dad3312a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603079851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctr
l_edge_detect.1603079851
Directory /workspace/0.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1002669166
Short name T507
Test name
Test status
Simulation time 2617470847 ps
CPU time 4.1 seconds
Started Jul 21 06:37:31 PM PDT 24
Finished Jul 21 06:37:37 PM PDT 24
Peak memory 201508 kb
Host smart-f0faf19a-83b1-4723-a151-8d9dde7abe44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002669166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.1002669166
Directory /workspace/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_in_out_inverted.1179683732
Short name T550
Test name
Test status
Simulation time 2464809931 ps
CPU time 3.87 seconds
Started Jul 21 06:37:28 PM PDT 24
Finished Jul 21 06:37:33 PM PDT 24
Peak memory 201540 kb
Host smart-3f66136f-2213-4faa-becf-bef1ea0f03b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179683732 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.1179683732
Directory /workspace/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_access_test.1696824813
Short name T532
Test name
Test status
Simulation time 2159692933 ps
CPU time 6.21 seconds
Started Jul 21 06:37:27 PM PDT 24
Finished Jul 21 06:37:35 PM PDT 24
Peak memory 201576 kb
Host smart-ab9019c7-73ad-4b98-8e96-779d6e3d71f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696824813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1696824813
Directory /workspace/0.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_pin_override_test.3159926411
Short name T488
Test name
Test status
Simulation time 2540928284 ps
CPU time 1.74 seconds
Started Jul 21 06:37:29 PM PDT 24
Finished Jul 21 06:37:31 PM PDT 24
Peak memory 201592 kb
Host smart-54bec831-eed3-42f3-96d2-fb232c3ea6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159926411 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.3159926411
Directory /workspace/0.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_sec_cm.3142268875
Short name T286
Test name
Test status
Simulation time 22018450095 ps
CPU time 28.19 seconds
Started Jul 21 06:37:44 PM PDT 24
Finished Jul 21 06:38:13 PM PDT 24
Peak memory 220960 kb
Host smart-39ce1619-d84d-4ed4-ba89-5fa97955ce4d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142268875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3142268875
Directory /workspace/0.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_smoke.2901430441
Short name T536
Test name
Test status
Simulation time 2124751292 ps
CPU time 1.89 seconds
Started Jul 21 06:37:30 PM PDT 24
Finished Jul 21 06:37:34 PM PDT 24
Peak memory 201444 kb
Host smart-db995826-7d32-41d8-926a-1a1bc033bd41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901430441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2901430441
Directory /workspace/0.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_stress_all.1779302927
Short name T201
Test name
Test status
Simulation time 14375605104 ps
CPU time 37.58 seconds
Started Jul 21 06:37:41 PM PDT 24
Finished Jul 21 06:38:19 PM PDT 24
Peak memory 201544 kb
Host smart-9b395fed-c1b0-4e3f-8498-cdfc2ff664c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779302927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_st
ress_all.1779302927
Directory /workspace/0.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/0.sysrst_ctrl_ultra_low_pwr.1637928641
Short name T510
Test name
Test status
Simulation time 3823412039 ps
CPU time 2.22 seconds
Started Jul 21 06:37:36 PM PDT 24
Finished Jul 21 06:37:40 PM PDT 24
Peak memory 201564 kb
Host smart-49fa9b38-2232-4ac0-812f-355aafa315c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1637928641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_c
trl_ultra_low_pwr.1637928641
Directory /workspace/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_alert_test.491677195
Short name T542
Test name
Test status
Simulation time 2025195646 ps
CPU time 2.98 seconds
Started Jul 21 06:37:45 PM PDT 24
Finished Jul 21 06:37:49 PM PDT 24
Peak memory 201532 kb
Host smart-c3860cce-421f-4269-ac9e-2b6cefb340f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491677195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test
.491677195
Directory /workspace/1.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3518155539
Short name T721
Test name
Test status
Simulation time 3014689526 ps
CPU time 1.49 seconds
Started Jul 21 06:37:36 PM PDT 24
Finished Jul 21 06:37:39 PM PDT 24
Peak memory 201608 kb
Host smart-e223ea2c-8770-4825-9fd9-4fb1a2169703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518155539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.3518155539
Directory /workspace/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect.2134877631
Short name T636
Test name
Test status
Simulation time 102271890828 ps
CPU time 247.89 seconds
Started Jul 21 06:37:38 PM PDT 24
Finished Jul 21 06:41:47 PM PDT 24
Peak memory 201788 kb
Host smart-721ebcb1-7b1f-4a1c-b2c3-e28789c61e59
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134877631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ct
rl_combo_detect.2134877631
Directory /workspace/1.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.4067087211
Short name T515
Test name
Test status
Simulation time 2431919278 ps
CPU time 5.45 seconds
Started Jul 21 06:37:46 PM PDT 24
Finished Jul 21 06:37:52 PM PDT 24
Peak memory 201564 kb
Host smart-00e32211-0946-4b87-b61f-426b0130617a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067087211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.4067087211
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2145214630
Short name T506
Test name
Test status
Simulation time 2518774264 ps
CPU time 2.13 seconds
Started Jul 21 06:37:35 PM PDT 24
Finished Jul 21 06:37:38 PM PDT 24
Peak memory 201448 kb
Host smart-b9c20d5c-a2a8-4f80-b5b3-04a35cb5590a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145214630 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.2145214630
Directory /workspace/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.3329945370
Short name T517
Test name
Test status
Simulation time 4156223549 ps
CPU time 3.42 seconds
Started Jul 21 06:37:44 PM PDT 24
Finished Jul 21 06:37:48 PM PDT 24
Peak memory 201536 kb
Host smart-cf24a774-937b-4d0e-9adc-e3d6d2845a77
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329945370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ec_pwr_on_rst.3329945370
Directory /workspace/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2058351022
Short name T524
Test name
Test status
Simulation time 2607468197 ps
CPU time 7.44 seconds
Started Jul 21 06:37:43 PM PDT 24
Finished Jul 21 06:37:51 PM PDT 24
Peak memory 201580 kb
Host smart-96be150c-0c1d-4a1d-bb38-dc133d2e576f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2058351022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.2058351022
Directory /workspace/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_in_out_inverted.2584328443
Short name T484
Test name
Test status
Simulation time 2478176110 ps
CPU time 3.53 seconds
Started Jul 21 06:37:35 PM PDT 24
Finished Jul 21 06:37:40 PM PDT 24
Peak memory 201464 kb
Host smart-afe523a4-3495-4964-9436-de17befd1d89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584328443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.2584328443
Directory /workspace/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_access_test.318234493
Short name T520
Test name
Test status
Simulation time 2199914173 ps
CPU time 6.63 seconds
Started Jul 21 06:37:38 PM PDT 24
Finished Jul 21 06:37:45 PM PDT 24
Peak memory 201496 kb
Host smart-96f94802-8740-475d-9522-3215bca58b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318234493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.318234493
Directory /workspace/1.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_pin_override_test.1700252982
Short name T761
Test name
Test status
Simulation time 2514077320 ps
CPU time 7.01 seconds
Started Jul 21 06:37:34 PM PDT 24
Finished Jul 21 06:37:42 PM PDT 24
Peak memory 201536 kb
Host smart-052ddaf0-b52c-46ac-9253-19236fc2a38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700252982 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.1700252982
Directory /workspace/1.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_sec_cm.1099570873
Short name T264
Test name
Test status
Simulation time 22083692921 ps
CPU time 14.7 seconds
Started Jul 21 06:37:35 PM PDT 24
Finished Jul 21 06:37:50 PM PDT 24
Peak memory 220884 kb
Host smart-4533bde4-a09c-4bfd-8530-ffe8a3c99c0f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099570873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.1099570873
Directory /workspace/1.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_smoke.2022496518
Short name T452
Test name
Test status
Simulation time 2150047512 ps
CPU time 1.43 seconds
Started Jul 21 06:37:37 PM PDT 24
Finished Jul 21 06:37:39 PM PDT 24
Peak memory 201540 kb
Host smart-d62f480a-d288-444e-9970-012e3c6ddf2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022496518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.2022496518
Directory /workspace/1.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_stress_all.1589575118
Short name T780
Test name
Test status
Simulation time 6562540970 ps
CPU time 9.22 seconds
Started Jul 21 06:37:43 PM PDT 24
Finished Jul 21 06:37:52 PM PDT 24
Peak memory 201540 kb
Host smart-28d19b33-3a7f-4b1b-920f-a7eb597fb4d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589575118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_st
ress_all.1589575118
Directory /workspace/1.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2519063392
Short name T534
Test name
Test status
Simulation time 6163021139 ps
CPU time 2.47 seconds
Started Jul 21 06:37:46 PM PDT 24
Finished Jul 21 06:37:49 PM PDT 24
Peak memory 201544 kb
Host smart-a7ea92fc-d0a3-4172-a654-7893153a9e2b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519063392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_c
trl_ultra_low_pwr.2519063392
Directory /workspace/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_alert_test.1736062425
Short name T486
Test name
Test status
Simulation time 2016164111 ps
CPU time 3.2 seconds
Started Jul 21 06:38:03 PM PDT 24
Finished Jul 21 06:38:07 PM PDT 24
Peak memory 201548 kb
Host smart-383faab0-5851-4894-846a-2cb0be161f66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736062425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_te
st.1736062425
Directory /workspace/10.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2671142432
Short name T46
Test name
Test status
Simulation time 3415377102 ps
CPU time 6.41 seconds
Started Jul 21 06:38:03 PM PDT 24
Finished Jul 21 06:38:10 PM PDT 24
Peak memory 201800 kb
Host smart-53b98bfe-020a-4374-a416-96b357f15098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671142432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.2
671142432
Directory /workspace/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect.2094104159
Short name T244
Test name
Test status
Simulation time 52365972208 ps
CPU time 37 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:38:39 PM PDT 24
Peak memory 201816 kb
Host smart-852e7945-87b6-49f9-a495-5e3e5a05d472
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094104159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_c
trl_combo_detect.2094104159
Directory /workspace/10.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3796457169
Short name T350
Test name
Test status
Simulation time 55629780386 ps
CPU time 153.92 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:40:36 PM PDT 24
Peak memory 201880 kb
Host smart-92949471-76be-4096-bdf4-c9433fb6119b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796457169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_w
ith_pre_cond.3796457169
Directory /workspace/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.4087275263
Short name T14
Test name
Test status
Simulation time 3575785968 ps
CPU time 2.9 seconds
Started Jul 21 06:38:03 PM PDT 24
Finished Jul 21 06:38:07 PM PDT 24
Peak memory 201540 kb
Host smart-631ac1e5-3fe1-4245-ade3-d5b7aaa40ebb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087275263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ec_pwr_on_rst.4087275263
Directory /workspace/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_edge_detect.1823779352
Short name T436
Test name
Test status
Simulation time 3021506449 ps
CPU time 1.07 seconds
Started Jul 21 06:38:03 PM PDT 24
Finished Jul 21 06:38:05 PM PDT 24
Peak memory 201452 kb
Host smart-be72962a-4f6a-40dc-9537-494c250883d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823779352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ct
rl_edge_detect.1823779352
Directory /workspace/10.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1339786530
Short name T724
Test name
Test status
Simulation time 2610525080 ps
CPU time 7.39 seconds
Started Jul 21 06:38:04 PM PDT 24
Finished Jul 21 06:38:12 PM PDT 24
Peak memory 201548 kb
Host smart-4f5ddd3b-1064-4b9a-a4cd-f42ecfff36c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339786530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.1339786530
Directory /workspace/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1182942615
Short name T435
Test name
Test status
Simulation time 2528665076 ps
CPU time 1.3 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:38:03 PM PDT 24
Peak memory 201572 kb
Host smart-95275f64-31f7-44e2-bf76-3b50d19fe3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182942615 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.1182942615
Directory /workspace/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_access_test.3330138211
Short name T216
Test name
Test status
Simulation time 2205864252 ps
CPU time 2.04 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:38:04 PM PDT 24
Peak memory 201572 kb
Host smart-9fe1d620-4cad-45ab-8939-fab54cac9c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330138211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.3330138211
Directory /workspace/10.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_pin_override_test.3719222760
Short name T595
Test name
Test status
Simulation time 2518124922 ps
CPU time 3.92 seconds
Started Jul 21 06:38:00 PM PDT 24
Finished Jul 21 06:38:04 PM PDT 24
Peak memory 201532 kb
Host smart-fadbf3c4-cda9-4df6-9e49-658fac87ddd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719222760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3719222760
Directory /workspace/10.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_smoke.156030053
Short name T155
Test name
Test status
Simulation time 2109773038 ps
CPU time 5.69 seconds
Started Jul 21 06:37:56 PM PDT 24
Finished Jul 21 06:38:03 PM PDT 24
Peak memory 201464 kb
Host smart-80515d82-bcf6-49c1-a869-2fb68275c9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156030053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.156030053
Directory /workspace/10.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all.1496092578
Short name T440
Test name
Test status
Simulation time 6455010163 ps
CPU time 4.67 seconds
Started Jul 21 06:38:00 PM PDT 24
Finished Jul 21 06:38:06 PM PDT 24
Peak memory 201544 kb
Host smart-a55eae86-525e-49a2-a32d-aca589b3bcfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496092578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_s
tress_all.1496092578
Directory /workspace/10.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2694365308
Short name T194
Test name
Test status
Simulation time 13733363759 ps
CPU time 35.02 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:38:37 PM PDT 24
Peak memory 209856 kb
Host smart-42af6b8b-21b0-4ea8-97ce-117f92bdc2eb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694365308 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.2694365308
Directory /workspace/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3014491032
Short name T112
Test name
Test status
Simulation time 8573740124 ps
CPU time 2.18 seconds
Started Jul 21 06:38:03 PM PDT 24
Finished Jul 21 06:38:06 PM PDT 24
Peak memory 201564 kb
Host smart-00f8d443-d12f-4722-b5f7-5f985ffb56b3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014491032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_
ctrl_ultra_low_pwr.3014491032
Directory /workspace/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2193342019
Short name T794
Test name
Test status
Simulation time 3386803607 ps
CPU time 9.05 seconds
Started Jul 21 06:37:59 PM PDT 24
Finished Jul 21 06:38:08 PM PDT 24
Peak memory 201596 kb
Host smart-eb15da11-0d01-404e-a9cd-0f47a5770553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193342019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2
193342019
Directory /workspace/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_combo_detect.458802120
Short name T98
Test name
Test status
Simulation time 92272526496 ps
CPU time 113.5 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:39:56 PM PDT 24
Peak memory 201780 kb
Host smart-1a6de207-e888-4105-bce1-1d51da3d661e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458802120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_combo_detect.458802120
Directory /workspace/11.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.365631571
Short name T588
Test name
Test status
Simulation time 3220778846 ps
CPU time 4.68 seconds
Started Jul 21 06:38:02 PM PDT 24
Finished Jul 21 06:38:08 PM PDT 24
Peak memory 201536 kb
Host smart-e80319c1-4683-43d5-9c75-8346c4f12054
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365631571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_c
trl_ec_pwr_on_rst.365631571
Directory /workspace/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_edge_detect.3049709593
Short name T152
Test name
Test status
Simulation time 3682821329 ps
CPU time 2.95 seconds
Started Jul 21 06:38:00 PM PDT 24
Finished Jul 21 06:38:04 PM PDT 24
Peak memory 201564 kb
Host smart-04eddeeb-99ee-4167-8a11-ceca3181e998
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049709593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ct
rl_edge_detect.3049709593
Directory /workspace/11.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.189603210
Short name T467
Test name
Test status
Simulation time 2611883795 ps
CPU time 7.06 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:38:09 PM PDT 24
Peak memory 201524 kb
Host smart-1e889444-f4a0-4b4e-a779-442ad561a7a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189603210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.189603210
Directory /workspace/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_in_out_inverted.1393650791
Short name T654
Test name
Test status
Simulation time 2457310452 ps
CPU time 3.67 seconds
Started Jul 21 06:37:59 PM PDT 24
Finished Jul 21 06:38:03 PM PDT 24
Peak memory 201572 kb
Host smart-0fa21874-3dbe-4b43-a2ce-b3c2cc5b8212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393650791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.1393650791
Directory /workspace/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_access_test.686908652
Short name T159
Test name
Test status
Simulation time 2109633970 ps
CPU time 1.97 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:38:05 PM PDT 24
Peak memory 201488 kb
Host smart-37de7966-d408-42a7-93c8-0cc45bf6f045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686908652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.686908652
Directory /workspace/11.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_pin_override_test.2884326159
Short name T698
Test name
Test status
Simulation time 2521288017 ps
CPU time 4.3 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:38:07 PM PDT 24
Peak memory 201548 kb
Host smart-db9321cc-7920-4bf8-9ae3-7a79e5e04c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884326159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2884326159
Directory /workspace/11.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_smoke.583054997
Short name T527
Test name
Test status
Simulation time 2111742474 ps
CPU time 6.17 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:38:08 PM PDT 24
Peak memory 201360 kb
Host smart-8267eeba-84a0-488f-8b38-b0d66f927892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583054997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.583054997
Directory /workspace/11.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all.3664141153
Short name T69
Test name
Test status
Simulation time 8939044285 ps
CPU time 23.14 seconds
Started Jul 21 06:38:02 PM PDT 24
Finished Jul 21 06:38:26 PM PDT 24
Peak memory 201504 kb
Host smart-368676cb-1aec-4af4-a8be-a8f6252b8367
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664141153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_s
tress_all.3664141153
Directory /workspace/11.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.173158382
Short name T292
Test name
Test status
Simulation time 65579756375 ps
CPU time 41 seconds
Started Jul 21 06:38:00 PM PDT 24
Finished Jul 21 06:38:43 PM PDT 24
Peak memory 210172 kb
Host smart-a73fd970-9822-4143-bea5-188956893b20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173158382 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.173158382
Directory /workspace/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1988193892
Short name T120
Test name
Test status
Simulation time 8369470235 ps
CPU time 4.07 seconds
Started Jul 21 06:38:06 PM PDT 24
Finished Jul 21 06:38:10 PM PDT 24
Peak memory 201500 kb
Host smart-2c932e9c-18cc-4489-8e34-a78ced7bcb3c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988193892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_
ctrl_ultra_low_pwr.1988193892
Directory /workspace/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_alert_test.125023495
Short name T725
Test name
Test status
Simulation time 2061166550 ps
CPU time 1.28 seconds
Started Jul 21 06:38:05 PM PDT 24
Finished Jul 21 06:38:07 PM PDT 24
Peak memory 201488 kb
Host smart-28a37271-f039-4fb3-92e8-6ec27183d439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125023495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_tes
t.125023495
Directory /workspace/12.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.4187674714
Short name T13
Test name
Test status
Simulation time 3526107635 ps
CPU time 10.42 seconds
Started Jul 21 06:38:00 PM PDT 24
Finished Jul 21 06:38:12 PM PDT 24
Peak memory 201608 kb
Host smart-c8657de1-f17b-445b-873e-b4e803c569f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187674714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.4
187674714
Directory /workspace/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_combo_detect.2485447166
Short name T583
Test name
Test status
Simulation time 22335840127 ps
CPU time 58.74 seconds
Started Jul 21 06:38:03 PM PDT 24
Finished Jul 21 06:39:03 PM PDT 24
Peak memory 201752 kb
Host smart-cddb22ca-e474-4fae-bcc0-ef743a520b0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485447166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_c
trl_combo_detect.2485447166
Directory /workspace/12.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.3883517593
Short name T154
Test name
Test status
Simulation time 2848664136 ps
CPU time 1.4 seconds
Started Jul 21 06:38:02 PM PDT 24
Finished Jul 21 06:38:04 PM PDT 24
Peak memory 201492 kb
Host smart-8b4f3624-c9ce-4491-9596-7be618d3272a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883517593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ec_pwr_on_rst.3883517593
Directory /workspace/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_edge_detect.2688116948
Short name T107
Test name
Test status
Simulation time 2921710689 ps
CPU time 5.45 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:38:08 PM PDT 24
Peak memory 201512 kb
Host smart-9432cb7e-471e-48b8-b53e-dadd7171de0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688116948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ct
rl_edge_detect.2688116948
Directory /workspace/12.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3215856120
Short name T659
Test name
Test status
Simulation time 2623569668 ps
CPU time 4.15 seconds
Started Jul 21 06:38:02 PM PDT 24
Finished Jul 21 06:38:07 PM PDT 24
Peak memory 201560 kb
Host smart-b2d62d9d-546c-4b1a-85dd-dba07d49031a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215856120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.3215856120
Directory /workspace/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_in_out_inverted.3090412187
Short name T714
Test name
Test status
Simulation time 2467462378 ps
CPU time 4.04 seconds
Started Jul 21 06:38:00 PM PDT 24
Finished Jul 21 06:38:04 PM PDT 24
Peak memory 201592 kb
Host smart-5c876bcc-e59e-46b9-9666-2bee95f369db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090412187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.3090412187
Directory /workspace/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.2553875289
Short name T131
Test name
Test status
Simulation time 2225068370 ps
CPU time 1.69 seconds
Started Jul 21 06:38:02 PM PDT 24
Finished Jul 21 06:38:05 PM PDT 24
Peak memory 201576 kb
Host smart-daf5b033-cb9b-452b-840b-94a282ccd57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553875289 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.2553875289
Directory /workspace/12.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.219165888
Short name T311
Test name
Test status
Simulation time 2509133121 ps
CPU time 7.17 seconds
Started Jul 21 06:38:05 PM PDT 24
Finished Jul 21 06:38:13 PM PDT 24
Peak memory 201536 kb
Host smart-62808c06-b3ec-4396-a39d-efc60d110367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219165888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.219165888
Directory /workspace/12.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_smoke.2638656163
Short name T214
Test name
Test status
Simulation time 2219533016 ps
CPU time 1.01 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:38:03 PM PDT 24
Peak memory 201440 kb
Host smart-7d2d32c7-c178-4801-a995-1fe1e75b31f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638656163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.2638656163
Directory /workspace/12.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_stress_all.153030449
Short name T115
Test name
Test status
Simulation time 15399656747 ps
CPU time 10.48 seconds
Started Jul 21 06:38:03 PM PDT 24
Finished Jul 21 06:38:14 PM PDT 24
Peak memory 201780 kb
Host smart-aa9b7a68-988d-44d0-ad0e-d4e64428c9b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153030449 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_st
ress_all.153030449
Directory /workspace/12.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1851590981
Short name T643
Test name
Test status
Simulation time 3917996585 ps
CPU time 3.45 seconds
Started Jul 21 06:38:01 PM PDT 24
Finished Jul 21 06:38:06 PM PDT 24
Peak memory 201540 kb
Host smart-11fb0f13-51bc-49e0-824a-4fd1da12283d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851590981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_
ctrl_ultra_low_pwr.1851590981
Directory /workspace/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_alert_test.2950491526
Short name T413
Test name
Test status
Simulation time 2011399684 ps
CPU time 5.45 seconds
Started Jul 21 06:38:14 PM PDT 24
Finished Jul 21 06:38:20 PM PDT 24
Peak memory 201544 kb
Host smart-b080286e-af48-4150-b586-90c44bf0f36d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950491526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_te
st.2950491526
Directory /workspace/13.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2611798645
Short name T48
Test name
Test status
Simulation time 3817923778 ps
CPU time 1.38 seconds
Started Jul 21 06:38:14 PM PDT 24
Finished Jul 21 06:38:16 PM PDT 24
Peak memory 201676 kb
Host smart-9bb187e5-9ccf-4593-9e3f-e5692fe28fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611798645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.2
611798645
Directory /workspace/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.423463428
Short name T238
Test name
Test status
Simulation time 156481804412 ps
CPU time 370.86 seconds
Started Jul 21 06:38:16 PM PDT 24
Finished Jul 21 06:44:28 PM PDT 24
Peak memory 201820 kb
Host smart-a82a7874-3b37-43fd-88a4-c461f3cc1c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423463428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_wi
th_pre_cond.423463428
Directory /workspace/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1413599116
Short name T560
Test name
Test status
Simulation time 3795754313 ps
CPU time 5.37 seconds
Started Jul 21 06:38:10 PM PDT 24
Finished Jul 21 06:38:16 PM PDT 24
Peak memory 201520 kb
Host smart-cdbd4303-a8e9-426d-89d6-ffc779d9a527
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413599116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ec_pwr_on_rst.1413599116
Directory /workspace/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_edge_detect.3838392348
Short name T556
Test name
Test status
Simulation time 3228860801 ps
CPU time 2.73 seconds
Started Jul 21 06:38:08 PM PDT 24
Finished Jul 21 06:38:11 PM PDT 24
Peak memory 201556 kb
Host smart-eb572260-aae5-4656-ba78-3cb619b841cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838392348 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ct
rl_edge_detect.3838392348
Directory /workspace/13.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.1386077754
Short name T211
Test name
Test status
Simulation time 2615508851 ps
CPU time 6.76 seconds
Started Jul 21 06:38:09 PM PDT 24
Finished Jul 21 06:38:16 PM PDT 24
Peak memory 201568 kb
Host smart-495d2ea5-41b3-471c-ab32-32456708bed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386077754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.1386077754
Directory /workspace/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_in_out_inverted.3981971386
Short name T723
Test name
Test status
Simulation time 2479516966 ps
CPU time 8.05 seconds
Started Jul 21 06:38:17 PM PDT 24
Finished Jul 21 06:38:26 PM PDT 24
Peak memory 201352 kb
Host smart-dcc1a50a-8eb9-4626-9aa5-a837ccdbcfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981971386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.3981971386
Directory /workspace/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_access_test.1145916209
Short name T628
Test name
Test status
Simulation time 2290625239 ps
CPU time 1.7 seconds
Started Jul 21 06:38:13 PM PDT 24
Finished Jul 21 06:38:16 PM PDT 24
Peak memory 201396 kb
Host smart-103c236e-7892-44e1-855a-ae5166a6a9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145916209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.1145916209
Directory /workspace/13.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_pin_override_test.1959717509
Short name T585
Test name
Test status
Simulation time 2513694060 ps
CPU time 4.01 seconds
Started Jul 21 06:38:10 PM PDT 24
Finished Jul 21 06:38:15 PM PDT 24
Peak memory 201564 kb
Host smart-8c48077d-16ce-4d1e-822f-5967caf71bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959717509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.1959717509
Directory /workspace/13.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_smoke.736825920
Short name T788
Test name
Test status
Simulation time 2122509649 ps
CPU time 3.02 seconds
Started Jul 21 06:37:59 PM PDT 24
Finished Jul 21 06:38:02 PM PDT 24
Peak memory 201400 kb
Host smart-c42e7f04-f47e-4abc-911d-95a7ea3ae04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736825920 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.736825920
Directory /workspace/13.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_stress_all.3457860988
Short name T31
Test name
Test status
Simulation time 11338812693 ps
CPU time 12.72 seconds
Started Jul 21 06:38:06 PM PDT 24
Finished Jul 21 06:38:20 PM PDT 24
Peak memory 201556 kb
Host smart-b247d04e-c46d-4403-9c0e-8e67048fc203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457860988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_s
tress_all.3457860988
Directory /workspace/13.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.2754573900
Short name T301
Test name
Test status
Simulation time 4843930369 ps
CPU time 1.88 seconds
Started Jul 21 06:38:13 PM PDT 24
Finished Jul 21 06:38:16 PM PDT 24
Peak memory 201468 kb
Host smart-ad31d2bf-7624-476c-bc30-08c028e814cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754573900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_
ctrl_ultra_low_pwr.2754573900
Directory /workspace/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_alert_test.2156212534
Short name T750
Test name
Test status
Simulation time 2011166434 ps
CPU time 5.73 seconds
Started Jul 21 06:38:07 PM PDT 24
Finished Jul 21 06:38:13 PM PDT 24
Peak memory 201456 kb
Host smart-4c68913f-d003-4453-a86e-5c09bd80f3a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156212534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_te
st.2156212534
Directory /workspace/14.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_auto_blk_key_output.584693424
Short name T504
Test name
Test status
Simulation time 3307818296 ps
CPU time 4.6 seconds
Started Jul 21 06:38:08 PM PDT 24
Finished Jul 21 06:38:14 PM PDT 24
Peak memory 201620 kb
Host smart-aa68c75f-759c-4158-95b9-7344c0a37662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584693424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.584693424
Directory /workspace/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.4162696231
Short name T125
Test name
Test status
Simulation time 74645879336 ps
CPU time 155.37 seconds
Started Jul 21 06:38:07 PM PDT 24
Finished Jul 21 06:40:43 PM PDT 24
Peak memory 201876 kb
Host smart-18858be1-8667-4fd7-97b2-6fd45d67129f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162696231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_w
ith_pre_cond.4162696231
Directory /workspace/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.824297592
Short name T564
Test name
Test status
Simulation time 3837679076 ps
CPU time 3.17 seconds
Started Jul 21 06:38:06 PM PDT 24
Finished Jul 21 06:38:10 PM PDT 24
Peak memory 201576 kb
Host smart-160fe164-4d3a-4de3-93ad-fb4e39636114
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824297592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_c
trl_ec_pwr_on_rst.824297592
Directory /workspace/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_edge_detect.415621622
Short name T198
Test name
Test status
Simulation time 5594551420 ps
CPU time 6.99 seconds
Started Jul 21 06:38:14 PM PDT 24
Finished Jul 21 06:38:22 PM PDT 24
Peak memory 201564 kb
Host smart-068c3b9a-250a-4802-a98d-88d419038578
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415621622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctr
l_edge_detect.415621622
Directory /workspace/14.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2834372992
Short name T412
Test name
Test status
Simulation time 2611402733 ps
CPU time 7.92 seconds
Started Jul 21 06:38:13 PM PDT 24
Finished Jul 21 06:38:22 PM PDT 24
Peak memory 201568 kb
Host smart-a0c3bfac-a278-4805-8388-e2e00892ea9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834372992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.2834372992
Directory /workspace/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_in_out_inverted.2904707545
Short name T65
Test name
Test status
Simulation time 2450531042 ps
CPU time 3.99 seconds
Started Jul 21 06:38:06 PM PDT 24
Finished Jul 21 06:38:11 PM PDT 24
Peak memory 201536 kb
Host smart-b50f96c6-274c-44d9-bab3-a8e469d74925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904707545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.2904707545
Directory /workspace/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_access_test.218437739
Short name T561
Test name
Test status
Simulation time 2167852233 ps
CPU time 0.85 seconds
Started Jul 21 06:38:23 PM PDT 24
Finished Jul 21 06:38:24 PM PDT 24
Peak memory 201532 kb
Host smart-6b10ca5d-6854-4479-853a-6cbc4f794482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218437739 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.218437739
Directory /workspace/14.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.1994072561
Short name T443
Test name
Test status
Simulation time 2518652717 ps
CPU time 3.16 seconds
Started Jul 21 06:38:17 PM PDT 24
Finished Jul 21 06:38:21 PM PDT 24
Peak memory 201340 kb
Host smart-5e7d9cf9-eede-46a0-8fa8-d9deba6b43e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994072561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.1994072561
Directory /workspace/14.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_smoke.1107826032
Short name T533
Test name
Test status
Simulation time 2135480496 ps
CPU time 2.07 seconds
Started Jul 21 06:38:08 PM PDT 24
Finished Jul 21 06:38:11 PM PDT 24
Peak memory 201456 kb
Host smart-841aaa69-7ac5-4378-8b3f-c45c8f8a58cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107826032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.1107826032
Directory /workspace/14.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/14.sysrst_ctrl_stress_all.2843708114
Short name T344
Test name
Test status
Simulation time 226640644558 ps
CPU time 547.43 seconds
Started Jul 21 06:38:07 PM PDT 24
Finished Jul 21 06:47:15 PM PDT 24
Peak memory 201856 kb
Host smart-e9b07791-f1ba-412d-bfe4-634aafbb29eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843708114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_s
tress_all.2843708114
Directory /workspace/14.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_alert_test.2000682467
Short name T158
Test name
Test status
Simulation time 2037866858 ps
CPU time 1.69 seconds
Started Jul 21 06:38:12 PM PDT 24
Finished Jul 21 06:38:14 PM PDT 24
Peak memory 201528 kb
Host smart-fe4aeb3f-309d-4fb7-8dfc-0b7b59d20d61
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000682467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_te
st.2000682467
Directory /workspace/15.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_auto_blk_key_output.736039315
Short name T775
Test name
Test status
Simulation time 3791449235 ps
CPU time 9.75 seconds
Started Jul 21 06:38:14 PM PDT 24
Finished Jul 21 06:38:24 PM PDT 24
Peak memory 201608 kb
Host smart-e96ba911-8aa3-4732-b824-768360e0e2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736039315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.736039315
Directory /workspace/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect.3416899899
Short name T342
Test name
Test status
Simulation time 46186425410 ps
CPU time 59.09 seconds
Started Jul 21 06:38:17 PM PDT 24
Finished Jul 21 06:39:17 PM PDT 24
Peak memory 201740 kb
Host smart-0c95b124-daf0-4889-aaef-17e6f31f6e0e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416899899 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_c
trl_combo_detect.3416899899
Directory /workspace/15.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.1246211280
Short name T357
Test name
Test status
Simulation time 74110445378 ps
CPU time 161.84 seconds
Started Jul 21 06:38:16 PM PDT 24
Finished Jul 21 06:40:59 PM PDT 24
Peak memory 201844 kb
Host smart-1003bec2-5328-4400-9cce-1de53dcf0383
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246211280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_w
ith_pre_cond.1246211280
Directory /workspace/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3103074061
Short name T691
Test name
Test status
Simulation time 2852561115 ps
CPU time 1.75 seconds
Started Jul 21 06:38:08 PM PDT 24
Finished Jul 21 06:38:10 PM PDT 24
Peak memory 201504 kb
Host smart-c9b07e4d-1c63-4992-b0b2-e01f36c51c3b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103074061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ec_pwr_on_rst.3103074061
Directory /workspace/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_edge_detect.4211306267
Short name T180
Test name
Test status
Simulation time 3089015932 ps
CPU time 6.35 seconds
Started Jul 21 06:38:12 PM PDT 24
Finished Jul 21 06:38:18 PM PDT 24
Peak memory 201540 kb
Host smart-cce24a68-4e79-48ae-98de-30a38ca36e28
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211306267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ct
rl_edge_detect.4211306267
Directory /workspace/15.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2824890002
Short name T495
Test name
Test status
Simulation time 2643717814 ps
CPU time 2.05 seconds
Started Jul 21 06:38:09 PM PDT 24
Finished Jul 21 06:38:12 PM PDT 24
Peak memory 201548 kb
Host smart-f4f7ff86-2ca3-45af-ba8d-e3f6ad5b7d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824890002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.2824890002
Directory /workspace/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2882219489
Short name T442
Test name
Test status
Simulation time 2474587334 ps
CPU time 4.21 seconds
Started Jul 21 06:38:12 PM PDT 24
Finished Jul 21 06:38:17 PM PDT 24
Peak memory 201548 kb
Host smart-e46701e1-2d85-461b-9467-1e24e6f7a7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882219489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.2882219489
Directory /workspace/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_access_test.4015833602
Short name T639
Test name
Test status
Simulation time 2226159538 ps
CPU time 1.98 seconds
Started Jul 21 06:38:08 PM PDT 24
Finished Jul 21 06:38:11 PM PDT 24
Peak memory 201524 kb
Host smart-881ad0c0-fa21-424c-9555-81cb391de105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015833602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.4015833602
Directory /workspace/15.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_pin_override_test.2872458870
Short name T548
Test name
Test status
Simulation time 2537805704 ps
CPU time 2.23 seconds
Started Jul 21 06:38:14 PM PDT 24
Finished Jul 21 06:38:18 PM PDT 24
Peak memory 201580 kb
Host smart-407a9f40-e197-460c-897f-da08d3e0c982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872458870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2872458870
Directory /workspace/15.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_smoke.3751977439
Short name T385
Test name
Test status
Simulation time 2137260891 ps
CPU time 2.15 seconds
Started Jul 21 06:38:15 PM PDT 24
Finished Jul 21 06:38:18 PM PDT 24
Peak memory 201492 kb
Host smart-6afab15b-97a0-4ccc-a006-16b0d5135544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751977439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3751977439
Directory /workspace/15.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_stress_all.2347269062
Short name T213
Test name
Test status
Simulation time 78454688847 ps
CPU time 47.99 seconds
Started Jul 21 06:38:22 PM PDT 24
Finished Jul 21 06:39:10 PM PDT 24
Peak memory 201772 kb
Host smart-12db3dee-4595-4164-9e94-e01e40f61f4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347269062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_s
tress_all.2347269062
Directory /workspace/15.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2435918843
Short name T300
Test name
Test status
Simulation time 3064886930 ps
CPU time 1.01 seconds
Started Jul 21 06:38:08 PM PDT 24
Finished Jul 21 06:38:10 PM PDT 24
Peak memory 201580 kb
Host smart-00c1ad08-3cdf-4932-8719-9d8dcc91bbb4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435918843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_
ctrl_ultra_low_pwr.2435918843
Directory /workspace/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_alert_test.2539613658
Short name T493
Test name
Test status
Simulation time 2022888693 ps
CPU time 3.11 seconds
Started Jul 21 06:38:07 PM PDT 24
Finished Jul 21 06:38:11 PM PDT 24
Peak memory 201428 kb
Host smart-4c421fb8-6b12-44a0-994c-d62331a8866e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539613658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_te
st.2539613658
Directory /workspace/16.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1458266692
Short name T109
Test name
Test status
Simulation time 3598471590 ps
CPU time 10.33 seconds
Started Jul 21 06:38:09 PM PDT 24
Finished Jul 21 06:38:20 PM PDT 24
Peak memory 201616 kb
Host smart-c8555240-38c5-4abe-b376-d2719abdb043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458266692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.1
458266692
Directory /workspace/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.4137163608
Short name T781
Test name
Test status
Simulation time 26335358054 ps
CPU time 35 seconds
Started Jul 21 06:38:09 PM PDT 24
Finished Jul 21 06:38:45 PM PDT 24
Peak memory 201876 kb
Host smart-bc1b619a-d068-41c7-85dd-ff8ac34cb9d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4137163608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_w
ith_pre_cond.4137163608
Directory /workspace/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.633411028
Short name T438
Test name
Test status
Simulation time 3233257199 ps
CPU time 4.98 seconds
Started Jul 21 06:38:16 PM PDT 24
Finished Jul 21 06:38:22 PM PDT 24
Peak memory 201544 kb
Host smart-98a00674-a2d1-47f1-8e64-4438a9f22f82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633411028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_c
trl_ec_pwr_on_rst.633411028
Directory /workspace/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_edge_detect.1524893443
Short name T142
Test name
Test status
Simulation time 4110177023 ps
CPU time 3.24 seconds
Started Jul 21 06:38:08 PM PDT 24
Finished Jul 21 06:38:11 PM PDT 24
Peak memory 201560 kb
Host smart-6422c844-c94e-4344-861c-4606185a3008
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524893443 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ct
rl_edge_detect.1524893443
Directory /workspace/16.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2253762530
Short name T104
Test name
Test status
Simulation time 2633720988 ps
CPU time 2.33 seconds
Started Jul 21 06:38:15 PM PDT 24
Finished Jul 21 06:38:19 PM PDT 24
Peak memory 201548 kb
Host smart-74a18c00-94fb-429a-937a-df615dd95600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253762530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.2253762530
Directory /workspace/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_in_out_inverted.2680912259
Short name T700
Test name
Test status
Simulation time 2458574437 ps
CPU time 7.72 seconds
Started Jul 21 06:38:09 PM PDT 24
Finished Jul 21 06:38:18 PM PDT 24
Peak memory 201556 kb
Host smart-ba54623a-8932-4a5a-b686-31d2a3279111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680912259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.2680912259
Directory /workspace/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.1418422675
Short name T437
Test name
Test status
Simulation time 2269757920 ps
CPU time 1.97 seconds
Started Jul 21 06:38:12 PM PDT 24
Finished Jul 21 06:38:15 PM PDT 24
Peak memory 201548 kb
Host smart-5985cd4e-1a83-4a35-b62e-9fb3f8607501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418422675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.1418422675
Directory /workspace/16.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2512584772
Short name T414
Test name
Test status
Simulation time 2514709658 ps
CPU time 6.75 seconds
Started Jul 21 06:38:09 PM PDT 24
Finished Jul 21 06:38:17 PM PDT 24
Peak memory 201508 kb
Host smart-7f62d752-0370-443d-8166-ab72ed2271e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512584772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.2512584772
Directory /workspace/16.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_smoke.2431285189
Short name T625
Test name
Test status
Simulation time 2160684604 ps
CPU time 1.34 seconds
Started Jul 21 06:38:07 PM PDT 24
Finished Jul 21 06:38:09 PM PDT 24
Peak memory 201580 kb
Host smart-0e52913a-35fc-4d2f-b31c-14ab061597ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431285189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.2431285189
Directory /workspace/16.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all.4040249773
Short name T74
Test name
Test status
Simulation time 13175856611 ps
CPU time 15.39 seconds
Started Jul 21 06:38:08 PM PDT 24
Finished Jul 21 06:38:24 PM PDT 24
Peak memory 201652 kb
Host smart-22a41aa0-ce01-44c9-82a2-3825cd9e6615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040249773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_s
tress_all.4040249773
Directory /workspace/16.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.716381538
Short name T207
Test name
Test status
Simulation time 143457369384 ps
CPU time 193.49 seconds
Started Jul 21 06:38:12 PM PDT 24
Finished Jul 21 06:41:26 PM PDT 24
Peak memory 210144 kb
Host smart-f7e21a52-5f27-4ffa-b2c4-81dbb1e2d8cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716381538 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.716381538
Directory /workspace/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.sysrst_ctrl_ultra_low_pwr.2738623460
Short name T378
Test name
Test status
Simulation time 1373140402991 ps
CPU time 317.08 seconds
Started Jul 21 06:38:08 PM PDT 24
Finished Jul 21 06:43:25 PM PDT 24
Peak memory 201572 kb
Host smart-21e0b6c8-668c-4b4f-bcbe-bb9cf6ec0dd1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738623460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_
ctrl_ultra_low_pwr.2738623460
Directory /workspace/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_alert_test.1727732777
Short name T105
Test name
Test status
Simulation time 2020384585 ps
CPU time 3.2 seconds
Started Jul 21 06:38:14 PM PDT 24
Finished Jul 21 06:38:18 PM PDT 24
Peak memory 201560 kb
Host smart-312e332e-b1db-49d1-a237-cbcc359acdb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727732777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_te
st.1727732777
Directory /workspace/17.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_auto_blk_key_output.396611268
Short name T501
Test name
Test status
Simulation time 3284232244 ps
CPU time 8.53 seconds
Started Jul 21 06:38:12 PM PDT 24
Finished Jul 21 06:38:21 PM PDT 24
Peak memory 201644 kb
Host smart-1f562670-ba76-475c-b311-497546796c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396611268 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.396611268
Directory /workspace/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect.2671930950
Short name T101
Test name
Test status
Simulation time 18849245202 ps
CPU time 52.21 seconds
Started Jul 21 06:38:14 PM PDT 24
Finished Jul 21 06:39:08 PM PDT 24
Peak memory 201728 kb
Host smart-749f812e-c51d-42e0-8c12-6d583b7b447c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671930950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_combo_detect.2671930950
Directory /workspace/17.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.842281702
Short name T568
Test name
Test status
Simulation time 122912779656 ps
CPU time 171.36 seconds
Started Jul 21 06:38:27 PM PDT 24
Finished Jul 21 06:41:19 PM PDT 24
Peak memory 201876 kb
Host smart-fec91691-39eb-4e4d-bd98-239e3300fa1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842281702 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_wi
th_pre_cond.842281702
Directory /workspace/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.1898125737
Short name T772
Test name
Test status
Simulation time 4630133464 ps
CPU time 13.25 seconds
Started Jul 21 06:38:11 PM PDT 24
Finished Jul 21 06:38:25 PM PDT 24
Peak memory 201508 kb
Host smart-ec4358bc-8a99-43e5-aa70-21e2d556e2a7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898125737 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_
ctrl_ec_pwr_on_rst.1898125737
Directory /workspace/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.4186148897
Short name T165
Test name
Test status
Simulation time 2607990060 ps
CPU time 7.53 seconds
Started Jul 21 06:38:13 PM PDT 24
Finished Jul 21 06:38:21 PM PDT 24
Peak memory 201580 kb
Host smart-645a03c4-8f14-4252-9e5a-5406fb0c04bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186148897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.4186148897
Directory /workspace/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_in_out_inverted.1886433614
Short name T577
Test name
Test status
Simulation time 2452541545 ps
CPU time 8.43 seconds
Started Jul 21 06:38:28 PM PDT 24
Finished Jul 21 06:38:37 PM PDT 24
Peak memory 201412 kb
Host smart-18dbf078-3c3f-4a21-94c7-003deb09f1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886433614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.1886433614
Directory /workspace/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3335282212
Short name T425
Test name
Test status
Simulation time 2256901053 ps
CPU time 2.1 seconds
Started Jul 21 06:38:31 PM PDT 24
Finished Jul 21 06:38:34 PM PDT 24
Peak memory 201392 kb
Host smart-520b8963-c47d-4e7b-a2ad-ce6fe19899fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335282212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.3335282212
Directory /workspace/17.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_pin_override_test.1377146710
Short name T299
Test name
Test status
Simulation time 2517979568 ps
CPU time 3.83 seconds
Started Jul 21 06:38:31 PM PDT 24
Finished Jul 21 06:38:36 PM PDT 24
Peak memory 201392 kb
Host smart-f36f33bf-8a2a-4945-9f6c-3d12102806f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377146710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.1377146710
Directory /workspace/17.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_smoke.3153889681
Short name T616
Test name
Test status
Simulation time 2135403111 ps
CPU time 1.91 seconds
Started Jul 21 06:38:13 PM PDT 24
Finished Jul 21 06:38:16 PM PDT 24
Peak memory 201500 kb
Host smart-1aa9e26a-a769-4c6d-a786-66d22239325d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153889681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.3153889681
Directory /workspace/17.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_stress_all.669250887
Short name T102
Test name
Test status
Simulation time 147428927807 ps
CPU time 125.17 seconds
Started Jul 21 06:38:18 PM PDT 24
Finished Jul 21 06:40:24 PM PDT 24
Peak memory 201816 kb
Host smart-d6fa1537-057a-4298-bc8b-629faeabf432
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669250887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_st
ress_all.669250887
Directory /workspace/17.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/17.sysrst_ctrl_ultra_low_pwr.868415873
Short name T594
Test name
Test status
Simulation time 4085362101 ps
CPU time 1.86 seconds
Started Jul 21 06:38:14 PM PDT 24
Finished Jul 21 06:38:17 PM PDT 24
Peak memory 201616 kb
Host smart-fc534bf6-2f23-4b48-bda7-a75749caf6bb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868415873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_c
trl_ultra_low_pwr.868415873
Directory /workspace/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_alert_test.4171054698
Short name T513
Test name
Test status
Simulation time 2014260596 ps
CPU time 6.08 seconds
Started Jul 21 06:38:16 PM PDT 24
Finished Jul 21 06:38:23 PM PDT 24
Peak memory 201508 kb
Host smart-6c26dbcf-92e1-4d35-b135-6d20794742dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171054698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_te
st.4171054698
Directory /workspace/18.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1953187846
Short name T793
Test name
Test status
Simulation time 3655380624 ps
CPU time 5.34 seconds
Started Jul 21 06:38:16 PM PDT 24
Finished Jul 21 06:38:23 PM PDT 24
Peak memory 201536 kb
Host smart-168d77e1-245f-4f87-93f0-ef223ff7c4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953187846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1
953187846
Directory /workspace/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_combo_detect.2568249727
Short name T680
Test name
Test status
Simulation time 89083576678 ps
CPU time 120.07 seconds
Started Jul 21 06:38:15 PM PDT 24
Finished Jul 21 06:40:17 PM PDT 24
Peak memory 201868 kb
Host smart-15fae854-287b-47d3-91c2-42b63e1acbba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568249727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_c
trl_combo_detect.2568249727
Directory /workspace/18.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.3777587584
Short name T392
Test name
Test status
Simulation time 4128193099 ps
CPU time 11.83 seconds
Started Jul 21 06:38:22 PM PDT 24
Finished Jul 21 06:38:35 PM PDT 24
Peak memory 201524 kb
Host smart-e007d0d9-9f74-43eb-80c9-7b6e48dc8f93
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777587584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_
ctrl_ec_pwr_on_rst.3777587584
Directory /workspace/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_edge_detect.1226373285
Short name T455
Test name
Test status
Simulation time 2575526491 ps
CPU time 1.89 seconds
Started Jul 21 06:38:23 PM PDT 24
Finished Jul 21 06:38:26 PM PDT 24
Peak memory 201576 kb
Host smart-40b51ee3-aa21-4668-9f16-56892b4b53f6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226373285 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_edge_detect.1226373285
Directory /workspace/18.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.1449260183
Short name T745
Test name
Test status
Simulation time 2617987944 ps
CPU time 4.15 seconds
Started Jul 21 06:38:18 PM PDT 24
Finished Jul 21 06:38:23 PM PDT 24
Peak memory 201556 kb
Host smart-fba71e6c-2e97-4363-9d4d-b5c2c7adc7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449260183 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.1449260183
Directory /workspace/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_in_out_inverted.4154281303
Short name T469
Test name
Test status
Simulation time 2455377608 ps
CPU time 2.11 seconds
Started Jul 21 06:38:20 PM PDT 24
Finished Jul 21 06:38:22 PM PDT 24
Peak memory 201576 kb
Host smart-3dc17659-6fcb-4b69-946f-f6b3ee84bbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154281303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.4154281303
Directory /workspace/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_access_test.3704929503
Short name T575
Test name
Test status
Simulation time 2060791572 ps
CPU time 3.22 seconds
Started Jul 21 06:38:15 PM PDT 24
Finished Jul 21 06:38:19 PM PDT 24
Peak memory 201508 kb
Host smart-0620f969-ac88-4eb0-8158-bd1f32d88945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704929503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.3704929503
Directory /workspace/18.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.1499591280
Short name T175
Test name
Test status
Simulation time 2511828763 ps
CPU time 7.15 seconds
Started Jul 21 06:38:22 PM PDT 24
Finished Jul 21 06:38:30 PM PDT 24
Peak memory 201532 kb
Host smart-b44a935d-a71a-46d5-9160-19e4fd686de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499591280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.1499591280
Directory /workspace/18.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_smoke.3813354012
Short name T441
Test name
Test status
Simulation time 2118539957 ps
CPU time 3.08 seconds
Started Jul 21 06:38:13 PM PDT 24
Finished Jul 21 06:38:17 PM PDT 24
Peak memory 201480 kb
Host smart-711521fa-a739-4c3a-b56b-720bf7684576
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813354012 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.3813354012
Directory /workspace/18.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all.3803971895
Short name T39
Test name
Test status
Simulation time 666475203644 ps
CPU time 78.85 seconds
Started Jul 21 06:38:17 PM PDT 24
Finished Jul 21 06:39:37 PM PDT 24
Peak memory 201528 kb
Host smart-91438245-e92a-4c6c-96d3-37b5c20f3024
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803971895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_s
tress_all.3803971895
Directory /workspace/18.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.523097647
Short name T492
Test name
Test status
Simulation time 22066694334 ps
CPU time 50.43 seconds
Started Jul 21 06:38:17 PM PDT 24
Finished Jul 21 06:39:08 PM PDT 24
Peak memory 217632 kb
Host smart-38be574a-55e5-4a90-8457-1c05f7dbe5f7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523097647 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.523097647
Directory /workspace/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.sysrst_ctrl_ultra_low_pwr.21883578
Short name T126
Test name
Test status
Simulation time 9216435921 ps
CPU time 1.77 seconds
Started Jul 21 06:38:12 PM PDT 24
Finished Jul 21 06:38:15 PM PDT 24
Peak memory 201488 kb
Host smart-9ee1f018-4915-48c4-9508-a77bd0a73e79
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21883578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ct
rl_ultra_low_pwr.21883578
Directory /workspace/18.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_alert_test.4155488907
Short name T275
Test name
Test status
Simulation time 2017132634 ps
CPU time 3.17 seconds
Started Jul 21 06:38:18 PM PDT 24
Finished Jul 21 06:38:22 PM PDT 24
Peak memory 201548 kb
Host smart-54760523-aa2c-4d17-9b75-cb8cc88ea06a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155488907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_te
st.4155488907
Directory /workspace/19.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_auto_blk_key_output.2748260525
Short name T607
Test name
Test status
Simulation time 3217952428 ps
CPU time 8.1 seconds
Started Jul 21 06:38:28 PM PDT 24
Finished Jul 21 06:38:37 PM PDT 24
Peak memory 201468 kb
Host smart-8f0e7d75-9d12-46a9-9c4b-ff87b61adb8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748260525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.2
748260525
Directory /workspace/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_combo_detect.3765363470
Short name T340
Test name
Test status
Simulation time 74129472874 ps
CPU time 184.68 seconds
Started Jul 21 06:38:19 PM PDT 24
Finished Jul 21 06:41:24 PM PDT 24
Peak memory 201756 kb
Host smart-a98feb19-4394-4224-80b1-880cd915c30e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765363470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_c
trl_combo_detect.3765363470
Directory /workspace/19.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.2791418526
Short name T382
Test name
Test status
Simulation time 4599176427 ps
CPU time 3.48 seconds
Started Jul 21 06:38:19 PM PDT 24
Finished Jul 21 06:38:23 PM PDT 24
Peak memory 201540 kb
Host smart-532eace3-8730-47ca-875d-c8c74435b50f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791418526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ec_pwr_on_rst.2791418526
Directory /workspace/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_edge_detect.2990329866
Short name T196
Test name
Test status
Simulation time 5862598632 ps
CPU time 13.77 seconds
Started Jul 21 06:38:14 PM PDT 24
Finished Jul 21 06:38:29 PM PDT 24
Peak memory 201540 kb
Host smart-8992380a-5f73-478f-9608-e0b9f9fdd52d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990329866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ct
rl_edge_detect.2990329866
Directory /workspace/19.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3327653743
Short name T307
Test name
Test status
Simulation time 2618052004 ps
CPU time 4.25 seconds
Started Jul 21 06:38:22 PM PDT 24
Finished Jul 21 06:38:27 PM PDT 24
Peak memory 201548 kb
Host smart-44e6f4ba-d812-455b-b8f4-8c87f2f25863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327653743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.3327653743
Directory /workspace/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_in_out_inverted.976899087
Short name T624
Test name
Test status
Simulation time 2466882346 ps
CPU time 4.41 seconds
Started Jul 21 06:38:14 PM PDT 24
Finished Jul 21 06:38:20 PM PDT 24
Peak memory 201528 kb
Host smart-5437803f-eef1-4467-9f1a-5bc8e704636d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=976899087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.976899087
Directory /workspace/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_access_test.3008006877
Short name T662
Test name
Test status
Simulation time 2052821212 ps
CPU time 1.8 seconds
Started Jul 21 06:38:15 PM PDT 24
Finished Jul 21 06:38:18 PM PDT 24
Peak memory 201512 kb
Host smart-7d9187f6-9a14-4edd-b941-91ead76cc34e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008006877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.3008006877
Directory /workspace/19.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_pin_override_test.3675877619
Short name T500
Test name
Test status
Simulation time 2510392414 ps
CPU time 7.01 seconds
Started Jul 21 06:38:17 PM PDT 24
Finished Jul 21 06:38:25 PM PDT 24
Peak memory 201536 kb
Host smart-70c3e2ac-eb96-4b1b-8b44-acee1bf0be51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675877619 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.3675877619
Directory /workspace/19.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_smoke.4134620033
Short name T518
Test name
Test status
Simulation time 2136569037 ps
CPU time 1.83 seconds
Started Jul 21 06:38:20 PM PDT 24
Finished Jul 21 06:38:23 PM PDT 24
Peak memory 201476 kb
Host smart-7a524712-80b4-4409-97a2-9afc038fc531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134620033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.4134620033
Directory /workspace/19.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_stress_all.3440519942
Short name T686
Test name
Test status
Simulation time 14491411600 ps
CPU time 9.75 seconds
Started Jul 21 06:38:15 PM PDT 24
Finished Jul 21 06:38:27 PM PDT 24
Peak memory 201448 kb
Host smart-2e2252b9-3cee-41a4-8fae-0df9397abc2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440519942 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_s
tress_all.3440519942
Directory /workspace/19.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2763662887
Short name T652
Test name
Test status
Simulation time 7305611235 ps
CPU time 2.31 seconds
Started Jul 21 06:38:13 PM PDT 24
Finished Jul 21 06:38:16 PM PDT 24
Peak memory 201544 kb
Host smart-c0e61339-5dfa-4c1b-aa6b-fd5b12630e45
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763662887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_
ctrl_ultra_low_pwr.2763662887
Directory /workspace/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_alert_test.1392323603
Short name T631
Test name
Test status
Simulation time 2012180205 ps
CPU time 5.87 seconds
Started Jul 21 06:37:42 PM PDT 24
Finished Jul 21 06:37:48 PM PDT 24
Peak memory 201584 kb
Host smart-9a49d266-ccd0-4d26-8a92-66017f71b0c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392323603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_tes
t.1392323603
Directory /workspace/2.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_auto_blk_key_output.1011778680
Short name T687
Test name
Test status
Simulation time 3424781781 ps
CPU time 9.77 seconds
Started Jul 21 06:37:37 PM PDT 24
Finished Jul 21 06:37:48 PM PDT 24
Peak memory 201668 kb
Host smart-02fdc67c-ade6-4ae1-a9ec-92cafa22cb09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011778680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.1011778680
Directory /workspace/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect.203812489
Short name T35
Test name
Test status
Simulation time 174782065836 ps
CPU time 431.67 seconds
Started Jul 21 06:37:43 PM PDT 24
Finished Jul 21 06:44:56 PM PDT 24
Peak memory 201696 kb
Host smart-5b40368d-f9c3-4784-b548-9f9b972960aa
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203812489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_combo_detect.203812489
Directory /workspace/2.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.4203131202
Short name T463
Test name
Test status
Simulation time 2273257671 ps
CPU time 3.54 seconds
Started Jul 21 06:37:48 PM PDT 24
Finished Jul 21 06:37:52 PM PDT 24
Peak memory 201512 kb
Host smart-d92a3200-279a-46a2-b04a-d104afa2aad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203131202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.4203131202
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4008069613
Short name T792
Test name
Test status
Simulation time 2271291898 ps
CPU time 2.06 seconds
Started Jul 21 06:37:43 PM PDT 24
Finished Jul 21 06:37:46 PM PDT 24
Peak memory 201600 kb
Host smart-2269a268-def8-4d28-8fb4-1c4c775ddc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008069613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.4008069613
Directory /workspace/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2892418104
Short name T83
Test name
Test status
Simulation time 36186706733 ps
CPU time 47.27 seconds
Started Jul 21 06:37:45 PM PDT 24
Finished Jul 21 06:38:33 PM PDT 24
Peak memory 201852 kb
Host smart-861ebe72-69e3-4bbf-9385-a2d76785a9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892418104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_wi
th_pre_cond.2892418104
Directory /workspace/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.1180225294
Short name T729
Test name
Test status
Simulation time 1324523255312 ps
CPU time 870.8 seconds
Started Jul 21 06:37:36 PM PDT 24
Finished Jul 21 06:52:08 PM PDT 24
Peak memory 201552 kb
Host smart-6d110422-9bd6-4d09-9296-b3b6294a4f16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180225294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ec_pwr_on_rst.1180225294
Directory /workspace/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_edge_detect.2609695924
Short name T571
Test name
Test status
Simulation time 2572529157 ps
CPU time 5.79 seconds
Started Jul 21 06:37:46 PM PDT 24
Finished Jul 21 06:37:53 PM PDT 24
Peak memory 201536 kb
Host smart-dadd32c5-c034-4477-adda-0cf229435105
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609695924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctr
l_edge_detect.2609695924
Directory /workspace/2.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1046931931
Short name T381
Test name
Test status
Simulation time 2611628596 ps
CPU time 7.58 seconds
Started Jul 21 06:37:36 PM PDT 24
Finished Jul 21 06:37:44 PM PDT 24
Peak memory 201532 kb
Host smart-38783720-b090-4345-b45b-4f6e4049d38e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046931931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1046931931
Directory /workspace/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.260903163
Short name T68
Test name
Test status
Simulation time 2498452935 ps
CPU time 2.34 seconds
Started Jul 21 06:37:43 PM PDT 24
Finished Jul 21 06:37:46 PM PDT 24
Peak memory 201548 kb
Host smart-ce637c40-7465-4b4a-a550-b9a38a543ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260903163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.260903163
Directory /workspace/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2421876936
Short name T52
Test name
Test status
Simulation time 2112278690 ps
CPU time 2.32 seconds
Started Jul 21 06:37:37 PM PDT 24
Finished Jul 21 06:37:41 PM PDT 24
Peak memory 201524 kb
Host smart-20c8652d-d871-4f43-860b-96ada91249cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421876936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.2421876936
Directory /workspace/2.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_pin_override_test.930878833
Short name T222
Test name
Test status
Simulation time 2517321686 ps
CPU time 3.97 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:37:57 PM PDT 24
Peak memory 201548 kb
Host smart-85d99ef0-5457-4816-9874-9be12d577318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930878833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.930878833
Directory /workspace/2.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_sec_cm.3620480892
Short name T263
Test name
Test status
Simulation time 42011210923 ps
CPU time 104.96 seconds
Started Jul 21 06:37:46 PM PDT 24
Finished Jul 21 06:39:32 PM PDT 24
Peak memory 220880 kb
Host smart-6de883e1-8291-470c-b422-277282075431
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620480892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.3620480892
Directory /workspace/2.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_smoke.2487074465
Short name T620
Test name
Test status
Simulation time 2139267763 ps
CPU time 1.86 seconds
Started Jul 21 06:37:37 PM PDT 24
Finished Jul 21 06:37:40 PM PDT 24
Peak memory 201440 kb
Host smart-1294b5b1-04c5-41d5-8b78-d48a9d88eec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487074465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.2487074465
Directory /workspace/2.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2154743451
Short name T395
Test name
Test status
Simulation time 6784572928 ps
CPU time 2.19 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:37:56 PM PDT 24
Peak memory 201524 kb
Host smart-7f631fb8-7bfc-4e80-b893-ea7bb0d0fe16
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154743451 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_c
trl_ultra_low_pwr.2154743451
Directory /workspace/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_alert_test.3981102673
Short name T468
Test name
Test status
Simulation time 2013527055 ps
CPU time 5.96 seconds
Started Jul 21 06:38:27 PM PDT 24
Finished Jul 21 06:38:34 PM PDT 24
Peak memory 201528 kb
Host smart-2a22c3d6-9e7f-4b6c-b937-9968c93020a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981102673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_te
st.3981102673
Directory /workspace/20.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3043358684
Short name T401
Test name
Test status
Simulation time 3634401878 ps
CPU time 1.59 seconds
Started Jul 21 06:38:28 PM PDT 24
Finished Jul 21 06:38:31 PM PDT 24
Peak memory 201472 kb
Host smart-74352787-bf0f-446d-b6cb-6da942b2ff4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043358684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.3
043358684
Directory /workspace/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect.2878753370
Short name T248
Test name
Test status
Simulation time 160427712802 ps
CPU time 410.27 seconds
Started Jul 21 06:38:17 PM PDT 24
Finished Jul 21 06:45:08 PM PDT 24
Peak memory 201848 kb
Host smart-33bfd9e8-27fe-4148-bcd6-4e38ae533302
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878753370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_combo_detect.2878753370
Directory /workspace/20.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2620650113
Short name T255
Test name
Test status
Simulation time 77666947204 ps
CPU time 197.26 seconds
Started Jul 21 06:38:26 PM PDT 24
Finished Jul 21 06:41:44 PM PDT 24
Peak memory 201820 kb
Host smart-5b206e2f-083f-4255-ab04-32331a62fce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620650113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_w
ith_pre_cond.2620650113
Directory /workspace/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.4074970238
Short name T433
Test name
Test status
Simulation time 5196347116 ps
CPU time 4.15 seconds
Started Jul 21 06:38:17 PM PDT 24
Finished Jul 21 06:38:22 PM PDT 24
Peak memory 201528 kb
Host smart-522484db-b467-493f-8644-d296ac849280
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074970238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_
ctrl_ec_pwr_on_rst.4074970238
Directory /workspace/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_edge_detect.3082718473
Short name T722
Test name
Test status
Simulation time 2373847110 ps
CPU time 6.56 seconds
Started Jul 21 06:38:22 PM PDT 24
Finished Jul 21 06:38:30 PM PDT 24
Peak memory 201484 kb
Host smart-c7a57258-5508-4767-8682-e7c1eb5c998b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082718473 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ct
rl_edge_detect.3082718473
Directory /workspace/20.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.50086669
Short name T797
Test name
Test status
Simulation time 2623166331 ps
CPU time 2.37 seconds
Started Jul 21 06:38:20 PM PDT 24
Finished Jul 21 06:38:23 PM PDT 24
Peak memory 201472 kb
Host smart-3b8c9d37-2643-4846-879f-eff9d0727ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50086669 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.50086669
Directory /workspace/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_in_out_inverted.55272419
Short name T573
Test name
Test status
Simulation time 2472478599 ps
CPU time 4.35 seconds
Started Jul 21 06:38:14 PM PDT 24
Finished Jul 21 06:38:20 PM PDT 24
Peak memory 201552 kb
Host smart-0be4ceba-af02-42a3-909a-97bf2e23fd5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55272419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.55272419
Directory /workspace/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_access_test.1803263841
Short name T650
Test name
Test status
Simulation time 2123624574 ps
CPU time 1.89 seconds
Started Jul 21 06:38:17 PM PDT 24
Finished Jul 21 06:38:20 PM PDT 24
Peak memory 201468 kb
Host smart-069a0304-5204-4768-b8c4-bb567f23fe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803263841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.1803263841
Directory /workspace/20.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_pin_override_test.947864179
Short name T453
Test name
Test status
Simulation time 2517883651 ps
CPU time 4.05 seconds
Started Jul 21 06:38:16 PM PDT 24
Finished Jul 21 06:38:21 PM PDT 24
Peak memory 201516 kb
Host smart-cbfd209c-a428-48f5-9e2c-ab5e94fea4d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947864179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.947864179
Directory /workspace/20.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_smoke.977764030
Short name T563
Test name
Test status
Simulation time 2115846269 ps
CPU time 3.32 seconds
Started Jul 21 06:38:22 PM PDT 24
Finished Jul 21 06:38:26 PM PDT 24
Peak memory 201476 kb
Host smart-1b44d894-7411-41b3-819f-2a1ae63134f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977764030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.977764030
Directory /workspace/20.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all.1709266128
Short name T315
Test name
Test status
Simulation time 6731162015 ps
CPU time 18.53 seconds
Started Jul 21 06:38:20 PM PDT 24
Finished Jul 21 06:38:40 PM PDT 24
Peak memory 201532 kb
Host smart-de6a1566-bd04-46a4-8822-0269c1ab3f71
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709266128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_s
tress_all.1709266128
Directory /workspace/20.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.647617247
Short name T784
Test name
Test status
Simulation time 33786283344 ps
CPU time 76.58 seconds
Started Jul 21 06:38:19 PM PDT 24
Finished Jul 21 06:39:36 PM PDT 24
Peak memory 218252 kb
Host smart-b96183ff-632e-4cf9-bf8e-16bad365a661
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647617247 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.647617247
Directory /workspace/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.sysrst_ctrl_ultra_low_pwr.247222489
Short name T715
Test name
Test status
Simulation time 10327206033 ps
CPU time 4.26 seconds
Started Jul 21 06:38:19 PM PDT 24
Finished Jul 21 06:38:24 PM PDT 24
Peak memory 201568 kb
Host smart-b8075648-d957-4908-acd1-64304ad2b678
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247222489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_c
trl_ultra_low_pwr.247222489
Directory /workspace/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_alert_test.3580270259
Short name T431
Test name
Test status
Simulation time 2026053128 ps
CPU time 1.87 seconds
Started Jul 21 06:38:29 PM PDT 24
Finished Jul 21 06:38:32 PM PDT 24
Peak memory 201572 kb
Host smart-28096bfa-f0f8-411c-ab73-22eddb524b52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580270259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_te
st.3580270259
Directory /workspace/21.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_auto_blk_key_output.819302568
Short name T795
Test name
Test status
Simulation time 3417179788 ps
CPU time 10.05 seconds
Started Jul 21 06:38:27 PM PDT 24
Finished Jul 21 06:38:38 PM PDT 24
Peak memory 201568 kb
Host smart-b6935854-2fd4-46a3-8db5-fb99a03f3ca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819302568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.819302568
Directory /workspace/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3723401267
Short name T251
Test name
Test status
Simulation time 99280462454 ps
CPU time 261.14 seconds
Started Jul 21 06:38:27 PM PDT 24
Finished Jul 21 06:42:48 PM PDT 24
Peak memory 201856 kb
Host smart-b0c4aae0-0c7a-4489-b0f9-ff3312f39cbf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723401267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_c
trl_combo_detect.3723401267
Directory /workspace/21.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3865357802
Short name T160
Test name
Test status
Simulation time 59828926826 ps
CPU time 161.94 seconds
Started Jul 21 06:38:28 PM PDT 24
Finished Jul 21 06:41:11 PM PDT 24
Peak memory 201916 kb
Host smart-2efeb097-4fce-4b82-8157-9c0a0f15a0d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865357802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_w
ith_pre_cond.3865357802
Directory /workspace/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3966642866
Short name T405
Test name
Test status
Simulation time 2776470326 ps
CPU time 8.14 seconds
Started Jul 21 06:38:20 PM PDT 24
Finished Jul 21 06:38:28 PM PDT 24
Peak memory 201484 kb
Host smart-39cc8e2d-acd5-4f77-bf9f-1a0e100db957
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966642866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_
ctrl_ec_pwr_on_rst.3966642866
Directory /workspace/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_edge_detect.2143715460
Short name T459
Test name
Test status
Simulation time 2668016186 ps
CPU time 6.6 seconds
Started Jul 21 06:38:24 PM PDT 24
Finished Jul 21 06:38:31 PM PDT 24
Peak memory 201544 kb
Host smart-7f89e472-9a52-4213-8e88-3208e78a6562
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143715460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ct
rl_edge_detect.2143715460
Directory /workspace/21.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.194548766
Short name T192
Test name
Test status
Simulation time 2697204741 ps
CPU time 1.08 seconds
Started Jul 21 06:38:20 PM PDT 24
Finished Jul 21 06:38:22 PM PDT 24
Peak memory 201564 kb
Host smart-794a1649-7daf-4036-b5f9-8c4ed9f6e2d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194548766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.194548766
Directory /workspace/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_in_out_inverted.2638669802
Short name T671
Test name
Test status
Simulation time 2467132230 ps
CPU time 7.64 seconds
Started Jul 21 06:38:20 PM PDT 24
Finished Jul 21 06:38:28 PM PDT 24
Peak memory 201564 kb
Host smart-4c629dda-8709-4af3-bf38-e760477ab728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638669802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.2638669802
Directory /workspace/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_access_test.2025632911
Short name T529
Test name
Test status
Simulation time 2122237509 ps
CPU time 1.81 seconds
Started Jul 21 06:38:27 PM PDT 24
Finished Jul 21 06:38:29 PM PDT 24
Peak memory 201468 kb
Host smart-1acb2ff0-6942-42c1-bf57-18fc4109c346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2025632911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.2025632911
Directory /workspace/21.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_pin_override_test.3766288959
Short name T182
Test name
Test status
Simulation time 2508652691 ps
CPU time 7.13 seconds
Started Jul 21 06:38:24 PM PDT 24
Finished Jul 21 06:38:31 PM PDT 24
Peak memory 201540 kb
Host smart-8453d702-c4c8-4d46-86f9-14b0b016490b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766288959 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.3766288959
Directory /workspace/21.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_smoke.2646941889
Short name T605
Test name
Test status
Simulation time 2109043828 ps
CPU time 6.35 seconds
Started Jul 21 06:38:23 PM PDT 24
Finished Jul 21 06:38:30 PM PDT 24
Peak memory 201440 kb
Host smart-358cdd15-88a6-4e56-9b85-f2ee0f1db65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646941889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.2646941889
Directory /workspace/21.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/21.sysrst_ctrl_stress_all.2814864931
Short name T139
Test name
Test status
Simulation time 9319625851 ps
CPU time 5.74 seconds
Started Jul 21 06:38:20 PM PDT 24
Finished Jul 21 06:38:27 PM PDT 24
Peak memory 201572 kb
Host smart-9a0f661e-5587-4fc9-808a-cb7182a0387d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814864931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_s
tress_all.2814864931
Directory /workspace/21.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_alert_test.1905622772
Short name T720
Test name
Test status
Simulation time 2011699404 ps
CPU time 5.53 seconds
Started Jul 21 06:38:28 PM PDT 24
Finished Jul 21 06:38:34 PM PDT 24
Peak memory 201556 kb
Host smart-190b4695-ae75-4f1b-9280-76c1d3b4a461
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905622772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_te
st.1905622772
Directory /workspace/22.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2471420415
Short name T287
Test name
Test status
Simulation time 3385675494 ps
CPU time 8.74 seconds
Started Jul 21 06:38:37 PM PDT 24
Finished Jul 21 06:38:46 PM PDT 24
Peak memory 201760 kb
Host smart-a383483f-0c31-4143-a586-39210d6b9b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471420415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.2
471420415
Directory /workspace/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.3927330237
Short name T773
Test name
Test status
Simulation time 31221937593 ps
CPU time 85.69 seconds
Started Jul 21 06:38:37 PM PDT 24
Finished Jul 21 06:40:03 PM PDT 24
Peak memory 201864 kb
Host smart-29960c29-7c20-4a01-b5cf-0e0088efbe58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927330237 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_w
ith_pre_cond.3927330237
Directory /workspace/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.1809247326
Short name T677
Test name
Test status
Simulation time 1176886748306 ps
CPU time 3044.29 seconds
Started Jul 21 06:38:29 PM PDT 24
Finished Jul 21 07:29:15 PM PDT 24
Peak memory 201512 kb
Host smart-5260fd0a-17c3-4033-9a64-b758ab715667
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809247326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ec_pwr_on_rst.1809247326
Directory /workspace/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_edge_detect.3500804603
Short name T42
Test name
Test status
Simulation time 6185423178 ps
CPU time 2.11 seconds
Started Jul 21 06:38:35 PM PDT 24
Finished Jul 21 06:38:38 PM PDT 24
Peak memory 201556 kb
Host smart-7f7c0976-dc6e-4400-96ae-6ddd9cdeaf27
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500804603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ct
rl_edge_detect.3500804603
Directory /workspace/22.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3680103856
Short name T579
Test name
Test status
Simulation time 2616259642 ps
CPU time 5.78 seconds
Started Jul 21 06:38:38 PM PDT 24
Finished Jul 21 06:38:44 PM PDT 24
Peak memory 201708 kb
Host smart-fea190ed-2e63-4f0d-832b-3933942b2e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680103856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3680103856
Directory /workspace/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_in_out_inverted.2959429826
Short name T704
Test name
Test status
Simulation time 2451195458 ps
CPU time 7.13 seconds
Started Jul 21 06:38:35 PM PDT 24
Finished Jul 21 06:38:43 PM PDT 24
Peak memory 201540 kb
Host smart-ba225863-e9da-412c-869a-5e8783063140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959429826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.2959429826
Directory /workspace/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_access_test.3970685944
Short name T570
Test name
Test status
Simulation time 2163365720 ps
CPU time 5.56 seconds
Started Jul 21 06:38:38 PM PDT 24
Finished Jul 21 06:38:44 PM PDT 24
Peak memory 201712 kb
Host smart-bbbf47fe-6b17-4270-b587-000a1d0aefe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970685944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.3970685944
Directory /workspace/22.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_pin_override_test.619294375
Short name T600
Test name
Test status
Simulation time 2509785111 ps
CPU time 6.74 seconds
Started Jul 21 06:38:29 PM PDT 24
Finished Jul 21 06:38:37 PM PDT 24
Peak memory 201580 kb
Host smart-b6e3c1d9-a5cc-430c-b815-4c773f10dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619294375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.619294375
Directory /workspace/22.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_smoke.130045027
Short name T789
Test name
Test status
Simulation time 2109475119 ps
CPU time 6.13 seconds
Started Jul 21 06:38:28 PM PDT 24
Finished Jul 21 06:38:35 PM PDT 24
Peak memory 201508 kb
Host smart-3d76fd9e-7c72-49c7-96a6-3c11eb80a5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130045027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.130045027
Directory /workspace/22.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all.1502869478
Short name T103
Test name
Test status
Simulation time 115498649423 ps
CPU time 157.7 seconds
Started Jul 21 06:38:37 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 201928 kb
Host smart-c9fff44c-0031-4179-98e8-ac4d5f46d2d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502869478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_s
tress_all.1502869478
Directory /workspace/22.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2126494960
Short name T166
Test name
Test status
Simulation time 33976395098 ps
CPU time 84.56 seconds
Started Jul 21 06:38:42 PM PDT 24
Finished Jul 21 06:40:07 PM PDT 24
Peak memory 210252 kb
Host smart-487ecafe-36c2-40e0-b487-bf93e3a9a2d0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126494960 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.2126494960
Directory /workspace/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.sysrst_ctrl_ultra_low_pwr.3323851870
Short name T466
Test name
Test status
Simulation time 6306178127 ps
CPU time 2.43 seconds
Started Jul 21 06:38:31 PM PDT 24
Finished Jul 21 06:38:34 PM PDT 24
Peak memory 201576 kb
Host smart-a0065588-9ac1-4498-bace-b75aed373561
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323851870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_
ctrl_ultra_low_pwr.3323851870
Directory /workspace/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_alert_test.511547413
Short name T696
Test name
Test status
Simulation time 2010646271 ps
CPU time 6.03 seconds
Started Jul 21 06:38:33 PM PDT 24
Finished Jul 21 06:38:39 PM PDT 24
Peak memory 201520 kb
Host smart-ba00f008-e6c4-477c-8751-f540b2d03445
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511547413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_tes
t.511547413
Directory /workspace/23.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3611082163
Short name T476
Test name
Test status
Simulation time 3636696262 ps
CPU time 5.06 seconds
Started Jul 21 06:38:34 PM PDT 24
Finished Jul 21 06:38:40 PM PDT 24
Peak memory 201600 kb
Host smart-60f81ca0-bc4e-47a2-84ee-01db04c9e5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611082163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.3
611082163
Directory /workspace/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3851373616
Short name T744
Test name
Test status
Simulation time 27102047011 ps
CPU time 18.73 seconds
Started Jul 21 06:38:29 PM PDT 24
Finished Jul 21 06:38:49 PM PDT 24
Peak memory 201936 kb
Host smart-c52519ef-1a37-4802-8e07-5e0118d76586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851373616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_w
ith_pre_cond.3851373616
Directory /workspace/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.2753347779
Short name T682
Test name
Test status
Simulation time 3269433971 ps
CPU time 4.25 seconds
Started Jul 21 06:38:29 PM PDT 24
Finished Jul 21 06:38:35 PM PDT 24
Peak memory 201516 kb
Host smart-9cde19ff-2c08-484d-88ee-0ff12e773c68
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753347779 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_
ctrl_ec_pwr_on_rst.2753347779
Directory /workspace/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_edge_detect.457784189
Short name T186
Test name
Test status
Simulation time 3045993093 ps
CPU time 4.58 seconds
Started Jul 21 06:38:30 PM PDT 24
Finished Jul 21 06:38:35 PM PDT 24
Peak memory 201552 kb
Host smart-fe86aac7-e3e2-4626-8154-3ba02998ca91
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457784189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctr
l_edge_detect.457784189
Directory /workspace/23.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3529539497
Short name T171
Test name
Test status
Simulation time 2630564533 ps
CPU time 2.43 seconds
Started Jul 21 06:38:29 PM PDT 24
Finished Jul 21 06:38:33 PM PDT 24
Peak memory 201512 kb
Host smart-cf316d9b-c465-44b3-87d3-cebc26ed622a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529539497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.3529539497
Directory /workspace/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.2989407219
Short name T296
Test name
Test status
Simulation time 2501056072 ps
CPU time 1.79 seconds
Started Jul 21 06:38:37 PM PDT 24
Finished Jul 21 06:38:40 PM PDT 24
Peak memory 201712 kb
Host smart-20416a76-f2e4-4582-81a7-78d87340cab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989407219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.2989407219
Directory /workspace/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1958609945
Short name T398
Test name
Test status
Simulation time 2201178766 ps
CPU time 1.9 seconds
Started Jul 21 06:38:29 PM PDT 24
Finished Jul 21 06:38:32 PM PDT 24
Peak memory 201560 kb
Host smart-204eef9e-291d-427f-8770-946225e97fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958609945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1958609945
Directory /workspace/23.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_pin_override_test.2866245277
Short name T675
Test name
Test status
Simulation time 2522812476 ps
CPU time 2.39 seconds
Started Jul 21 06:38:28 PM PDT 24
Finished Jul 21 06:38:32 PM PDT 24
Peak memory 201580 kb
Host smart-bd71635f-3786-4d3d-971c-581b9fea8217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866245277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.2866245277
Directory /workspace/23.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_smoke.3882587589
Short name T545
Test name
Test status
Simulation time 2132622277 ps
CPU time 1.82 seconds
Started Jul 21 06:38:29 PM PDT 24
Finished Jul 21 06:38:32 PM PDT 24
Peak memory 201492 kb
Host smart-2558f539-6198-488e-ac26-6d98169e83fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882587589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.3882587589
Directory /workspace/23.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all.1982232002
Short name T366
Test name
Test status
Simulation time 11452582554 ps
CPU time 6.67 seconds
Started Jul 21 06:38:29 PM PDT 24
Finished Jul 21 06:38:37 PM PDT 24
Peak memory 201548 kb
Host smart-1ba78c17-402b-48c6-9518-60529882ca43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982232002 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_s
tress_all.1982232002
Directory /workspace/23.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.450049163
Short name T245
Test name
Test status
Simulation time 78023424574 ps
CPU time 102.99 seconds
Started Jul 21 06:38:27 PM PDT 24
Finished Jul 21 06:40:10 PM PDT 24
Peak memory 210140 kb
Host smart-710cdabd-6556-4af6-a134-f7d8c7a7e5a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450049163 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.450049163
Directory /workspace/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_alert_test.3633178573
Short name T742
Test name
Test status
Simulation time 2032891323 ps
CPU time 1.79 seconds
Started Jul 21 06:38:36 PM PDT 24
Finished Jul 21 06:38:39 PM PDT 24
Peak memory 200800 kb
Host smart-9025225b-953d-4ae5-8899-48194ceff54e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633178573 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_te
st.3633178573
Directory /workspace/24.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3893145834
Short name T399
Test name
Test status
Simulation time 3945110133 ps
CPU time 2.93 seconds
Started Jul 21 06:38:30 PM PDT 24
Finished Jul 21 06:38:33 PM PDT 24
Peak memory 201628 kb
Host smart-2e97f63c-8a77-4c3d-9d70-5de4eb65287f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893145834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.3
893145834
Directory /workspace/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect.823270490
Short name T335
Test name
Test status
Simulation time 105083517900 ps
CPU time 275.31 seconds
Started Jul 21 06:38:34 PM PDT 24
Finished Jul 21 06:43:09 PM PDT 24
Peak memory 201744 kb
Host smart-3d632ab9-c76d-412e-8a51-f299ce5c6f5a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823270490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_combo_detect.823270490
Directory /workspace/24.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.230751898
Short name T123
Test name
Test status
Simulation time 27342214822 ps
CPU time 19.2 seconds
Started Jul 21 06:38:33 PM PDT 24
Finished Jul 21 06:38:52 PM PDT 24
Peak memory 201892 kb
Host smart-a0ae84de-e222-4962-a012-c52488dfde54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230751898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_wi
th_pre_cond.230751898
Directory /workspace/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.4086784271
Short name T397
Test name
Test status
Simulation time 2605729813 ps
CPU time 6.88 seconds
Started Jul 21 06:38:29 PM PDT 24
Finished Jul 21 06:38:37 PM PDT 24
Peak memory 201528 kb
Host smart-3cd78dfc-8a5a-4f72-960d-0f678c450bcd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086784271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ec_pwr_on_rst.4086784271
Directory /workspace/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_edge_detect.1333604505
Short name T8
Test name
Test status
Simulation time 3435988556 ps
CPU time 8.72 seconds
Started Jul 21 06:38:34 PM PDT 24
Finished Jul 21 06:38:44 PM PDT 24
Peak memory 201512 kb
Host smart-91e03fd0-c5da-4866-94e6-98a7fad3fd7f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333604505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ct
rl_edge_detect.1333604505
Directory /workspace/24.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2395225246
Short name T121
Test name
Test status
Simulation time 2620274975 ps
CPU time 4.45 seconds
Started Jul 21 06:38:34 PM PDT 24
Finished Jul 21 06:38:40 PM PDT 24
Peak memory 201544 kb
Host smart-d23a1f13-3d98-4786-a82b-6963d17f85fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395225246 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.2395225246
Directory /workspace/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_in_out_inverted.3441475843
Short name T623
Test name
Test status
Simulation time 2467005727 ps
CPU time 7.17 seconds
Started Jul 21 06:38:38 PM PDT 24
Finished Jul 21 06:38:46 PM PDT 24
Peak memory 201712 kb
Host smart-c9d32975-adb2-444d-b8f6-86392c80cde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441475843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3441475843
Directory /workspace/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.2120484393
Short name T428
Test name
Test status
Simulation time 2235185080 ps
CPU time 6.45 seconds
Started Jul 21 06:38:37 PM PDT 24
Finished Jul 21 06:38:44 PM PDT 24
Peak memory 201716 kb
Host smart-e12fa8bc-e471-478e-b8cc-9033d3d4cf9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120484393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.2120484393
Directory /workspace/24.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2673990607
Short name T434
Test name
Test status
Simulation time 2513521969 ps
CPU time 3.9 seconds
Started Jul 21 06:38:27 PM PDT 24
Finished Jul 21 06:38:32 PM PDT 24
Peak memory 201584 kb
Host smart-141058d3-d7c4-48a9-8f66-1f8545e3e9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673990607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2673990607
Directory /workspace/24.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_smoke.1690385647
Short name T210
Test name
Test status
Simulation time 2109450288 ps
CPU time 5.54 seconds
Started Jul 21 06:38:28 PM PDT 24
Finished Jul 21 06:38:35 PM PDT 24
Peak memory 201512 kb
Host smart-df786168-d09a-48ba-967d-156f4754e77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690385647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.1690385647
Directory /workspace/24.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_stress_all.2853640125
Short name T796
Test name
Test status
Simulation time 15552125992 ps
CPU time 39.88 seconds
Started Jul 21 06:38:44 PM PDT 24
Finished Jul 21 06:39:24 PM PDT 24
Peak memory 201896 kb
Host smart-0d3906c4-0f22-47ab-9e73-b45b34dfd23c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853640125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_s
tress_all.2853640125
Directory /workspace/24.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/24.sysrst_ctrl_ultra_low_pwr.2471515104
Short name T502
Test name
Test status
Simulation time 3211270823 ps
CPU time 2.34 seconds
Started Jul 21 06:38:33 PM PDT 24
Finished Jul 21 06:38:36 PM PDT 24
Peak memory 201520 kb
Host smart-26739850-29b2-42a0-9f07-1a4b6fc2c43b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471515104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_
ctrl_ultra_low_pwr.2471515104
Directory /workspace/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_alert_test.1459792223
Short name T655
Test name
Test status
Simulation time 2012668789 ps
CPU time 5.77 seconds
Started Jul 21 06:38:38 PM PDT 24
Finished Jul 21 06:38:45 PM PDT 24
Peak memory 201568 kb
Host smart-95e9d03d-6a49-4c3a-8071-d718ee8cfd15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459792223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_te
st.1459792223
Directory /workspace/25.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_auto_blk_key_output.1202498981
Short name T701
Test name
Test status
Simulation time 3853604609 ps
CPU time 5.76 seconds
Started Jul 21 06:38:37 PM PDT 24
Finished Jul 21 06:38:44 PM PDT 24
Peak memory 201568 kb
Host smart-55c6a1b6-3367-428f-acd5-88ce4994cc24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202498981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.1
202498981
Directory /workspace/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect.1665557527
Short name T769
Test name
Test status
Simulation time 77327104081 ps
CPU time 17.46 seconds
Started Jul 21 06:38:33 PM PDT 24
Finished Jul 21 06:38:52 PM PDT 24
Peak memory 201764 kb
Host smart-3518fd55-3408-494a-a7c1-4a6d5eb4a885
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665557527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_combo_detect.1665557527
Directory /workspace/25.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1020898332
Short name T633
Test name
Test status
Simulation time 33108405005 ps
CPU time 19.27 seconds
Started Jul 21 06:38:34 PM PDT 24
Finished Jul 21 06:38:53 PM PDT 24
Peak memory 201964 kb
Host smart-d05a7d17-daac-4232-83f6-7f82268e41f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020898332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_w
ith_pre_cond.1020898332
Directory /workspace/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.4108142021
Short name T386
Test name
Test status
Simulation time 3728192630 ps
CPU time 5.14 seconds
Started Jul 21 06:38:34 PM PDT 24
Finished Jul 21 06:38:39 PM PDT 24
Peak memory 201584 kb
Host smart-8e78882a-47cb-4fe6-9eb8-dd623e6d1323
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108142021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_
ctrl_ec_pwr_on_rst.4108142021
Directory /workspace/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_edge_detect.3315717686
Short name T167
Test name
Test status
Simulation time 5609979588 ps
CPU time 3.12 seconds
Started Jul 21 06:38:41 PM PDT 24
Finished Jul 21 06:38:45 PM PDT 24
Peak memory 201544 kb
Host smart-6da804d5-091d-4eec-b21a-9fe2217a2f25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315717686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ct
rl_edge_detect.3315717686
Directory /workspace/25.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3967235463
Short name T754
Test name
Test status
Simulation time 2627740590 ps
CPU time 2.19 seconds
Started Jul 21 06:38:33 PM PDT 24
Finished Jul 21 06:38:36 PM PDT 24
Peak memory 201540 kb
Host smart-6f849065-fbc9-407c-89c9-81a62ef60c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967235463 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3967235463
Directory /workspace/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_in_out_inverted.1359815526
Short name T629
Test name
Test status
Simulation time 2468178929 ps
CPU time 5.79 seconds
Started Jul 21 06:38:35 PM PDT 24
Finished Jul 21 06:38:41 PM PDT 24
Peak memory 201548 kb
Host smart-bb7ad7e4-d181-4b74-b809-567d01dfd674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359815526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1359815526
Directory /workspace/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_access_test.552280780
Short name T726
Test name
Test status
Simulation time 2098694011 ps
CPU time 1.82 seconds
Started Jul 21 06:38:35 PM PDT 24
Finished Jul 21 06:38:37 PM PDT 24
Peak memory 201480 kb
Host smart-4a3c24cf-dc79-44d0-984a-133ba1cbdd62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552280780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.552280780
Directory /workspace/25.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_pin_override_test.1807482368
Short name T458
Test name
Test status
Simulation time 2511703447 ps
CPU time 7.11 seconds
Started Jul 21 06:38:33 PM PDT 24
Finished Jul 21 06:38:40 PM PDT 24
Peak memory 201560 kb
Host smart-9bfc324d-12e6-4206-99a1-6be44f7edb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807482368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.1807482368
Directory /workspace/25.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_smoke.4151399468
Short name T106
Test name
Test status
Simulation time 2110496998 ps
CPU time 6.19 seconds
Started Jul 21 06:38:45 PM PDT 24
Finished Jul 21 06:38:52 PM PDT 24
Peak memory 201464 kb
Host smart-252f9e5f-ddd5-4551-9bef-167f0dac9bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151399468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.4151399468
Directory /workspace/25.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_stress_all.3071778614
Short name T140
Test name
Test status
Simulation time 13423660205 ps
CPU time 27.93 seconds
Started Jul 21 06:38:36 PM PDT 24
Finished Jul 21 06:39:04 PM PDT 24
Peak memory 201532 kb
Host smart-32c856fb-7b00-4c2b-96e5-c39ea99a0547
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071778614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_s
tress_all.3071778614
Directory /workspace/25.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/25.sysrst_ctrl_ultra_low_pwr.374648491
Short name T63
Test name
Test status
Simulation time 7215166741 ps
CPU time 2.22 seconds
Started Jul 21 06:38:37 PM PDT 24
Finished Jul 21 06:38:40 PM PDT 24
Peak memory 201536 kb
Host smart-64ce7eeb-794a-4a50-bb1b-2fda7e3d8cc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374648491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_c
trl_ultra_low_pwr.374648491
Directory /workspace/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_alert_test.1508354421
Short name T783
Test name
Test status
Simulation time 2011910912 ps
CPU time 5.55 seconds
Started Jul 21 06:38:43 PM PDT 24
Finished Jul 21 06:38:49 PM PDT 24
Peak memory 201600 kb
Host smart-5ce5fa42-94d4-4f4c-9def-7bb2004acafe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508354421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_te
st.1508354421
Directory /workspace/26.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.847414530
Short name T389
Test name
Test status
Simulation time 3443540433 ps
CPU time 2.56 seconds
Started Jul 21 06:38:33 PM PDT 24
Finished Jul 21 06:38:36 PM PDT 24
Peak memory 201624 kb
Host smart-1a8b82f3-53d4-4afd-b883-5743dd7877ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847414530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.847414530
Directory /workspace/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect.2325804167
Short name T100
Test name
Test status
Simulation time 88241601508 ps
CPU time 56.52 seconds
Started Jul 21 06:38:39 PM PDT 24
Finished Jul 21 06:39:36 PM PDT 24
Peak memory 201716 kb
Host smart-9c8d9c12-6b9e-44c4-853e-18253771b393
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325804167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_c
trl_combo_detect.2325804167
Directory /workspace/26.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.3510975343
Short name T228
Test name
Test status
Simulation time 44192929934 ps
CPU time 113.26 seconds
Started Jul 21 06:38:36 PM PDT 24
Finished Jul 21 06:40:29 PM PDT 24
Peak memory 201784 kb
Host smart-51111a08-32de-477b-8c01-94bdf59eac05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510975343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_w
ith_pre_cond.3510975343
Directory /workspace/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.3708174134
Short name T491
Test name
Test status
Simulation time 5758506289 ps
CPU time 7.65 seconds
Started Jul 21 06:38:36 PM PDT 24
Finished Jul 21 06:38:45 PM PDT 24
Peak memory 201512 kb
Host smart-c6636a83-fd7e-4a60-8782-4103dc953214
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708174134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ec_pwr_on_rst.3708174134
Directory /workspace/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_edge_detect.2272238410
Short name T187
Test name
Test status
Simulation time 3576379698 ps
CPU time 2.49 seconds
Started Jul 21 06:38:33 PM PDT 24
Finished Jul 21 06:38:37 PM PDT 24
Peak memory 201556 kb
Host smart-799f8f74-b135-467b-9c61-505dfbad3e8f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272238410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ct
rl_edge_detect.2272238410
Directory /workspace/26.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.435644067
Short name T642
Test name
Test status
Simulation time 2614613218 ps
CPU time 6.72 seconds
Started Jul 21 06:38:44 PM PDT 24
Finished Jul 21 06:38:51 PM PDT 24
Peak memory 201440 kb
Host smart-91528214-514d-46b5-9cb5-e0d71787e5d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435644067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.435644067
Directory /workspace/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_in_out_inverted.2918248904
Short name T117
Test name
Test status
Simulation time 2471277294 ps
CPU time 4.05 seconds
Started Jul 21 06:38:41 PM PDT 24
Finished Jul 21 06:38:46 PM PDT 24
Peak memory 201508 kb
Host smart-d961f55b-ee13-4b81-afcf-5632b53c7323
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918248904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.2918248904
Directory /workspace/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3702336902
Short name T404
Test name
Test status
Simulation time 2178969971 ps
CPU time 6.14 seconds
Started Jul 21 06:38:34 PM PDT 24
Finished Jul 21 06:38:41 PM PDT 24
Peak memory 201540 kb
Host smart-428b4eb4-6200-44a0-a8ac-5658725a8082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702336902 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.3702336902
Directory /workspace/26.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.2638317128
Short name T57
Test name
Test status
Simulation time 2511161041 ps
CPU time 6.97 seconds
Started Jul 21 06:38:37 PM PDT 24
Finished Jul 21 06:38:45 PM PDT 24
Peak memory 201508 kb
Host smart-6c3d2495-7b22-47c7-9a29-1433cdc6bd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638317128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.2638317128
Directory /workspace/26.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_smoke.3647688868
Short name T665
Test name
Test status
Simulation time 2114190392 ps
CPU time 5.9 seconds
Started Jul 21 06:38:33 PM PDT 24
Finished Jul 21 06:38:40 PM PDT 24
Peak memory 201456 kb
Host smart-1243b970-d1f5-4f87-9eba-1b80118ba83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647688868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.3647688868
Directory /workspace/26.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all.4247945209
Short name T147
Test name
Test status
Simulation time 1233482696901 ps
CPU time 58.22 seconds
Started Jul 21 06:38:36 PM PDT 24
Finished Jul 21 06:39:34 PM PDT 24
Peak memory 201544 kb
Host smart-5ffecec2-4f12-4b4c-b58c-c0ed7835be37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247945209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_s
tress_all.4247945209
Directory /workspace/26.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2043690446
Short name T305
Test name
Test status
Simulation time 23363859204 ps
CPU time 58.15 seconds
Started Jul 21 06:38:41 PM PDT 24
Finished Jul 21 06:39:40 PM PDT 24
Peak memory 213152 kb
Host smart-e539178f-0baa-435a-81e6-9f1815d9c69e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043690446 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.2043690446
Directory /workspace/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.sysrst_ctrl_ultra_low_pwr.2989285961
Short name T454
Test name
Test status
Simulation time 2856162980 ps
CPU time 3.22 seconds
Started Jul 21 06:38:36 PM PDT 24
Finished Jul 21 06:38:40 PM PDT 24
Peak memory 201512 kb
Host smart-fc9dd787-0337-4a78-827c-be03898dc596
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989285961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_
ctrl_ultra_low_pwr.2989285961
Directory /workspace/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_alert_test.1650171886
Short name T460
Test name
Test status
Simulation time 2020846509 ps
CPU time 3.2 seconds
Started Jul 21 06:38:45 PM PDT 24
Finished Jul 21 06:38:49 PM PDT 24
Peak memory 201552 kb
Host smart-39802de4-df79-42ea-bfa6-cbc295827068
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650171886 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_te
st.1650171886
Directory /workspace/27.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_auto_blk_key_output.3927818904
Short name T288
Test name
Test status
Simulation time 3871702861 ps
CPU time 2.7 seconds
Started Jul 21 06:38:40 PM PDT 24
Finished Jul 21 06:38:43 PM PDT 24
Peak memory 201608 kb
Host smart-c56a3ca9-4bb0-42c1-9360-62e1ac73f2a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927818904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.3
927818904
Directory /workspace/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect.170649880
Short name T253
Test name
Test status
Simulation time 108874137202 ps
CPU time 76.48 seconds
Started Jul 21 06:38:45 PM PDT 24
Finished Jul 21 06:40:02 PM PDT 24
Peak memory 201748 kb
Host smart-cf6e2aa9-ce3b-4a58-a061-29a9f49d92a9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170649880 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_combo_detect.170649880
Directory /workspace/27.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2123149400
Short name T470
Test name
Test status
Simulation time 30727401418 ps
CPU time 19.16 seconds
Started Jul 21 06:38:35 PM PDT 24
Finished Jul 21 06:38:55 PM PDT 24
Peak memory 201884 kb
Host smart-416eee10-48bb-460e-8c91-c5069b10a992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123149400 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_w
ith_pre_cond.2123149400
Directory /workspace/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.1656777162
Short name T496
Test name
Test status
Simulation time 4169110719 ps
CPU time 11.57 seconds
Started Jul 21 06:38:39 PM PDT 24
Finished Jul 21 06:38:51 PM PDT 24
Peak memory 201440 kb
Host smart-5fdd533f-67c2-485b-b8a3-306793975415
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656777162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ec_pwr_on_rst.1656777162
Directory /workspace/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_edge_detect.1111294947
Short name T657
Test name
Test status
Simulation time 6160396221 ps
CPU time 16.12 seconds
Started Jul 21 06:38:35 PM PDT 24
Finished Jul 21 06:38:52 PM PDT 24
Peak memory 201556 kb
Host smart-8b392ea7-9d59-4d9d-a423-6f7b78edbd7a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111294947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ct
rl_edge_detect.1111294947
Directory /workspace/27.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.732118601
Short name T649
Test name
Test status
Simulation time 2630482965 ps
CPU time 2.36 seconds
Started Jul 21 06:38:37 PM PDT 24
Finished Jul 21 06:38:40 PM PDT 24
Peak memory 201556 kb
Host smart-167c3682-daa7-4089-a194-7938488c5677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732118601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.732118601
Directory /workspace/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_in_out_inverted.2312237560
Short name T472
Test name
Test status
Simulation time 2468711272 ps
CPU time 4.38 seconds
Started Jul 21 06:38:39 PM PDT 24
Finished Jul 21 06:38:45 PM PDT 24
Peak memory 201536 kb
Host smart-7e253ed9-dcf3-43c9-992a-ddeacb90cb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312237560 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.2312237560
Directory /workspace/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3407445508
Short name T310
Test name
Test status
Simulation time 2197500512 ps
CPU time 5.99 seconds
Started Jul 21 06:38:38 PM PDT 24
Finished Jul 21 06:38:45 PM PDT 24
Peak memory 201536 kb
Host smart-a618871d-5839-4953-94f6-a089c3d67955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407445508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.3407445508
Directory /workspace/27.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_pin_override_test.1603208600
Short name T733
Test name
Test status
Simulation time 2538734174 ps
CPU time 2.23 seconds
Started Jul 21 06:38:36 PM PDT 24
Finished Jul 21 06:38:39 PM PDT 24
Peak memory 200936 kb
Host smart-ed8d5474-27fa-4247-b0f2-35842e9034d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603208600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.1603208600
Directory /workspace/27.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_smoke.65973666
Short name T137
Test name
Test status
Simulation time 2131466052 ps
CPU time 2.06 seconds
Started Jul 21 06:38:38 PM PDT 24
Finished Jul 21 06:38:40 PM PDT 24
Peak memory 201472 kb
Host smart-ae0085c2-0628-423f-82bc-0389e8b440fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65973666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.65973666
Directory /workspace/27.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_stress_all.1709234135
Short name T511
Test name
Test status
Simulation time 12149203097 ps
CPU time 8.42 seconds
Started Jul 21 06:38:48 PM PDT 24
Finished Jul 21 06:38:57 PM PDT 24
Peak memory 201684 kb
Host smart-56a30bf1-0b69-4fba-b738-ccfa75199a34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709234135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_s
tress_all.1709234135
Directory /workspace/27.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/27.sysrst_ctrl_ultra_low_pwr.3765182583
Short name T735
Test name
Test status
Simulation time 3845425608 ps
CPU time 6.44 seconds
Started Jul 21 06:38:34 PM PDT 24
Finished Jul 21 06:38:41 PM PDT 24
Peak memory 201576 kb
Host smart-d8bee510-a334-42d5-92f4-0f13ff5f1822
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765182583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_
ctrl_ultra_low_pwr.3765182583
Directory /workspace/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_alert_test.3545252091
Short name T233
Test name
Test status
Simulation time 2032323313 ps
CPU time 1.96 seconds
Started Jul 21 06:38:42 PM PDT 24
Finished Jul 21 06:38:44 PM PDT 24
Peak memory 201540 kb
Host smart-9dd51aa8-1892-4ee9-a089-46e1f7fcb247
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545252091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_te
st.3545252091
Directory /workspace/28.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.4291951706
Short name T16
Test name
Test status
Simulation time 300933497328 ps
CPU time 366.96 seconds
Started Jul 21 06:38:40 PM PDT 24
Finished Jul 21 06:44:48 PM PDT 24
Peak memory 201608 kb
Host smart-0ab5db22-1c00-4a52-86bb-18759c6f75bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291951706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.4
291951706
Directory /workspace/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect.4153456084
Short name T362
Test name
Test status
Simulation time 103396503233 ps
CPU time 136.05 seconds
Started Jul 21 06:38:43 PM PDT 24
Finished Jul 21 06:40:59 PM PDT 24
Peak memory 201740 kb
Host smart-50d0f353-19f0-460b-ac8d-2e2447e29cce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153456084 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_c
trl_combo_detect.4153456084
Directory /workspace/28.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3212442819
Short name T45
Test name
Test status
Simulation time 89774219205 ps
CPU time 236.69 seconds
Started Jul 21 06:38:45 PM PDT 24
Finished Jul 21 06:42:43 PM PDT 24
Peak memory 201924 kb
Host smart-94188fce-b58b-4b89-835a-f2a48c12a7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212442819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_w
ith_pre_cond.3212442819
Directory /workspace/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3900786319
Short name T601
Test name
Test status
Simulation time 6019273662 ps
CPU time 7.91 seconds
Started Jul 21 06:38:46 PM PDT 24
Finished Jul 21 06:38:55 PM PDT 24
Peak memory 201540 kb
Host smart-d1f23f6c-df1d-4c06-aeb8-5a04c060228e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900786319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ec_pwr_on_rst.3900786319
Directory /workspace/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_edge_detect.3455099081
Short name T4
Test name
Test status
Simulation time 3316893613 ps
CPU time 4.96 seconds
Started Jul 21 06:38:40 PM PDT 24
Finished Jul 21 06:38:46 PM PDT 24
Peak memory 201512 kb
Host smart-d866ca61-e9f5-40ef-9c03-81746713f1e0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455099081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ct
rl_edge_detect.3455099081
Directory /workspace/28.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.4231607142
Short name T55
Test name
Test status
Simulation time 2609472917 ps
CPU time 7.97 seconds
Started Jul 21 06:38:40 PM PDT 24
Finished Jul 21 06:38:49 PM PDT 24
Peak memory 201516 kb
Host smart-26bbe84c-638a-418c-b0d9-c250734bbe0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231607142 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.4231607142
Directory /workspace/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_in_out_inverted.112552962
Short name T770
Test name
Test status
Simulation time 2497952640 ps
CPU time 1.69 seconds
Started Jul 21 06:38:45 PM PDT 24
Finished Jul 21 06:38:47 PM PDT 24
Peak memory 201476 kb
Host smart-993aaab0-8cbe-4871-a107-982575c2106f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112552962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.112552962
Directory /workspace/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_access_test.1716070900
Short name T574
Test name
Test status
Simulation time 2170931497 ps
CPU time 1.38 seconds
Started Jul 21 06:38:41 PM PDT 24
Finished Jul 21 06:38:43 PM PDT 24
Peak memory 201696 kb
Host smart-264dcf10-4b52-46b3-ba90-b4b5d490de94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716070900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.1716070900
Directory /workspace/28.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1514269255
Short name T54
Test name
Test status
Simulation time 2510094119 ps
CPU time 5.29 seconds
Started Jul 21 06:38:40 PM PDT 24
Finished Jul 21 06:38:46 PM PDT 24
Peak memory 201544 kb
Host smart-02a6ad42-e079-433d-b376-7b73df4d167b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514269255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1514269255
Directory /workspace/28.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_smoke.2417969546
Short name T176
Test name
Test status
Simulation time 2172611700 ps
CPU time 1.23 seconds
Started Jul 21 06:38:38 PM PDT 24
Finished Jul 21 06:38:40 PM PDT 24
Peak memory 201500 kb
Host smart-3459067c-c88f-4e0e-bd90-1e50a210b983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417969546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.2417969546
Directory /workspace/28.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all.3206090803
Short name T749
Test name
Test status
Simulation time 12425521140 ps
CPU time 30.21 seconds
Started Jul 21 06:38:45 PM PDT 24
Finished Jul 21 06:39:16 PM PDT 24
Peak memory 201572 kb
Host smart-16a58d63-6483-42f8-8565-8245df707867
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206090803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_s
tress_all.3206090803
Directory /workspace/28.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.780838175
Short name T295
Test name
Test status
Simulation time 51555719814 ps
CPU time 25.73 seconds
Started Jul 21 06:38:39 PM PDT 24
Finished Jul 21 06:39:06 PM PDT 24
Peak memory 218300 kb
Host smart-a56793e5-68b6-467a-acf0-851641fdbe2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780838175 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.780838175
Directory /workspace/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2887013778
Short name T302
Test name
Test status
Simulation time 131571326565 ps
CPU time 34.23 seconds
Started Jul 21 06:38:39 PM PDT 24
Finished Jul 21 06:39:15 PM PDT 24
Peak memory 201568 kb
Host smart-2b8a7043-6b7e-403c-80ef-bb504ed42b23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887013778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_
ctrl_ultra_low_pwr.2887013778
Directory /workspace/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_alert_test.4020655633
Short name T427
Test name
Test status
Simulation time 2036003899 ps
CPU time 2.11 seconds
Started Jul 21 06:38:46 PM PDT 24
Finished Jul 21 06:38:49 PM PDT 24
Peak memory 201564 kb
Host smart-589c4f2f-b92d-4570-b8c1-b1ec933dc358
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020655633 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_te
st.4020655633
Directory /workspace/29.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_auto_blk_key_output.293389992
Short name T508
Test name
Test status
Simulation time 3671966820 ps
CPU time 2.9 seconds
Started Jul 21 06:38:48 PM PDT 24
Finished Jul 21 06:38:52 PM PDT 24
Peak memory 201472 kb
Host smart-988cf0fa-e760-4512-8040-4061a1657d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293389992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.293389992
Directory /workspace/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect.1895071866
Short name T341
Test name
Test status
Simulation time 68316387639 ps
CPU time 182.54 seconds
Started Jul 21 06:38:39 PM PDT 24
Finished Jul 21 06:41:42 PM PDT 24
Peak memory 201740 kb
Host smart-3cff1866-f187-43ba-9e44-75504cedd40f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895071866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_c
trl_combo_detect.1895071866
Directory /workspace/29.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.2472711715
Short name T782
Test name
Test status
Simulation time 100826702450 ps
CPU time 65.21 seconds
Started Jul 21 06:38:39 PM PDT 24
Finished Jul 21 06:39:45 PM PDT 24
Peak memory 201880 kb
Host smart-ebc71d95-ad9f-4545-aa3e-050941d08301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472711715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_w
ith_pre_cond.2472711715
Directory /workspace/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.3722878478
Short name T651
Test name
Test status
Simulation time 3577335481 ps
CPU time 5.52 seconds
Started Jul 21 06:38:40 PM PDT 24
Finished Jul 21 06:38:46 PM PDT 24
Peak memory 201492 kb
Host smart-0467a7ba-4fe4-4c26-aba8-4bc54d62e308
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722878478 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ec_pwr_on_rst.3722878478
Directory /workspace/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_edge_detect.1065771611
Short name T9
Test name
Test status
Simulation time 2506392927 ps
CPU time 6.07 seconds
Started Jul 21 06:38:44 PM PDT 24
Finished Jul 21 06:38:51 PM PDT 24
Peak memory 201516 kb
Host smart-1eaa91d3-70a8-4857-acdd-9056d9c87de1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065771611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ct
rl_edge_detect.1065771611
Directory /workspace/29.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.4160179271
Short name T70
Test name
Test status
Simulation time 2616987071 ps
CPU time 5.55 seconds
Started Jul 21 06:38:38 PM PDT 24
Finished Jul 21 06:38:44 PM PDT 24
Peak memory 201556 kb
Host smart-833ec71f-d2ba-4d99-95d3-4499b035719f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160179271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.4160179271
Directory /workspace/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_in_out_inverted.2856681773
Short name T482
Test name
Test status
Simulation time 2448701544 ps
CPU time 6.53 seconds
Started Jul 21 06:38:44 PM PDT 24
Finished Jul 21 06:38:51 PM PDT 24
Peak memory 201532 kb
Host smart-c169b63a-aeb5-4a32-b9ea-f8c2450c689c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856681773 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2856681773
Directory /workspace/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_access_test.733393833
Short name T479
Test name
Test status
Simulation time 2203500340 ps
CPU time 2.83 seconds
Started Jul 21 06:38:47 PM PDT 24
Finished Jul 21 06:38:51 PM PDT 24
Peak memory 201532 kb
Host smart-20a9f86a-60a7-45b2-9c8f-bb037ec0ecb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733393833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.733393833
Directory /workspace/29.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_pin_override_test.1198337860
Short name T557
Test name
Test status
Simulation time 2513930306 ps
CPU time 4.6 seconds
Started Jul 21 06:38:45 PM PDT 24
Finished Jul 21 06:38:50 PM PDT 24
Peak memory 201476 kb
Host smart-78d5f12d-d576-496c-b115-205464f2cdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198337860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.1198337860
Directory /workspace/29.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_smoke.4280534141
Short name T56
Test name
Test status
Simulation time 2131902430 ps
CPU time 1.93 seconds
Started Jul 21 06:38:46 PM PDT 24
Finished Jul 21 06:38:49 PM PDT 24
Peak memory 201444 kb
Host smart-c5f26d18-7254-4d0c-8cfd-90330c6ab8ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280534141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.4280534141
Directory /workspace/29.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all.3144896851
Short name T562
Test name
Test status
Simulation time 14490610558 ps
CPU time 9.71 seconds
Started Jul 21 06:38:47 PM PDT 24
Finished Jul 21 06:38:58 PM PDT 24
Peak memory 201472 kb
Host smart-f4c583e3-3f0f-4382-b9d3-40376a974dca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144896851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_s
tress_all.3144896851
Directory /workspace/29.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2782363791
Short name T339
Test name
Test status
Simulation time 43096647503 ps
CPU time 107.69 seconds
Started Jul 21 06:38:48 PM PDT 24
Finished Jul 21 06:40:37 PM PDT 24
Peak memory 209988 kb
Host smart-768f4a5f-711e-46ad-b975-6e499a53360e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782363791 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.2782363791
Directory /workspace/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2770059950
Short name T377
Test name
Test status
Simulation time 1262900206878 ps
CPU time 164.55 seconds
Started Jul 21 06:38:45 PM PDT 24
Finished Jul 21 06:41:30 PM PDT 24
Peak memory 201448 kb
Host smart-b808cdc4-9430-45d4-97a5-bef596c9dbad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770059950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_
ctrl_ultra_low_pwr.2770059950
Directory /workspace/29.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_alert_test.2971693303
Short name T553
Test name
Test status
Simulation time 2035812053 ps
CPU time 1.89 seconds
Started Jul 21 06:37:50 PM PDT 24
Finished Jul 21 06:37:54 PM PDT 24
Peak memory 201500 kb
Host smart-f29b65a2-4149-4715-a8db-514623fbc975
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971693303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_tes
t.2971693303
Directory /workspace/3.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1404563518
Short name T608
Test name
Test status
Simulation time 3425404039 ps
CPU time 1.47 seconds
Started Jul 21 06:37:43 PM PDT 24
Finished Jul 21 06:37:45 PM PDT 24
Peak memory 201624 kb
Host smart-d8d57864-3a49-43e0-81a5-2effec76af79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404563518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.1404563518
Directory /workspace/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect.4279048172
Short name T445
Test name
Test status
Simulation time 146354629357 ps
CPU time 97.33 seconds
Started Jul 21 06:37:47 PM PDT 24
Finished Jul 21 06:39:26 PM PDT 24
Peak memory 201696 kb
Host smart-84998626-16d3-4508-8661-d84d459e3eb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279048172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ct
rl_combo_detect.4279048172
Directory /workspace/3.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1656470589
Short name T7
Test name
Test status
Simulation time 2402185511 ps
CPU time 6.72 seconds
Started Jul 21 06:37:46 PM PDT 24
Finished Jul 21 06:37:54 PM PDT 24
Peak memory 201532 kb
Host smart-3ffb8709-e927-4125-b479-0a71f1491abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656470589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.1656470589
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1086063964
Short name T685
Test name
Test status
Simulation time 2550244951 ps
CPU time 5.47 seconds
Started Jul 21 06:37:47 PM PDT 24
Finished Jul 21 06:37:54 PM PDT 24
Peak memory 201580 kb
Host smart-069e5ca1-3c5d-40cd-8a6f-7477fe6addfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086063964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.1086063964
Directory /workspace/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.89328334
Short name T768
Test name
Test status
Simulation time 27081322885 ps
CPU time 68.79 seconds
Started Jul 21 06:37:48 PM PDT 24
Finished Jul 21 06:38:58 PM PDT 24
Peak memory 201848 kb
Host smart-8b4de491-9f66-4e1b-89b7-e570acdd947b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89328334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_with
_pre_cond.89328334
Directory /workspace/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.3678896856
Short name T61
Test name
Test status
Simulation time 4521708067 ps
CPU time 1.87 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:37:55 PM PDT 24
Peak memory 201524 kb
Host smart-046dd016-54f0-4627-84f9-648841428a64
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678896856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ec_pwr_on_rst.3678896856
Directory /workspace/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_edge_detect.3232158262
Short name T168
Test name
Test status
Simulation time 3691645570 ps
CPU time 8.63 seconds
Started Jul 21 06:37:47 PM PDT 24
Finished Jul 21 06:37:57 PM PDT 24
Peak memory 201584 kb
Host smart-57599e89-0f63-41c5-a823-1a08e49fc837
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232158262 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctr
l_edge_detect.3232158262
Directory /workspace/3.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2220272604
Short name T645
Test name
Test status
Simulation time 2627363767 ps
CPU time 2.78 seconds
Started Jul 21 06:37:46 PM PDT 24
Finished Jul 21 06:37:49 PM PDT 24
Peak memory 201532 kb
Host smart-80846cd1-0646-4bfe-8693-9ca26e6efb85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220272604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.2220272604
Directory /workspace/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.375999533
Short name T225
Test name
Test status
Simulation time 2449441628 ps
CPU time 5.9 seconds
Started Jul 21 06:37:45 PM PDT 24
Finished Jul 21 06:37:51 PM PDT 24
Peak memory 201516 kb
Host smart-db10044f-29c7-4309-893a-a75b794b5756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375999533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.375999533
Directory /workspace/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_access_test.3051482166
Short name T591
Test name
Test status
Simulation time 2207249129 ps
CPU time 3.07 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:37:57 PM PDT 24
Peak memory 201512 kb
Host smart-585673a1-6170-437f-8f1c-7587a5ea5d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051482166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.3051482166
Directory /workspace/3.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.1157851209
Short name T379
Test name
Test status
Simulation time 2532908196 ps
CPU time 2.46 seconds
Started Jul 21 06:37:45 PM PDT 24
Finished Jul 21 06:37:48 PM PDT 24
Peak memory 201492 kb
Host smart-19c26dc6-7861-41a9-a706-2d767b3eb711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157851209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.1157851209
Directory /workspace/3.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_smoke.2143922339
Short name T771
Test name
Test status
Simulation time 2114320941 ps
CPU time 6.1 seconds
Started Jul 21 06:37:48 PM PDT 24
Finished Jul 21 06:37:55 PM PDT 24
Peak memory 201456 kb
Host smart-7626c0c2-0b85-436b-a346-d70daa899987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143922339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2143922339
Directory /workspace/3.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all.3961571826
Short name T710
Test name
Test status
Simulation time 7271089923 ps
CPU time 5.97 seconds
Started Jul 21 06:37:47 PM PDT 24
Finished Jul 21 06:37:54 PM PDT 24
Peak memory 201408 kb
Host smart-26ae24df-4ac6-489f-9208-b2f2b29b1cf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961571826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_st
ress_all.3961571826
Directory /workspace/3.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.2188726409
Short name T372
Test name
Test status
Simulation time 21488896454 ps
CPU time 28.55 seconds
Started Jul 21 06:37:47 PM PDT 24
Finished Jul 21 06:38:16 PM PDT 24
Peak memory 201920 kb
Host smart-a2eb759f-2236-48fa-b1b1-7cf1bff63aec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188726409 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.2188726409
Directory /workspace/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2487046909
Short name T227
Test name
Test status
Simulation time 4812594693 ps
CPU time 7.35 seconds
Started Jul 21 06:37:44 PM PDT 24
Finished Jul 21 06:37:52 PM PDT 24
Peak memory 201528 kb
Host smart-ed1ed5d5-ead4-4a60-b32b-127b21530272
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487046909 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_c
trl_ultra_low_pwr.2487046909
Directory /workspace/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_alert_test.2734849724
Short name T471
Test name
Test status
Simulation time 2014765027 ps
CPU time 5.91 seconds
Started Jul 21 06:38:48 PM PDT 24
Finished Jul 21 06:38:55 PM PDT 24
Peak memory 201536 kb
Host smart-ec31efac-72d9-42a0-bf26-ee872dfdc237
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734849724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_te
st.2734849724
Directory /workspace/30.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_auto_blk_key_output.2532024541
Short name T546
Test name
Test status
Simulation time 3451899363 ps
CPU time 9.1 seconds
Started Jul 21 06:38:39 PM PDT 24
Finished Jul 21 06:38:49 PM PDT 24
Peak memory 201680 kb
Host smart-1765fa2d-87f2-4007-9dc1-b503a90cc45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532024541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.2
532024541
Directory /workspace/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_combo_detect.3402919048
Short name T259
Test name
Test status
Simulation time 92824339333 ps
CPU time 60.88 seconds
Started Jul 21 06:38:49 PM PDT 24
Finished Jul 21 06:39:51 PM PDT 24
Peak memory 201832 kb
Host smart-77e3aba9-c015-4ab6-84e8-eb0706fac35b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402919048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_c
trl_combo_detect.3402919048
Directory /workspace/30.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2039800961
Short name T375
Test name
Test status
Simulation time 636904889714 ps
CPU time 423.61 seconds
Started Jul 21 06:38:39 PM PDT 24
Finished Jul 21 06:45:44 PM PDT 24
Peak memory 201516 kb
Host smart-975652a2-e8c7-4ff1-a5cb-a7c0d433d0cb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039800961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_
ctrl_ec_pwr_on_rst.2039800961
Directory /workspace/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_edge_detect.3497974771
Short name T86
Test name
Test status
Simulation time 3283137149 ps
CPU time 4.31 seconds
Started Jul 21 06:38:46 PM PDT 24
Finished Jul 21 06:38:52 PM PDT 24
Peak memory 201608 kb
Host smart-47247136-6ca8-445a-ac5b-438132321e10
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497974771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ct
rl_edge_detect.3497974771
Directory /workspace/30.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.463000164
Short name T478
Test name
Test status
Simulation time 2625987347 ps
CPU time 2.35 seconds
Started Jul 21 06:38:39 PM PDT 24
Finished Jul 21 06:38:43 PM PDT 24
Peak memory 201544 kb
Host smart-ec0f5640-bd43-4153-adce-76105810b406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463000164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.463000164
Directory /workspace/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_in_out_inverted.1622877765
Short name T67
Test name
Test status
Simulation time 2488993736 ps
CPU time 2.37 seconds
Started Jul 21 06:38:40 PM PDT 24
Finished Jul 21 06:38:43 PM PDT 24
Peak memory 201568 kb
Host smart-7048e462-d4d3-47f1-b82b-6d9892e1c05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622877765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.1622877765
Directory /workspace/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_access_test.3207996208
Short name T747
Test name
Test status
Simulation time 2228337812 ps
CPU time 5.95 seconds
Started Jul 21 06:38:39 PM PDT 24
Finished Jul 21 06:38:45 PM PDT 24
Peak memory 201568 kb
Host smart-a2c85d76-655b-42c9-9a00-e76b7908b121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207996208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.3207996208
Directory /workspace/30.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.1224968298
Short name T314
Test name
Test status
Simulation time 2513318067 ps
CPU time 6.77 seconds
Started Jul 21 06:38:48 PM PDT 24
Finished Jul 21 06:38:56 PM PDT 24
Peak memory 201392 kb
Host smart-0cd04c3e-f013-4262-b726-c042cc7b246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224968298 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.1224968298
Directory /workspace/30.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_smoke.2891626368
Short name T622
Test name
Test status
Simulation time 2123345261 ps
CPU time 1.93 seconds
Started Jul 21 06:38:46 PM PDT 24
Finished Jul 21 06:38:49 PM PDT 24
Peak memory 201520 kb
Host smart-48a5e8a8-f155-463c-b29a-233401e85b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891626368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.2891626368
Directory /workspace/30.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all.2066945384
Short name T289
Test name
Test status
Simulation time 218392603983 ps
CPU time 140.04 seconds
Started Jul 21 06:38:47 PM PDT 24
Finished Jul 21 06:41:08 PM PDT 24
Peak memory 201628 kb
Host smart-4aa4e66f-4677-48b6-8761-d3c37d3459d9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066945384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_s
tress_all.2066945384
Directory /workspace/30.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.2190879399
Short name T705
Test name
Test status
Simulation time 93558136370 ps
CPU time 59.28 seconds
Started Jul 21 06:38:46 PM PDT 24
Finished Jul 21 06:39:47 PM PDT 24
Peak memory 210204 kb
Host smart-a087d53e-b21d-42ea-9115-6bb41dcab3f5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190879399 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.2190879399
Directory /workspace/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_alert_test.1867710464
Short name T439
Test name
Test status
Simulation time 2012473063 ps
CPU time 5.83 seconds
Started Jul 21 06:38:51 PM PDT 24
Finished Jul 21 06:38:57 PM PDT 24
Peak memory 201552 kb
Host smart-581967ef-e024-404d-8b7d-01210d082567
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867710464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_te
st.1867710464
Directory /workspace/31.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3081764835
Short name T572
Test name
Test status
Simulation time 3509336484 ps
CPU time 9.81 seconds
Started Jul 21 06:38:47 PM PDT 24
Finished Jul 21 06:38:58 PM PDT 24
Peak memory 201652 kb
Host smart-afe0d0d5-18ab-4d8b-a80f-b942ebf4aebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081764835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3
081764835
Directory /workspace/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect.1261063578
Short name T737
Test name
Test status
Simulation time 59506887929 ps
CPU time 39.72 seconds
Started Jul 21 06:38:47 PM PDT 24
Finished Jul 21 06:39:28 PM PDT 24
Peak memory 201704 kb
Host smart-78cee5ec-853f-40c1-80e4-cc769372337f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261063578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_c
trl_combo_detect.1261063578
Directory /workspace/31.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.4109194961
Short name T596
Test name
Test status
Simulation time 29855097929 ps
CPU time 20.99 seconds
Started Jul 21 06:38:47 PM PDT 24
Finished Jul 21 06:39:09 PM PDT 24
Peak memory 201812 kb
Host smart-a4258aeb-6ed9-4c2c-b86e-a8ffa6763aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109194961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_w
ith_pre_cond.4109194961
Directory /workspace/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.3094517583
Short name T653
Test name
Test status
Simulation time 698383760081 ps
CPU time 1638.23 seconds
Started Jul 21 06:38:50 PM PDT 24
Finished Jul 21 07:06:09 PM PDT 24
Peak memory 201512 kb
Host smart-d42e39bb-9524-4ce8-b3fc-529ffd9481c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094517583 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ec_pwr_on_rst.3094517583
Directory /workspace/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.3863636673
Short name T790
Test name
Test status
Simulation time 2609354131 ps
CPU time 6.98 seconds
Started Jul 21 06:38:45 PM PDT 24
Finished Jul 21 06:38:53 PM PDT 24
Peak memory 201484 kb
Host smart-43419558-f10b-4a71-8522-6b76d0d72f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863636673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.3863636673
Directory /workspace/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1253780501
Short name T188
Test name
Test status
Simulation time 2485961676 ps
CPU time 1.22 seconds
Started Jul 21 06:38:49 PM PDT 24
Finished Jul 21 06:38:51 PM PDT 24
Peak memory 201564 kb
Host smart-b532d19a-80d0-4e1f-aa31-2336f8531a15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253780501 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.1253780501
Directory /workspace/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_access_test.2484722465
Short name T712
Test name
Test status
Simulation time 2256134638 ps
CPU time 1.3 seconds
Started Jul 21 06:38:47 PM PDT 24
Finished Jul 21 06:38:50 PM PDT 24
Peak memory 201564 kb
Host smart-bbd5cbbf-08a0-4e7b-bcce-c7fe88558c3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484722465 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.2484722465
Directory /workspace/31.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_pin_override_test.1936201743
Short name T767
Test name
Test status
Simulation time 2530998841 ps
CPU time 2.43 seconds
Started Jul 21 06:38:47 PM PDT 24
Finished Jul 21 06:38:50 PM PDT 24
Peak memory 201564 kb
Host smart-ff73eca9-d669-4e85-87a8-230723e85d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936201743 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.1936201743
Directory /workspace/31.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_smoke.3104739889
Short name T110
Test name
Test status
Simulation time 2128961506 ps
CPU time 1.71 seconds
Started Jul 21 06:38:45 PM PDT 24
Finished Jul 21 06:38:48 PM PDT 24
Peak memory 201408 kb
Host smart-d53d20c7-e39d-4a49-a68a-18248726d326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104739889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.3104739889
Directory /workspace/31.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all.3289126858
Short name T791
Test name
Test status
Simulation time 11124220000 ps
CPU time 8.12 seconds
Started Jul 21 06:38:49 PM PDT 24
Finished Jul 21 06:38:58 PM PDT 24
Peak memory 201544 kb
Host smart-7ed56c88-b192-4efc-acf0-a3da436a01f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289126858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_s
tress_all.3289126858
Directory /workspace/31.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.4055399425
Short name T41
Test name
Test status
Simulation time 50606650000 ps
CPU time 63.41 seconds
Started Jul 21 06:38:46 PM PDT 24
Finished Jul 21 06:39:50 PM PDT 24
Peak memory 210124 kb
Host smart-16c8dcfc-d627-45a1-a753-eaa4b30d8419
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055399425 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.4055399425
Directory /workspace/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.sysrst_ctrl_ultra_low_pwr.2052662007
Short name T681
Test name
Test status
Simulation time 5680958636 ps
CPU time 2.22 seconds
Started Jul 21 06:38:46 PM PDT 24
Finished Jul 21 06:38:49 PM PDT 24
Peak memory 201516 kb
Host smart-210eaceb-c06a-4287-b2a5-25329407c7dd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052662007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_
ctrl_ultra_low_pwr.2052662007
Directory /workspace/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_alert_test.638001710
Short name T462
Test name
Test status
Simulation time 2058338720 ps
CPU time 1.61 seconds
Started Jul 21 06:38:50 PM PDT 24
Finished Jul 21 06:38:52 PM PDT 24
Peak memory 201552 kb
Host smart-141c0ac5-5d04-4223-8b3f-d3489ec6687c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638001710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_tes
t.638001710
Directory /workspace/32.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_auto_blk_key_output.107758812
Short name T547
Test name
Test status
Simulation time 3527035119 ps
CPU time 10.08 seconds
Started Jul 21 06:38:49 PM PDT 24
Finished Jul 21 06:39:00 PM PDT 24
Peak memory 201604 kb
Host smart-25799494-0c83-41aa-a689-b50d868030d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107758812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.107758812
Directory /workspace/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3225112869
Short name T190
Test name
Test status
Simulation time 68938695482 ps
CPU time 177.57 seconds
Started Jul 21 06:38:47 PM PDT 24
Finished Jul 21 06:41:46 PM PDT 24
Peak memory 201836 kb
Host smart-67b01104-8037-46fc-85cf-43830e9123ce
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225112869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_c
trl_combo_detect.3225112869
Directory /workspace/32.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1010151267
Short name T203
Test name
Test status
Simulation time 42241967106 ps
CPU time 26.11 seconds
Started Jul 21 06:38:50 PM PDT 24
Finished Jul 21 06:39:16 PM PDT 24
Peak memory 201816 kb
Host smart-d306e45b-aa8d-492c-bdf3-85f4a0acd026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010151267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_w
ith_pre_cond.1010151267
Directory /workspace/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2991664242
Short name T421
Test name
Test status
Simulation time 4757349334 ps
CPU time 6.26 seconds
Started Jul 21 06:38:46 PM PDT 24
Finished Jul 21 06:38:54 PM PDT 24
Peak memory 201556 kb
Host smart-83e21441-637f-4c5c-bf20-ad1e2f218060
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991664242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ec_pwr_on_rst.2991664242
Directory /workspace/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_edge_detect.1042975036
Short name T193
Test name
Test status
Simulation time 3759519103 ps
CPU time 1.14 seconds
Started Jul 21 06:38:48 PM PDT 24
Finished Jul 21 06:38:51 PM PDT 24
Peak memory 201412 kb
Host smart-222442f7-3de6-4d34-95e0-33161a8c9226
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042975036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ct
rl_edge_detect.1042975036
Directory /workspace/32.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.2381088946
Short name T709
Test name
Test status
Simulation time 2614039325 ps
CPU time 7.02 seconds
Started Jul 21 06:38:51 PM PDT 24
Finished Jul 21 06:38:59 PM PDT 24
Peak memory 201572 kb
Host smart-7e35d068-027f-43cc-b534-de36c91a9d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381088946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.2381088946
Directory /workspace/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_in_out_inverted.953225167
Short name T456
Test name
Test status
Simulation time 2458850860 ps
CPU time 3.6 seconds
Started Jul 21 06:38:46 PM PDT 24
Finished Jul 21 06:38:50 PM PDT 24
Peak memory 201524 kb
Host smart-3cdd36aa-835c-4bce-a6af-a4e75d75213c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953225167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.953225167
Directory /workspace/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_access_test.734346157
Short name T587
Test name
Test status
Simulation time 2290474797 ps
CPU time 0.99 seconds
Started Jul 21 06:38:47 PM PDT 24
Finished Jul 21 06:38:50 PM PDT 24
Peak memory 201532 kb
Host smart-17c31e20-7466-4956-a755-d4fd5e106e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734346157 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.734346157
Directory /workspace/32.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.1076441401
Short name T447
Test name
Test status
Simulation time 2510355327 ps
CPU time 7.22 seconds
Started Jul 21 06:38:47 PM PDT 24
Finished Jul 21 06:38:56 PM PDT 24
Peak memory 201436 kb
Host smart-39656b40-2747-4b66-9519-1752f38611b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076441401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.1076441401
Directory /workspace/32.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_smoke.2643400549
Short name T611
Test name
Test status
Simulation time 2111764798 ps
CPU time 5.95 seconds
Started Jul 21 06:38:45 PM PDT 24
Finished Jul 21 06:38:52 PM PDT 24
Peak memory 201516 kb
Host smart-0d883510-a869-4ae7-916a-502a7968cb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643400549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.2643400549
Directory /workspace/32.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all.2658496592
Short name T212
Test name
Test status
Simulation time 8370899577 ps
CPU time 6.01 seconds
Started Jul 21 06:38:52 PM PDT 24
Finished Jul 21 06:38:59 PM PDT 24
Peak memory 201540 kb
Host smart-b6477031-32e3-4b74-b6e7-fdbf5997b977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658496592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_s
tress_all.2658496592
Directory /workspace/32.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2033822152
Short name T294
Test name
Test status
Simulation time 40145799245 ps
CPU time 103.54 seconds
Started Jul 21 06:38:52 PM PDT 24
Finished Jul 21 06:40:36 PM PDT 24
Peak memory 210100 kb
Host smart-bac742b0-d01b-4fe6-86cd-0dfb3d300b9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033822152 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.2033822152
Directory /workspace/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2407782309
Short name T474
Test name
Test status
Simulation time 10460554281 ps
CPU time 2.66 seconds
Started Jul 21 06:38:48 PM PDT 24
Finished Jul 21 06:38:52 PM PDT 24
Peak memory 201608 kb
Host smart-b64c9d2c-4328-4ecd-9cf8-7474ac1eb577
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407782309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_
ctrl_ultra_low_pwr.2407782309
Directory /workspace/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_alert_test.4052074446
Short name T678
Test name
Test status
Simulation time 2017175454 ps
CPU time 3.07 seconds
Started Jul 21 06:38:54 PM PDT 24
Finished Jul 21 06:38:58 PM PDT 24
Peak memory 201488 kb
Host smart-dbf92119-3f3c-4263-aceb-a97ffae92c68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052074446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_te
st.4052074446
Directory /workspace/33.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_auto_blk_key_output.1377448699
Short name T603
Test name
Test status
Simulation time 3474193810 ps
CPU time 1.28 seconds
Started Jul 21 06:38:54 PM PDT 24
Finished Jul 21 06:38:56 PM PDT 24
Peak memory 201572 kb
Host smart-41bcef6d-45a3-4848-8c96-4f893614dcba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377448699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.1
377448699
Directory /workspace/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_combo_detect.537448595
Short name T247
Test name
Test status
Simulation time 136311730621 ps
CPU time 338.1 seconds
Started Jul 21 06:38:52 PM PDT 24
Finished Jul 21 06:44:31 PM PDT 24
Peak memory 201764 kb
Host smart-d536433e-f2aa-4a78-92be-1eeda9d1a6f3
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537448595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_combo_detect.537448595
Directory /workspace/33.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.693722666
Short name T519
Test name
Test status
Simulation time 3793286611 ps
CPU time 2.96 seconds
Started Jul 21 06:38:52 PM PDT 24
Finished Jul 21 06:38:56 PM PDT 24
Peak memory 201532 kb
Host smart-1fa475cb-bf77-42c3-bd2f-a215470970fd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693722666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_c
trl_ec_pwr_on_rst.693722666
Directory /workspace/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_edge_detect.3318299832
Short name T753
Test name
Test status
Simulation time 3474999900 ps
CPU time 2.28 seconds
Started Jul 21 06:38:53 PM PDT 24
Finished Jul 21 06:38:56 PM PDT 24
Peak memory 201560 kb
Host smart-94ff3215-8fc5-4974-9a87-98c8ac2ee421
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318299832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ct
rl_edge_detect.3318299832
Directory /workspace/33.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.830105903
Short name T535
Test name
Test status
Simulation time 2615026436 ps
CPU time 4.06 seconds
Started Jul 21 06:38:53 PM PDT 24
Finished Jul 21 06:38:58 PM PDT 24
Peak memory 201436 kb
Host smart-3e57e86a-1928-4747-99a5-431d224fb672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830105903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.830105903
Directory /workspace/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1507093194
Short name T133
Test name
Test status
Simulation time 2456946357 ps
CPU time 7.02 seconds
Started Jul 21 06:38:56 PM PDT 24
Finished Jul 21 06:39:04 PM PDT 24
Peak memory 201564 kb
Host smart-54340f2c-fa79-40fe-919d-26ca08f0e43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507093194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.1507093194
Directory /workspace/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_access_test.3402310444
Short name T632
Test name
Test status
Simulation time 2096099561 ps
CPU time 6.25 seconds
Started Jul 21 06:38:54 PM PDT 24
Finished Jul 21 06:39:01 PM PDT 24
Peak memory 201464 kb
Host smart-739a655e-536f-45ad-b233-6b56c8f46cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402310444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3402310444
Directory /workspace/33.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.467625060
Short name T202
Test name
Test status
Simulation time 2517484371 ps
CPU time 3.8 seconds
Started Jul 21 06:38:54 PM PDT 24
Finished Jul 21 06:38:59 PM PDT 24
Peak memory 201580 kb
Host smart-ccc7f27b-eb4d-44f7-9c3f-dc70d01960ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467625060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.467625060
Directory /workspace/33.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_smoke.4030220003
Short name T668
Test name
Test status
Simulation time 2125260032 ps
CPU time 2.03 seconds
Started Jul 21 06:38:53 PM PDT 24
Finished Jul 21 06:38:56 PM PDT 24
Peak memory 201460 kb
Host smart-5a7ae609-8b7d-4a74-af9a-e955dfbf3a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030220003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.4030220003
Directory /workspace/33.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.863313010
Short name T178
Test name
Test status
Simulation time 75523078861 ps
CPU time 77.08 seconds
Started Jul 21 06:38:52 PM PDT 24
Finished Jul 21 06:40:09 PM PDT 24
Peak memory 218412 kb
Host smart-d01abb4f-02f0-4c86-aef6-456e9178febb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863313010 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.863313010
Directory /workspace/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.sysrst_ctrl_ultra_low_pwr.3066689367
Short name T116
Test name
Test status
Simulation time 1060225216222 ps
CPU time 262.95 seconds
Started Jul 21 06:38:54 PM PDT 24
Finished Jul 21 06:43:18 PM PDT 24
Peak memory 201512 kb
Host smart-d7d8a2b0-90e8-4826-aba0-24febdaa6e47
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066689367 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_
ctrl_ultra_low_pwr.3066689367
Directory /workspace/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_alert_test.938101651
Short name T604
Test name
Test status
Simulation time 2010124602 ps
CPU time 5.81 seconds
Started Jul 21 06:38:52 PM PDT 24
Finished Jul 21 06:38:58 PM PDT 24
Peak memory 201552 kb
Host smart-c18dc8ad-37a7-4869-9dda-dc155eda0634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938101651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_tes
t.938101651
Directory /workspace/34.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_auto_blk_key_output.4188559652
Short name T590
Test name
Test status
Simulation time 181283963475 ps
CPU time 479.54 seconds
Started Jul 21 06:38:53 PM PDT 24
Finished Jul 21 06:46:53 PM PDT 24
Peak memory 201628 kb
Host smart-1c486890-f766-499c-a654-12742a483441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188559652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.4
188559652
Directory /workspace/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect.3685681758
Short name T243
Test name
Test status
Simulation time 39808818352 ps
CPU time 30.64 seconds
Started Jul 21 06:38:55 PM PDT 24
Finished Jul 21 06:39:26 PM PDT 24
Peak memory 201648 kb
Host smart-8b3e83ad-afda-4ea9-9791-b652153847c1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685681758 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_combo_detect.3685681758
Directory /workspace/34.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3007319331
Short name T739
Test name
Test status
Simulation time 43401148224 ps
CPU time 20.54 seconds
Started Jul 21 06:38:56 PM PDT 24
Finished Jul 21 06:39:17 PM PDT 24
Peak memory 201792 kb
Host smart-67af034c-f9a9-46a0-a63a-56a55ba6155d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007319331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_w
ith_pre_cond.3007319331
Directory /workspace/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.163659282
Short name T391
Test name
Test status
Simulation time 4045719023 ps
CPU time 11.16 seconds
Started Jul 21 06:38:56 PM PDT 24
Finished Jul 21 06:39:08 PM PDT 24
Peak memory 201528 kb
Host smart-1f14e23d-8559-4ed1-b9db-5880fb1e2706
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163659282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_ec_pwr_on_rst.163659282
Directory /workspace/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1752571123
Short name T151
Test name
Test status
Simulation time 4635743179 ps
CPU time 1.99 seconds
Started Jul 21 06:38:54 PM PDT 24
Finished Jul 21 06:38:56 PM PDT 24
Peak memory 201556 kb
Host smart-23725b40-96a0-49a8-aa78-d0ed5b5d4d96
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752571123 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ct
rl_edge_detect.1752571123
Directory /workspace/34.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.409801519
Short name T415
Test name
Test status
Simulation time 2613202341 ps
CPU time 7.47 seconds
Started Jul 21 06:38:56 PM PDT 24
Finished Jul 21 06:39:04 PM PDT 24
Peak memory 201436 kb
Host smart-e8530165-665d-472f-a82f-3ee89cce9a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409801519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.409801519
Directory /workspace/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_in_out_inverted.2188612216
Short name T451
Test name
Test status
Simulation time 2475368169 ps
CPU time 2.21 seconds
Started Jul 21 06:39:00 PM PDT 24
Finished Jul 21 06:39:03 PM PDT 24
Peak memory 201548 kb
Host smart-0f41accf-6a0e-491c-8752-d3352f610a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188612216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.2188612216
Directory /workspace/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_access_test.3039839874
Short name T614
Test name
Test status
Simulation time 2185339340 ps
CPU time 3.28 seconds
Started Jul 21 06:38:54 PM PDT 24
Finished Jul 21 06:38:59 PM PDT 24
Peak memory 201464 kb
Host smart-86625f72-d5d1-458d-8d1d-772559eeec7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039839874 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.3039839874
Directory /workspace/34.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_pin_override_test.3444974748
Short name T234
Test name
Test status
Simulation time 2531471951 ps
CPU time 2.44 seconds
Started Jul 21 06:39:01 PM PDT 24
Finished Jul 21 06:39:04 PM PDT 24
Peak memory 201548 kb
Host smart-ea8f6490-9728-4c61-af4a-5fe88cf0cdf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444974748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.3444974748
Directory /workspace/34.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_smoke.3300904576
Short name T526
Test name
Test status
Simulation time 2120140803 ps
CPU time 1.91 seconds
Started Jul 21 06:38:53 PM PDT 24
Finished Jul 21 06:38:56 PM PDT 24
Peak memory 201436 kb
Host smart-c0e9751f-7381-44f5-bf7d-c1ec17313ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300904576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.3300904576
Directory /workspace/34.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_stress_all.3097504660
Short name T461
Test name
Test status
Simulation time 7278886628 ps
CPU time 5.94 seconds
Started Jul 21 06:38:56 PM PDT 24
Finished Jul 21 06:39:02 PM PDT 24
Peak memory 201520 kb
Host smart-9645f5ed-162b-431a-b41e-1f44cc53c7f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097504660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_s
tress_all.3097504660
Directory /workspace/34.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/34.sysrst_ctrl_ultra_low_pwr.159584310
Short name T760
Test name
Test status
Simulation time 9705022407 ps
CPU time 3.27 seconds
Started Jul 21 06:38:54 PM PDT 24
Finished Jul 21 06:38:58 PM PDT 24
Peak memory 201548 kb
Host smart-c5efdd6a-0c2f-4770-b359-a00094137090
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159584310 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_c
trl_ultra_low_pwr.159584310
Directory /workspace/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_alert_test.2960317373
Short name T226
Test name
Test status
Simulation time 2030459340 ps
CPU time 1.96 seconds
Started Jul 21 06:39:05 PM PDT 24
Finished Jul 21 06:39:07 PM PDT 24
Peak memory 201572 kb
Host smart-72a31b10-775d-4e4b-98cd-ff1b58bf6c10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960317373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_te
st.2960317373
Directory /workspace/35.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1356844355
Short name T49
Test name
Test status
Simulation time 3325628495 ps
CPU time 2.68 seconds
Started Jul 21 06:38:56 PM PDT 24
Finished Jul 21 06:38:59 PM PDT 24
Peak memory 201604 kb
Host smart-f1b722c5-7d57-41b8-ae84-c236a89597e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356844355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.1
356844355
Directory /workspace/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect.233794264
Short name T242
Test name
Test status
Simulation time 73814553473 ps
CPU time 49.55 seconds
Started Jul 21 06:38:59 PM PDT 24
Finished Jul 21 06:39:49 PM PDT 24
Peak memory 201840 kb
Host smart-7d144850-1b0c-471a-8c4f-327b6fb16d55
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233794264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ct
rl_combo_detect.233794264
Directory /workspace/35.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2408646587
Short name T239
Test name
Test status
Simulation time 78321558488 ps
CPU time 48.85 seconds
Started Jul 21 06:38:55 PM PDT 24
Finished Jul 21 06:39:44 PM PDT 24
Peak memory 201872 kb
Host smart-70c36423-3705-42cc-861b-5b7b20aff9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408646587 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_w
ith_pre_cond.2408646587
Directory /workspace/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3853550532
Short name T627
Test name
Test status
Simulation time 2529928632 ps
CPU time 1.44 seconds
Started Jul 21 06:38:53 PM PDT 24
Finished Jul 21 06:38:55 PM PDT 24
Peak memory 201528 kb
Host smart-c774f0e1-0d67-4de3-afad-1464c2d8f529
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853550532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_
ctrl_ec_pwr_on_rst.3853550532
Directory /workspace/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_edge_detect.202933951
Short name T538
Test name
Test status
Simulation time 3166393259 ps
CPU time 2.14 seconds
Started Jul 21 06:38:55 PM PDT 24
Finished Jul 21 06:38:57 PM PDT 24
Peak memory 201544 kb
Host smart-cbdc19d7-1684-4b9c-a5cc-f7e8eee9c61e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202933951 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctr
l_edge_detect.202933951
Directory /workspace/35.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.1882062273
Short name T569
Test name
Test status
Simulation time 2619338498 ps
CPU time 3.82 seconds
Started Jul 21 06:38:53 PM PDT 24
Finished Jul 21 06:38:58 PM PDT 24
Peak memory 201544 kb
Host smart-0fce6c06-5e24-4d1a-8ee9-c5b7a8cd48ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882062273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.1882062273
Directory /workspace/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_in_out_inverted.1429202363
Short name T528
Test name
Test status
Simulation time 2467345981 ps
CPU time 2.36 seconds
Started Jul 21 06:38:54 PM PDT 24
Finished Jul 21 06:38:58 PM PDT 24
Peak memory 201500 kb
Host smart-1a1be537-bba5-430b-9796-373663e503f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1429202363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.1429202363
Directory /workspace/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_access_test.900254418
Short name T679
Test name
Test status
Simulation time 2174730314 ps
CPU time 6.22 seconds
Started Jul 21 06:38:58 PM PDT 24
Finished Jul 21 06:39:05 PM PDT 24
Peak memory 201524 kb
Host smart-fba5d76e-2d1b-4746-bfec-6bf2fbcf9696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900254418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.900254418
Directory /workspace/35.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_pin_override_test.3982359507
Short name T638
Test name
Test status
Simulation time 2508013367 ps
CPU time 7.53 seconds
Started Jul 21 06:38:56 PM PDT 24
Finished Jul 21 06:39:04 PM PDT 24
Peak memory 201476 kb
Host smart-70168b8f-fe92-4680-98f2-10043195dcc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982359507 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.3982359507
Directory /workspace/35.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_smoke.399647030
Short name T409
Test name
Test status
Simulation time 2161781864 ps
CPU time 1.27 seconds
Started Jul 21 06:38:52 PM PDT 24
Finished Jul 21 06:38:54 PM PDT 24
Peak memory 201544 kb
Host smart-5e590295-ca73-4e2d-87a8-c70322ebca6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399647030 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.399647030
Directory /workspace/35.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all.1370243549
Short name T384
Test name
Test status
Simulation time 9919710130 ps
CPU time 7.57 seconds
Started Jul 21 06:39:02 PM PDT 24
Finished Jul 21 06:39:11 PM PDT 24
Peak memory 201552 kb
Host smart-93085720-d956-4ef2-90bc-8af3183522d7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370243549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_s
tress_all.1370243549
Directory /workspace/35.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1984180957
Short name T162
Test name
Test status
Simulation time 86007573245 ps
CPU time 46.27 seconds
Started Jul 21 06:38:59 PM PDT 24
Finished Jul 21 06:39:46 PM PDT 24
Peak memory 210240 kb
Host smart-abbaab52-d112-4f82-8148-2e15f81e1312
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984180957 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1984180957
Directory /workspace/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.sysrst_ctrl_ultra_low_pwr.739746659
Short name T85
Test name
Test status
Simulation time 918777839487 ps
CPU time 11.69 seconds
Started Jul 21 06:38:53 PM PDT 24
Finished Jul 21 06:39:06 PM PDT 24
Peak memory 201544 kb
Host smart-18ab8303-a4f8-443e-88fd-8f644a8d4735
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739746659 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_c
trl_ultra_low_pwr.739746659
Directory /workspace/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_alert_test.290105724
Short name T774
Test name
Test status
Simulation time 2013690993 ps
CPU time 5.33 seconds
Started Jul 21 06:38:58 PM PDT 24
Finished Jul 21 06:39:04 PM PDT 24
Peak memory 201552 kb
Host smart-caaf2fa6-c000-47b1-ab73-1d2a0c4640bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290105724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_tes
t.290105724
Directory /workspace/36.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1125298220
Short name T497
Test name
Test status
Simulation time 3019864220 ps
CPU time 8.21 seconds
Started Jul 21 06:38:59 PM PDT 24
Finished Jul 21 06:39:08 PM PDT 24
Peak memory 201608 kb
Host smart-27dff6c2-001a-4872-ad65-2ab4010b5399
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125298220 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.1
125298220
Directory /workspace/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect.4042171175
Short name T336
Test name
Test status
Simulation time 135465808410 ps
CPU time 41.89 seconds
Started Jul 21 06:38:57 PM PDT 24
Finished Jul 21 06:39:40 PM PDT 24
Peak memory 201796 kb
Host smart-1e9b7713-3e7a-4ec9-91e4-52067c61a5cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042171175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_c
trl_combo_detect.4042171175
Directory /workspace/36.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.245756953
Short name T598
Test name
Test status
Simulation time 94864218903 ps
CPU time 123.78 seconds
Started Jul 21 06:38:58 PM PDT 24
Finished Jul 21 06:41:03 PM PDT 24
Peak memory 201832 kb
Host smart-f05ad46a-91f0-4ebe-9602-bad574023682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245756953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_wi
th_pre_cond.245756953
Directory /workspace/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3748880561
Short name T394
Test name
Test status
Simulation time 5170583123 ps
CPU time 3.81 seconds
Started Jul 21 06:38:58 PM PDT 24
Finished Jul 21 06:39:03 PM PDT 24
Peak memory 201480 kb
Host smart-b2cadb8b-9035-4fd5-b28d-5b9d3b5cb16c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748880561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_
ctrl_ec_pwr_on_rst.3748880561
Directory /workspace/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_edge_detect.1868558673
Short name T195
Test name
Test status
Simulation time 280136297231 ps
CPU time 150.33 seconds
Started Jul 21 06:39:00 PM PDT 24
Finished Jul 21 06:41:31 PM PDT 24
Peak memory 201504 kb
Host smart-9ba4266a-0115-469a-b968-774d430d4505
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868558673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ct
rl_edge_detect.1868558673
Directory /workspace/36.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2942149813
Short name T584
Test name
Test status
Simulation time 2623972508 ps
CPU time 2.52 seconds
Started Jul 21 06:39:02 PM PDT 24
Finished Jul 21 06:39:05 PM PDT 24
Peak memory 201580 kb
Host smart-49e8dc69-ea4d-44ae-8171-2c0fd06aec44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942149813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.2942149813
Directory /workspace/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.4229006755
Short name T189
Test name
Test status
Simulation time 2459946980 ps
CPU time 5.46 seconds
Started Jul 21 06:38:58 PM PDT 24
Finished Jul 21 06:39:05 PM PDT 24
Peak memory 201408 kb
Host smart-c3debb1f-7fa8-43ba-8436-d85208908800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229006755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.4229006755
Directory /workspace/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_access_test.1098523245
Short name T164
Test name
Test status
Simulation time 2123187488 ps
CPU time 1.96 seconds
Started Jul 21 06:38:58 PM PDT 24
Finished Jul 21 06:39:01 PM PDT 24
Peak memory 201504 kb
Host smart-4a490341-13f4-45d6-9ab1-e53e4f22c2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098523245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.1098523245
Directory /workspace/36.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_pin_override_test.707902039
Short name T592
Test name
Test status
Simulation time 2516900634 ps
CPU time 4.02 seconds
Started Jul 21 06:38:58 PM PDT 24
Finished Jul 21 06:39:03 PM PDT 24
Peak memory 201516 kb
Host smart-ec78fcf2-3f5c-4998-8b08-3f02f7629b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707902039 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.707902039
Directory /workspace/36.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_smoke.2723253305
Short name T758
Test name
Test status
Simulation time 2115826299 ps
CPU time 3.11 seconds
Started Jul 21 06:38:59 PM PDT 24
Finished Jul 21 06:39:03 PM PDT 24
Peak memory 201488 kb
Host smart-bda8b07a-151c-40e0-be9a-c8d1e34f5159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723253305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.2723253305
Directory /workspace/36.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all.1101943812
Short name T149
Test name
Test status
Simulation time 16199490968 ps
CPU time 12.01 seconds
Started Jul 21 06:39:00 PM PDT 24
Finished Jul 21 06:39:13 PM PDT 24
Peak memory 201532 kb
Host smart-19580c53-5e70-4364-9fd7-63cc2b4706e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101943812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_s
tress_all.1101943812
Directory /workspace/36.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2020240291
Short name T38
Test name
Test status
Simulation time 18542469490 ps
CPU time 5.53 seconds
Started Jul 21 06:38:59 PM PDT 24
Finished Jul 21 06:39:05 PM PDT 24
Peak memory 210996 kb
Host smart-fc99445f-9c6b-4800-b24f-d2f30ccef15c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020240291 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.2020240291
Directory /workspace/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_alert_test.4152537774
Short name T403
Test name
Test status
Simulation time 2020469693 ps
CPU time 3.17 seconds
Started Jul 21 06:39:00 PM PDT 24
Finished Jul 21 06:39:04 PM PDT 24
Peak memory 201552 kb
Host smart-02dd6d80-301a-4cf5-b778-911a73d2b998
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152537774 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_te
st.4152537774
Directory /workspace/37.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2578372781
Short name T516
Test name
Test status
Simulation time 3858264984 ps
CPU time 10.91 seconds
Started Jul 21 06:38:58 PM PDT 24
Finished Jul 21 06:39:10 PM PDT 24
Peak memory 201636 kb
Host smart-5221ada5-cf10-4cf0-92b5-ddcbbe1be05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578372781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.2
578372781
Directory /workspace/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_combo_detect.2286476760
Short name T777
Test name
Test status
Simulation time 97015606642 ps
CPU time 248.17 seconds
Started Jul 21 06:38:59 PM PDT 24
Finished Jul 21 06:43:08 PM PDT 24
Peak memory 201756 kb
Host smart-11fd036c-f983-485c-8e22-da5cd8e7b2c7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286476760 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_c
trl_combo_detect.2286476760
Directory /workspace/37.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2500998835
Short name T580
Test name
Test status
Simulation time 4764503698 ps
CPU time 5.26 seconds
Started Jul 21 06:39:00 PM PDT 24
Finished Jul 21 06:39:05 PM PDT 24
Peak memory 201540 kb
Host smart-96872873-0784-4c8d-bde5-c83e98686962
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500998835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ec_pwr_on_rst.2500998835
Directory /workspace/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_edge_detect.1709565706
Short name T40
Test name
Test status
Simulation time 2445794001 ps
CPU time 4.77 seconds
Started Jul 21 06:39:02 PM PDT 24
Finished Jul 21 06:39:07 PM PDT 24
Peak memory 201544 kb
Host smart-3db688a0-8e61-46fd-b25f-b465c6ff18d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709565706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ct
rl_edge_detect.1709565706
Directory /workspace/37.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1186469917
Short name T719
Test name
Test status
Simulation time 2609993280 ps
CPU time 7.31 seconds
Started Jul 21 06:38:57 PM PDT 24
Finished Jul 21 06:39:05 PM PDT 24
Peak memory 201540 kb
Host smart-88a10080-64d7-489f-b90e-3d7b227b0520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186469917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.1186469917
Directory /workspace/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_in_out_inverted.286605588
Short name T539
Test name
Test status
Simulation time 2483341828 ps
CPU time 1.94 seconds
Started Jul 21 06:39:00 PM PDT 24
Finished Jul 21 06:39:03 PM PDT 24
Peak memory 201580 kb
Host smart-d7f675c5-c87d-4475-8f54-55f6adcf5738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286605588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.286605588
Directory /workspace/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.299929742
Short name T313
Test name
Test status
Simulation time 2084020389 ps
CPU time 2.01 seconds
Started Jul 21 06:38:58 PM PDT 24
Finished Jul 21 06:39:01 PM PDT 24
Peak memory 201468 kb
Host smart-23686101-19ff-4171-95e0-8d993ccabdab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299929742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.299929742
Directory /workspace/37.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_pin_override_test.3831219069
Short name T230
Test name
Test status
Simulation time 2581269328 ps
CPU time 1.39 seconds
Started Jul 21 06:38:59 PM PDT 24
Finished Jul 21 06:39:01 PM PDT 24
Peak memory 201556 kb
Host smart-c3835b9a-dc4a-42b3-96c3-b6424a5b25b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831219069 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.3831219069
Directory /workspace/37.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_smoke.1962899004
Short name T615
Test name
Test status
Simulation time 2111864894 ps
CPU time 5.43 seconds
Started Jul 21 06:38:57 PM PDT 24
Finished Jul 21 06:39:04 PM PDT 24
Peak memory 201472 kb
Host smart-0ace4354-c6b8-4eaf-8671-cb2b041bcc70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962899004 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.1962899004
Directory /workspace/37.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2825386989
Short name T134
Test name
Test status
Simulation time 14347636654 ps
CPU time 10.07 seconds
Started Jul 21 06:39:05 PM PDT 24
Finished Jul 21 06:39:16 PM PDT 24
Peak memory 201552 kb
Host smart-d24e4711-34f5-4742-81f8-33217ada0534
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825386989 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_
ctrl_ultra_low_pwr.2825386989
Directory /workspace/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_alert_test.916538361
Short name T417
Test name
Test status
Simulation time 2045981332 ps
CPU time 1.41 seconds
Started Jul 21 06:39:04 PM PDT 24
Finished Jul 21 06:39:06 PM PDT 24
Peak memory 201544 kb
Host smart-7db2029d-7794-42a9-b7d2-55c41e0d6116
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916538361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_tes
t.916538361
Directory /workspace/38.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3342045571
Short name T156
Test name
Test status
Simulation time 3350595252 ps
CPU time 9.38 seconds
Started Jul 21 06:39:04 PM PDT 24
Finished Jul 21 06:39:14 PM PDT 24
Peak memory 201620 kb
Host smart-d61e38e0-f2e2-4ee8-b7b2-83f8b53559c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342045571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.3
342045571
Directory /workspace/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect.300326018
Short name T108
Test name
Test status
Simulation time 59313859794 ps
CPU time 44.17 seconds
Started Jul 21 06:39:10 PM PDT 24
Finished Jul 21 06:39:55 PM PDT 24
Peak memory 201788 kb
Host smart-79aa046e-e5b0-4665-b455-374fd0a3c0d5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300326018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ct
rl_combo_detect.300326018
Directory /workspace/38.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.3165733790
Short name T374
Test name
Test status
Simulation time 133081335079 ps
CPU time 331.69 seconds
Started Jul 21 06:39:02 PM PDT 24
Finished Jul 21 06:44:35 PM PDT 24
Peak memory 201940 kb
Host smart-a951bf13-8dca-4471-8ff0-c10c4282ecca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165733790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_w
ith_pre_cond.3165733790
Directory /workspace/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.314954288
Short name T586
Test name
Test status
Simulation time 3214744008 ps
CPU time 9.18 seconds
Started Jul 21 06:39:04 PM PDT 24
Finished Jul 21 06:39:14 PM PDT 24
Peak memory 201528 kb
Host smart-fd689250-99df-4e23-866e-ce7e698e1b75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314954288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_c
trl_ec_pwr_on_rst.314954288
Directory /workspace/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.2711034036
Short name T621
Test name
Test status
Simulation time 2640515843 ps
CPU time 1.47 seconds
Started Jul 21 06:39:01 PM PDT 24
Finished Jul 21 06:39:03 PM PDT 24
Peak memory 201576 kb
Host smart-092de493-d145-4cb4-a0db-2825dab48153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711034036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.2711034036
Directory /workspace/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.2550207906
Short name T6
Test name
Test status
Simulation time 2486245866 ps
CPU time 2.33 seconds
Started Jul 21 06:38:58 PM PDT 24
Finished Jul 21 06:39:01 PM PDT 24
Peak memory 201516 kb
Host smart-0cf3224f-62b3-42bb-bb37-dcdce58e87ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550207906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.2550207906
Directory /workspace/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_access_test.139914102
Short name T521
Test name
Test status
Simulation time 2110811785 ps
CPU time 3.36 seconds
Started Jul 21 06:39:02 PM PDT 24
Finished Jul 21 06:39:06 PM PDT 24
Peak memory 201516 kb
Host smart-11aded5e-17b1-489f-8868-397c3fcad81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139914102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.139914102
Directory /workspace/38.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_pin_override_test.1222574195
Short name T297
Test name
Test status
Simulation time 2516910963 ps
CPU time 4.09 seconds
Started Jul 21 06:39:05 PM PDT 24
Finished Jul 21 06:39:09 PM PDT 24
Peak memory 201580 kb
Host smart-2212b398-f774-47b4-ba7e-c1a3bc701087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222574195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.1222574195
Directory /workspace/38.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_smoke.3399765718
Short name T420
Test name
Test status
Simulation time 2111377604 ps
CPU time 3.74 seconds
Started Jul 21 06:39:01 PM PDT 24
Finished Jul 21 06:39:05 PM PDT 24
Peak memory 201500 kb
Host smart-6cd5b4d4-f735-4787-9071-06366d392983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399765718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.3399765718
Directory /workspace/38.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all.1829095227
Short name T732
Test name
Test status
Simulation time 1741236620014 ps
CPU time 356.75 seconds
Started Jul 21 06:39:05 PM PDT 24
Finished Jul 21 06:45:03 PM PDT 24
Peak memory 201560 kb
Host smart-3dd6a5d8-c535-48ce-b0bb-95f97eea1512
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829095227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_s
tress_all.1829095227
Directory /workspace/38.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.641182172
Short name T185
Test name
Test status
Simulation time 25465238068 ps
CPU time 61.82 seconds
Started Jul 21 06:39:06 PM PDT 24
Finished Jul 21 06:40:08 PM PDT 24
Peak memory 210216 kb
Host smart-85721770-5343-4db7-bbd2-2d8da3a583be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641182172 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.641182172
Directory /workspace/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1896493241
Short name T663
Test name
Test status
Simulation time 5636938901 ps
CPU time 2.31 seconds
Started Jul 21 06:39:04 PM PDT 24
Finished Jul 21 06:39:07 PM PDT 24
Peak memory 201532 kb
Host smart-ceb63ce2-a105-4c6a-a7ec-db8001be5953
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896493241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_
ctrl_ultra_low_pwr.1896493241
Directory /workspace/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_alert_test.177084644
Short name T448
Test name
Test status
Simulation time 2041173050 ps
CPU time 2 seconds
Started Jul 21 06:39:12 PM PDT 24
Finished Jul 21 06:39:15 PM PDT 24
Peak memory 201524 kb
Host smart-551276f6-0b29-4c08-b4d3-be85c58fb611
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177084644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_tes
t.177084644
Directory /workspace/39.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1331196610
Short name T711
Test name
Test status
Simulation time 3200715375 ps
CPU time 9.12 seconds
Started Jul 21 06:39:10 PM PDT 24
Finished Jul 21 06:39:20 PM PDT 24
Peak memory 201656 kb
Host smart-606af578-94c7-4d77-95f8-4ec59b7d1967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331196610 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1
331196610
Directory /workspace/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect.3734938938
Short name T333
Test name
Test status
Simulation time 159466806045 ps
CPU time 414.8 seconds
Started Jul 21 06:39:05 PM PDT 24
Finished Jul 21 06:46:00 PM PDT 24
Peak memory 201760 kb
Host smart-c5aad392-4b53-4553-9f3a-282248cc9d44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734938938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_c
trl_combo_detect.3734938938
Directory /workspace/39.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.1202896409
Short name T371
Test name
Test status
Simulation time 50503073849 ps
CPU time 129.4 seconds
Started Jul 21 06:39:02 PM PDT 24
Finished Jul 21 06:41:12 PM PDT 24
Peak memory 201932 kb
Host smart-74f9b42e-d38b-4031-9bc4-cc6a0bdec675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202896409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_w
ith_pre_cond.1202896409
Directory /workspace/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1244323343
Short name T544
Test name
Test status
Simulation time 3964762421 ps
CPU time 11.11 seconds
Started Jul 21 06:39:07 PM PDT 24
Finished Jul 21 06:39:18 PM PDT 24
Peak memory 201544 kb
Host smart-9be60d9b-837b-4dcb-a0f3-7f2444c429d2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244323343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ec_pwr_on_rst.1244323343
Directory /workspace/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_edge_detect.3007579644
Short name T2
Test name
Test status
Simulation time 3465411530 ps
CPU time 2.52 seconds
Started Jul 21 06:39:02 PM PDT 24
Finished Jul 21 06:39:05 PM PDT 24
Peak memory 201540 kb
Host smart-1d0d688f-61c8-4a8c-ad18-3a520943730c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007579644 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ct
rl_edge_detect.3007579644
Directory /workspace/39.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1532824224
Short name T24
Test name
Test status
Simulation time 2609767552 ps
CPU time 7.48 seconds
Started Jul 21 06:39:04 PM PDT 24
Finished Jul 21 06:39:12 PM PDT 24
Peak memory 201532 kb
Host smart-2cb2c5ae-8f45-464d-a1df-62c3b729d035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532824224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.1532824224
Directory /workspace/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.1901790355
Short name T426
Test name
Test status
Simulation time 2487184162 ps
CPU time 1.97 seconds
Started Jul 21 06:39:04 PM PDT 24
Finished Jul 21 06:39:06 PM PDT 24
Peak memory 201548 kb
Host smart-4c36df24-a61d-4871-8020-23ea1d9ab219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901790355 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.1901790355
Directory /workspace/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_access_test.870513867
Short name T743
Test name
Test status
Simulation time 2075257703 ps
CPU time 1.27 seconds
Started Jul 21 06:39:03 PM PDT 24
Finished Jul 21 06:39:05 PM PDT 24
Peak memory 201496 kb
Host smart-da042edc-411e-4516-b687-c37f7a794f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870513867 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.870513867
Directory /workspace/39.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_pin_override_test.1348225829
Short name T612
Test name
Test status
Simulation time 2510594382 ps
CPU time 7.51 seconds
Started Jul 21 06:39:10 PM PDT 24
Finished Jul 21 06:39:18 PM PDT 24
Peak memory 201544 kb
Host smart-cba20ea3-2e0d-4209-9e99-b29eba9154ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348225829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1348225829
Directory /workspace/39.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_smoke.3268361352
Short name T648
Test name
Test status
Simulation time 2114087295 ps
CPU time 3.06 seconds
Started Jul 21 06:39:10 PM PDT 24
Finished Jul 21 06:39:13 PM PDT 24
Peak memory 201488 kb
Host smart-e65b4422-8459-4ccb-8be3-ba4a01c238a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268361352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.3268361352
Directory /workspace/39.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all.3354978848
Short name T581
Test name
Test status
Simulation time 7722380296 ps
CPU time 5.71 seconds
Started Jul 21 06:39:04 PM PDT 24
Finished Jul 21 06:39:10 PM PDT 24
Peak memory 201624 kb
Host smart-c80d1899-97de-41b2-9af4-9a0d988fb75f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354978848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_s
tress_all.3354978848
Directory /workspace/39.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2234270546
Short name T674
Test name
Test status
Simulation time 18310585340 ps
CPU time 41.15 seconds
Started Jul 21 06:39:04 PM PDT 24
Finished Jul 21 06:39:45 PM PDT 24
Peak memory 201772 kb
Host smart-b2122c69-bc85-4ba3-97f1-7902adda0d3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234270546 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.2234270546
Directory /workspace/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.sysrst_ctrl_ultra_low_pwr.1527585474
Short name T763
Test name
Test status
Simulation time 5954852232 ps
CPU time 1.84 seconds
Started Jul 21 06:39:05 PM PDT 24
Finished Jul 21 06:39:08 PM PDT 24
Peak memory 201484 kb
Host smart-d2f93065-6903-419a-95fd-1bf7ad585570
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527585474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_
ctrl_ultra_low_pwr.1527585474
Directory /workspace/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_alert_test.2530612757
Short name T597
Test name
Test status
Simulation time 2044461632 ps
CPU time 1.86 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:37:56 PM PDT 24
Peak memory 201100 kb
Host smart-708a9dd6-c148-4368-b507-a28feaca31a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530612757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_tes
t.2530612757
Directory /workspace/4.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2361141542
Short name T554
Test name
Test status
Simulation time 3495568597 ps
CPU time 5.15 seconds
Started Jul 21 06:37:46 PM PDT 24
Finished Jul 21 06:37:52 PM PDT 24
Peak memory 201624 kb
Host smart-acaa4fef-be7e-431d-8813-98b775e05b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361141542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.2361141542
Directory /workspace/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect.444555599
Short name T619
Test name
Test status
Simulation time 96020902616 ps
CPU time 253.7 seconds
Started Jul 21 06:37:45 PM PDT 24
Finished Jul 21 06:41:59 PM PDT 24
Peak memory 201780 kb
Host smart-7d8c5be1-dae2-4550-8c70-8ea7c86afc78
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444555599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_combo_detect.444555599
Directory /workspace/4.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1657618385
Short name T523
Test name
Test status
Simulation time 2436184770 ps
CPU time 1.34 seconds
Started Jul 21 06:37:46 PM PDT 24
Finished Jul 21 06:37:48 PM PDT 24
Peak memory 201548 kb
Host smart-ce4c3c73-c912-4f28-9208-169359e2f7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1657618385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.1657618385
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3093528922
Short name T430
Test name
Test status
Simulation time 2526806834 ps
CPU time 3.63 seconds
Started Jul 21 06:37:44 PM PDT 24
Finished Jul 21 06:37:48 PM PDT 24
Peak memory 201572 kb
Host smart-afce0903-310c-497e-89f6-22096c9d1fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093528922 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre
_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_de
tect_ec_rst_with_pre_cond.3093528922
Directory /workspace/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3498246415
Short name T44
Test name
Test status
Simulation time 50722468381 ps
CPU time 31.09 seconds
Started Jul 21 06:37:49 PM PDT 24
Finished Jul 21 06:38:21 PM PDT 24
Peak memory 201804 kb
Host smart-5dc2cbb9-a073-4fba-b604-faf80840d7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498246415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_wi
th_pre_cond.3498246415
Directory /workspace/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.785521666
Short name T666
Test name
Test status
Simulation time 4047977934 ps
CPU time 3.41 seconds
Started Jul 21 06:37:44 PM PDT 24
Finished Jul 21 06:37:48 PM PDT 24
Peak memory 201540 kb
Host smart-4df3f6d0-a24a-468b-b9ae-95ca9b3c7bf2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785521666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ct
rl_ec_pwr_on_rst.785521666
Directory /workspace/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_edge_detect.1853992780
Short name T734
Test name
Test status
Simulation time 3579083670 ps
CPU time 2.16 seconds
Started Jul 21 06:37:46 PM PDT 24
Finished Jul 21 06:37:49 PM PDT 24
Peak memory 201560 kb
Host smart-db573daa-ca48-406b-b98b-06bb862c87ac
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853992780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctr
l_edge_detect.1853992780
Directory /workspace/4.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.95127458
Short name T387
Test name
Test status
Simulation time 2609803644 ps
CPU time 7.36 seconds
Started Jul 21 06:37:47 PM PDT 24
Finished Jul 21 06:37:55 PM PDT 24
Peak memory 201564 kb
Host smart-850e6bfc-2359-40d8-ac5f-4c5a7107506e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95127458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.95127458
Directory /workspace/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_in_out_inverted.3661091967
Short name T751
Test name
Test status
Simulation time 2484136163 ps
CPU time 4.14 seconds
Started Jul 21 06:37:47 PM PDT 24
Finished Jul 21 06:37:53 PM PDT 24
Peak memory 201580 kb
Host smart-43ff8ce8-218c-4c67-b151-ccc35aeee7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661091967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.3661091967
Directory /workspace/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_access_test.2879389688
Short name T731
Test name
Test status
Simulation time 2144097015 ps
CPU time 2.15 seconds
Started Jul 21 06:37:46 PM PDT 24
Finished Jul 21 06:37:49 PM PDT 24
Peak memory 201480 kb
Host smart-1d1df251-7d17-460a-b8f3-195cb64fa6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879389688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.2879389688
Directory /workspace/4.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_pin_override_test.1637662339
Short name T509
Test name
Test status
Simulation time 2525705020 ps
CPU time 2.16 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:37:56 PM PDT 24
Peak memory 201344 kb
Host smart-4ef914cb-18a2-4d44-bcf1-51fdc2c2eec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637662339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.1637662339
Directory /workspace/4.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_sec_cm.872576320
Short name T231
Test name
Test status
Simulation time 42080418960 ps
CPU time 30.17 seconds
Started Jul 21 06:37:50 PM PDT 24
Finished Jul 21 06:38:23 PM PDT 24
Peak memory 220948 kb
Host smart-ce75b61c-4ff7-4b07-ba9c-6726475343ad
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872576320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.872576320
Directory /workspace/4.sysrst_ctrl_sec_cm/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_smoke.2402387364
Short name T512
Test name
Test status
Simulation time 2116254220 ps
CPU time 3.46 seconds
Started Jul 21 06:37:46 PM PDT 24
Finished Jul 21 06:37:50 PM PDT 24
Peak memory 201448 kb
Host smart-99c73a99-ca1e-4cc8-8702-5bb59d04fb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402387364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.2402387364
Directory /workspace/4.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all.4074177536
Short name T667
Test name
Test status
Simulation time 9060659471 ps
CPU time 24.13 seconds
Started Jul 21 06:37:50 PM PDT 24
Finished Jul 21 06:38:16 PM PDT 24
Peak memory 201568 kb
Host smart-847010f0-3de0-4e69-9313-641c52e05839
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074177536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_st
ress_all.4074177536
Directory /workspace/4.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.128875174
Short name T373
Test name
Test status
Simulation time 449831582524 ps
CPU time 27.57 seconds
Started Jul 21 06:37:54 PM PDT 24
Finished Jul 21 06:38:24 PM PDT 24
Peak memory 218100 kb
Host smart-4c27f104-140e-4456-a6eb-e10cf0e73101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128875174 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.128875174
Directory /workspace/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_alert_test.916996278
Short name T177
Test name
Test status
Simulation time 2013094574 ps
CPU time 5.67 seconds
Started Jul 21 06:39:13 PM PDT 24
Finished Jul 21 06:39:19 PM PDT 24
Peak memory 201528 kb
Host smart-abde7d51-74f6-41ef-80c1-629c82d20cca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916996278 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_tes
t.916996278
Directory /workspace/40.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3142096683
Short name T741
Test name
Test status
Simulation time 3403337659 ps
CPU time 2.72 seconds
Started Jul 21 06:39:14 PM PDT 24
Finished Jul 21 06:39:17 PM PDT 24
Peak memory 201628 kb
Host smart-0f479d5c-c5aa-4e08-bbf2-96993e80f908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142096683 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.3
142096683
Directory /workspace/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect.3773699200
Short name T252
Test name
Test status
Simulation time 73098648295 ps
CPU time 93.41 seconds
Started Jul 21 06:39:12 PM PDT 24
Finished Jul 21 06:40:46 PM PDT 24
Peak memory 201772 kb
Host smart-08bca007-9188-460b-9d9f-271d7e2a89dc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773699200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_combo_detect.3773699200
Directory /workspace/40.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1330687837
Short name T73
Test name
Test status
Simulation time 24836504442 ps
CPU time 28.04 seconds
Started Jul 21 06:39:11 PM PDT 24
Finished Jul 21 06:39:39 PM PDT 24
Peak memory 201936 kb
Host smart-81929cfb-bba6-4bc6-9e22-c0dcc5c7ea31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330687837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_w
ith_pre_cond.1330687837
Directory /workspace/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1307752859
Short name T490
Test name
Test status
Simulation time 4928162476 ps
CPU time 13.56 seconds
Started Jul 21 06:39:10 PM PDT 24
Finished Jul 21 06:39:24 PM PDT 24
Peak memory 201588 kb
Host smart-b402c1a3-ea48-4a01-b737-03f9974ecbde
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307752859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_
ctrl_ec_pwr_on_rst.1307752859
Directory /workspace/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_edge_detect.1534698510
Short name T184
Test name
Test status
Simulation time 4429330701 ps
CPU time 7.31 seconds
Started Jul 21 06:39:10 PM PDT 24
Finished Jul 21 06:39:18 PM PDT 24
Peak memory 201564 kb
Host smart-2ae9b4dc-003a-4436-bd53-f8849cdf7d4f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534698510 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ct
rl_edge_detect.1534698510
Directory /workspace/40.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.554283064
Short name T449
Test name
Test status
Simulation time 2630105402 ps
CPU time 2.03 seconds
Started Jul 21 06:39:12 PM PDT 24
Finished Jul 21 06:39:14 PM PDT 24
Peak memory 201588 kb
Host smart-0a80a5a8-5a0a-4ac0-aa39-8f45d1057bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554283064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.554283064
Directory /workspace/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_in_out_inverted.1233373871
Short name T551
Test name
Test status
Simulation time 2502711788 ps
CPU time 2.35 seconds
Started Jul 21 06:39:12 PM PDT 24
Finished Jul 21 06:39:15 PM PDT 24
Peak memory 201560 kb
Host smart-e30d07a3-ce5c-4273-867e-523fca071d5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233373871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.1233373871
Directory /workspace/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3693591275
Short name T128
Test name
Test status
Simulation time 2257455868 ps
CPU time 2.02 seconds
Started Jul 21 06:39:12 PM PDT 24
Finished Jul 21 06:39:15 PM PDT 24
Peak memory 201528 kb
Host smart-15c70f62-1459-4502-8427-ead19373f2a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693591275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.3693591275
Directory /workspace/40.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_pin_override_test.1415279676
Short name T718
Test name
Test status
Simulation time 2511912541 ps
CPU time 7.38 seconds
Started Jul 21 06:39:13 PM PDT 24
Finished Jul 21 06:39:21 PM PDT 24
Peak memory 201440 kb
Host smart-c7ecf792-20c0-4c57-8a9b-1a34f457ff52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415279676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.1415279676
Directory /workspace/40.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_smoke.1610028036
Short name T541
Test name
Test status
Simulation time 2120443607 ps
CPU time 3.2 seconds
Started Jul 21 06:39:12 PM PDT 24
Finished Jul 21 06:39:16 PM PDT 24
Peak memory 201404 kb
Host smart-7caf00ee-973c-420d-84b8-11ce602aa474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610028036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.1610028036
Directory /workspace/40.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all.78191222
Short name T23
Test name
Test status
Simulation time 16762619332 ps
CPU time 20.95 seconds
Started Jul 21 06:39:11 PM PDT 24
Finished Jul 21 06:39:33 PM PDT 24
Peak memory 201552 kb
Host smart-261359cc-0003-4385-80d5-c84a45ebd1c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78191222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_str
ess_all.78191222
Directory /workspace/40.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2144572712
Short name T179
Test name
Test status
Simulation time 21904021642 ps
CPU time 56.19 seconds
Started Jul 21 06:39:13 PM PDT 24
Finished Jul 21 06:40:10 PM PDT 24
Peak memory 218228 kb
Host smart-1d4a1e60-a370-4306-bcdf-b9af3f3dc760
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144572712 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.2144572712
Directory /workspace/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.sysrst_ctrl_ultra_low_pwr.399032897
Short name T672
Test name
Test status
Simulation time 6516461117 ps
CPU time 8.69 seconds
Started Jul 21 06:39:12 PM PDT 24
Finished Jul 21 06:39:21 PM PDT 24
Peak memory 201576 kb
Host smart-458433d4-8854-42ad-b4aa-b8c75a89b17c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399032897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_c
trl_ultra_low_pwr.399032897
Directory /workspace/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_alert_test.4149690304
Short name T209
Test name
Test status
Simulation time 2031681278 ps
CPU time 2.02 seconds
Started Jul 21 06:39:16 PM PDT 24
Finished Jul 21 06:39:18 PM PDT 24
Peak memory 201552 kb
Host smart-91182eac-3812-4928-8e4d-1afbc230900f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149690304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_te
st.4149690304
Directory /workspace/41.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_auto_blk_key_output.4015084602
Short name T756
Test name
Test status
Simulation time 3138153714 ps
CPU time 2.86 seconds
Started Jul 21 06:39:11 PM PDT 24
Finished Jul 21 06:39:14 PM PDT 24
Peak memory 201604 kb
Host smart-76ee2e49-f388-4327-987e-fd322c5faee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015084602 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.4
015084602
Directory /workspace/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_combo_detect.270239851
Short name T765
Test name
Test status
Simulation time 139733156077 ps
CPU time 346.98 seconds
Started Jul 21 06:39:12 PM PDT 24
Finished Jul 21 06:45:00 PM PDT 24
Peak memory 201788 kb
Host smart-b55b4503-183d-4ca8-a7e5-8219b3d7870d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270239851 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_combo_detect.270239851
Directory /workspace/41.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.571466486
Short name T566
Test name
Test status
Simulation time 4285941409 ps
CPU time 11.58 seconds
Started Jul 21 06:39:12 PM PDT 24
Finished Jul 21 06:39:24 PM PDT 24
Peak memory 201576 kb
Host smart-bc976cf9-09e6-4311-809f-7d0ccf566c46
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571466486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_c
trl_ec_pwr_on_rst.571466486
Directory /workspace/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_edge_detect.3271491893
Short name T567
Test name
Test status
Simulation time 4680519408 ps
CPU time 2.96 seconds
Started Jul 21 06:39:13 PM PDT 24
Finished Jul 21 06:39:16 PM PDT 24
Peak memory 201512 kb
Host smart-13a4c496-c102-4c09-852f-bea4edb4ea8c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271491893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ct
rl_edge_detect.3271491893
Directory /workspace/41.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2716795133
Short name T429
Test name
Test status
Simulation time 2646273313 ps
CPU time 1.59 seconds
Started Jul 21 06:39:13 PM PDT 24
Finished Jul 21 06:39:15 PM PDT 24
Peak memory 201564 kb
Host smart-fa879396-105c-455e-80d1-c2d6ddac5bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716795133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.2716795133
Directory /workspace/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.2194215333
Short name T402
Test name
Test status
Simulation time 2517556778 ps
CPU time 2.11 seconds
Started Jul 21 06:39:10 PM PDT 24
Finished Jul 21 06:39:12 PM PDT 24
Peak memory 201564 kb
Host smart-23e923ea-8310-421a-932c-124ebbb7bec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194215333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.2194215333
Directory /workspace/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_access_test.1748002651
Short name T229
Test name
Test status
Simulation time 2113722427 ps
CPU time 5.91 seconds
Started Jul 21 06:39:09 PM PDT 24
Finished Jul 21 06:39:15 PM PDT 24
Peak memory 201436 kb
Host smart-449f440e-81ee-4a70-a576-126b21c9f72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748002651 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1748002651
Directory /workspace/41.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_pin_override_test.231791570
Short name T697
Test name
Test status
Simulation time 2551227925 ps
CPU time 1.82 seconds
Started Jul 21 06:39:12 PM PDT 24
Finished Jul 21 06:39:14 PM PDT 24
Peak memory 201596 kb
Host smart-28634d78-d78f-406d-8b56-263ba8e31df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231791570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.231791570
Directory /workspace/41.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_smoke.1587827863
Short name T728
Test name
Test status
Simulation time 2129989835 ps
CPU time 1.86 seconds
Started Jul 21 06:39:14 PM PDT 24
Finished Jul 21 06:39:16 PM PDT 24
Peak memory 201476 kb
Host smart-6d1de0df-6841-41b4-a395-5fab46ef761b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587827863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.1587827863
Directory /workspace/41.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all.3201154388
Short name T673
Test name
Test status
Simulation time 9777791290 ps
CPU time 26.75 seconds
Started Jul 21 06:39:18 PM PDT 24
Finished Jul 21 06:39:46 PM PDT 24
Peak memory 201560 kb
Host smart-b4a0a049-fb0f-4fbd-a811-9f78fd1c446e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201154388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_s
tress_all.3201154388
Directory /workspace/41.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2747074905
Short name T15
Test name
Test status
Simulation time 19876879658 ps
CPU time 54.25 seconds
Started Jul 21 06:39:16 PM PDT 24
Finished Jul 21 06:40:11 PM PDT 24
Peak memory 210168 kb
Host smart-dd854c41-2513-4567-bb4b-002b90047e98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747074905 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.2747074905
Directory /workspace/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3551116274
Short name T32
Test name
Test status
Simulation time 9750673004 ps
CPU time 2.94 seconds
Started Jul 21 06:39:13 PM PDT 24
Finished Jul 21 06:39:17 PM PDT 24
Peak memory 201544 kb
Host smart-b33e1c88-a62b-40e3-b040-a6bd4c7c80bf
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551116274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_
ctrl_ultra_low_pwr.3551116274
Directory /workspace/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_alert_test.3536021240
Short name T738
Test name
Test status
Simulation time 2033568980 ps
CPU time 2.04 seconds
Started Jul 21 06:39:18 PM PDT 24
Finished Jul 21 06:39:21 PM PDT 24
Peak memory 201428 kb
Host smart-8eefb47a-7240-4f59-a4b2-d43ad3e2ee0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536021240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_te
st.3536021240
Directory /workspace/42.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_auto_blk_key_output.1290664316
Short name T693
Test name
Test status
Simulation time 3410532052 ps
CPU time 9.37 seconds
Started Jul 21 06:39:17 PM PDT 24
Finished Jul 21 06:39:27 PM PDT 24
Peak memory 201576 kb
Host smart-c647b0c4-7aba-4fe5-b841-5389e1cca18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290664316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.1
290664316
Directory /workspace/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect.2186668143
Short name T99
Test name
Test status
Simulation time 20686486936 ps
CPU time 53.18 seconds
Started Jul 21 06:39:16 PM PDT 24
Finished Jul 21 06:40:10 PM PDT 24
Peak memory 201776 kb
Host smart-4ec3dbf6-59a7-40af-823a-5f086e1e21a6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186668143 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_c
trl_combo_detect.2186668143
Directory /workspace/42.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.496499646
Short name T72
Test name
Test status
Simulation time 45659725011 ps
CPU time 29.89 seconds
Started Jul 21 06:39:15 PM PDT 24
Finished Jul 21 06:39:46 PM PDT 24
Peak memory 201788 kb
Host smart-ebf74221-7a2a-48e7-bacb-41313e9b8979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496499646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_wi
th_pre_cond.496499646
Directory /workspace/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.1380730858
Short name T525
Test name
Test status
Simulation time 298238259548 ps
CPU time 102.74 seconds
Started Jul 21 06:39:17 PM PDT 24
Finished Jul 21 06:41:00 PM PDT 24
Peak memory 201540 kb
Host smart-14f8ab30-d214-4169-8be1-4878cd2c07c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380730858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ec_pwr_on_rst.1380730858
Directory /workspace/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_edge_detect.3327475305
Short name T181
Test name
Test status
Simulation time 3956571379 ps
CPU time 7.52 seconds
Started Jul 21 06:39:18 PM PDT 24
Finished Jul 21 06:39:27 PM PDT 24
Peak memory 201564 kb
Host smart-e437f535-4b71-47ae-9304-b0ea09821c24
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327475305 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ct
rl_edge_detect.3327475305
Directory /workspace/42.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.4197862324
Short name T759
Test name
Test status
Simulation time 2649465051 ps
CPU time 1.52 seconds
Started Jul 21 06:39:17 PM PDT 24
Finished Jul 21 06:39:19 PM PDT 24
Peak memory 201556 kb
Host smart-7f137ff1-cb64-40a2-ae0c-bebdff819c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197862324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.4197862324
Directory /workspace/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.4002201672
Short name T191
Test name
Test status
Simulation time 2494392324 ps
CPU time 2.32 seconds
Started Jul 21 06:39:16 PM PDT 24
Finished Jul 21 06:39:19 PM PDT 24
Peak memory 201548 kb
Host smart-de014adb-cc46-439c-a1f9-b53ae5b0a76f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002201672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.4002201672
Directory /workspace/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4008635698
Short name T199
Test name
Test status
Simulation time 2213128730 ps
CPU time 2.18 seconds
Started Jul 21 06:39:16 PM PDT 24
Finished Jul 21 06:39:18 PM PDT 24
Peak memory 201568 kb
Host smart-939d0e07-0a9f-4fd0-97c0-7ad440b13183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008635698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.4008635698
Directory /workspace/42.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_pin_override_test.2548335417
Short name T161
Test name
Test status
Simulation time 2519976299 ps
CPU time 2.93 seconds
Started Jul 21 06:39:15 PM PDT 24
Finished Jul 21 06:39:18 PM PDT 24
Peak memory 201540 kb
Host smart-a77b558b-6474-44bc-981e-19f682a2ad37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548335417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.2548335417
Directory /workspace/42.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_smoke.1243341932
Short name T400
Test name
Test status
Simulation time 2122546476 ps
CPU time 3.08 seconds
Started Jul 21 06:39:19 PM PDT 24
Finished Jul 21 06:39:23 PM PDT 24
Peak memory 201468 kb
Host smart-fd2cb707-c185-4d99-990c-45205e0738e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243341932 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.1243341932
Directory /workspace/42.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all.1742487954
Short name T303
Test name
Test status
Simulation time 16419313471 ps
CPU time 27.7 seconds
Started Jul 21 06:39:18 PM PDT 24
Finished Jul 21 06:39:46 PM PDT 24
Peak memory 201560 kb
Host smart-552306a3-9c30-4281-b34c-878210267758
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742487954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_s
tress_all.1742487954
Directory /workspace/42.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3204132929
Short name T290
Test name
Test status
Simulation time 32588982504 ps
CPU time 66.85 seconds
Started Jul 21 06:39:16 PM PDT 24
Finished Jul 21 06:40:24 PM PDT 24
Peak memory 201704 kb
Host smart-ca11647b-6be8-4383-ae39-bf4d4081cd0e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204132929 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.3204132929
Directory /workspace/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1589344203
Short name T87
Test name
Test status
Simulation time 6984674283 ps
CPU time 8.2 seconds
Started Jul 21 06:39:23 PM PDT 24
Finished Jul 21 06:39:31 PM PDT 24
Peak memory 201516 kb
Host smart-18775345-d9e9-4815-8175-8f4a3d9d046a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589344203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_
ctrl_ultra_low_pwr.1589344203
Directory /workspace/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_alert_test.3758826835
Short name T606
Test name
Test status
Simulation time 2022015443 ps
CPU time 3.31 seconds
Started Jul 21 06:39:23 PM PDT 24
Finished Jul 21 06:39:26 PM PDT 24
Peak memory 201532 kb
Host smart-73b61f41-fcfb-4d11-8447-c2e12b849487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758826835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_te
st.3758826835
Directory /workspace/43.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2065274087
Short name T446
Test name
Test status
Simulation time 3305414887 ps
CPU time 9.27 seconds
Started Jul 21 06:39:20 PM PDT 24
Finished Jul 21 06:39:29 PM PDT 24
Peak memory 201676 kb
Host smart-c75632ac-1ef4-4e94-a282-cdd011ba6077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065274087 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.2
065274087
Directory /workspace/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect.831747697
Short name T258
Test name
Test status
Simulation time 110257183242 ps
CPU time 287.74 seconds
Started Jul 21 06:39:18 PM PDT 24
Finished Jul 21 06:44:06 PM PDT 24
Peak memory 201808 kb
Host smart-e0365d49-ccd1-4c04-8644-59adfafb65b9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831747697 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_combo_detect.831747697
Directory /workspace/43.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.684654010
Short name T129
Test name
Test status
Simulation time 68357644697 ps
CPU time 25.74 seconds
Started Jul 21 06:39:18 PM PDT 24
Finished Jul 21 06:39:45 PM PDT 24
Peak memory 201916 kb
Host smart-79f4a06d-ff12-4665-88dd-fdd4917c9b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684654010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_wi
th_pre_cond.684654010
Directory /workspace/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1749652841
Short name T485
Test name
Test status
Simulation time 3616138374 ps
CPU time 9.65 seconds
Started Jul 21 06:39:19 PM PDT 24
Finished Jul 21 06:39:29 PM PDT 24
Peak memory 201556 kb
Host smart-80bbbbba-a9bf-45c2-b8b5-b8f252d6e50b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749652841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_
ctrl_ec_pwr_on_rst.1749652841
Directory /workspace/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_edge_detect.3963818046
Short name T143
Test name
Test status
Simulation time 3454309979 ps
CPU time 2.39 seconds
Started Jul 21 06:39:16 PM PDT 24
Finished Jul 21 06:39:19 PM PDT 24
Peak memory 201544 kb
Host smart-bfc932f8-68cb-4d05-9675-bfdfba94327c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963818046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ct
rl_edge_detect.3963818046
Directory /workspace/43.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2407667973
Short name T684
Test name
Test status
Simulation time 2619288117 ps
CPU time 3.73 seconds
Started Jul 21 06:39:20 PM PDT 24
Finished Jul 21 06:39:24 PM PDT 24
Peak memory 201580 kb
Host smart-e325c607-6ce1-4432-b393-7e349db4859b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407667973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.2407667973
Directory /workspace/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3001006441
Short name T514
Test name
Test status
Simulation time 2526757273 ps
CPU time 1.49 seconds
Started Jul 21 06:39:17 PM PDT 24
Finished Jul 21 06:39:19 PM PDT 24
Peak memory 201528 kb
Host smart-db33dca8-542b-433f-a8b8-2540539b0904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001006441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.3001006441
Directory /workspace/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3749254064
Short name T647
Test name
Test status
Simulation time 2093724934 ps
CPU time 1.76 seconds
Started Jul 21 06:39:19 PM PDT 24
Finished Jul 21 06:39:22 PM PDT 24
Peak memory 201404 kb
Host smart-756dc9ae-79dc-45b7-8a8c-f5837d1e1dc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749254064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.3749254064
Directory /workspace/43.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2735487883
Short name T122
Test name
Test status
Simulation time 2624684712 ps
CPU time 1.05 seconds
Started Jul 21 06:39:19 PM PDT 24
Finished Jul 21 06:39:21 PM PDT 24
Peak memory 201540 kb
Host smart-7ca71735-6670-45eb-86fc-ed0102dc9bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735487883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.2735487883
Directory /workspace/43.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_smoke.2392305898
Short name T708
Test name
Test status
Simulation time 2113229500 ps
CPU time 5.96 seconds
Started Jul 21 06:39:16 PM PDT 24
Finished Jul 21 06:39:23 PM PDT 24
Peak memory 201636 kb
Host smart-a5c1a9ed-7199-4912-abb9-6d53e04d8b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392305898 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2392305898
Directory /workspace/43.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all.1560357395
Short name T396
Test name
Test status
Simulation time 8740741829 ps
CPU time 17.97 seconds
Started Jul 21 06:39:19 PM PDT 24
Finished Jul 21 06:39:37 PM PDT 24
Peak memory 201528 kb
Host smart-b420fcd2-beb7-4e9b-aa03-338564bc85a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560357395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_s
tress_all.1560357395
Directory /workspace/43.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2447472219
Short name T306
Test name
Test status
Simulation time 5711789534 ps
CPU time 11.38 seconds
Started Jul 21 06:39:20 PM PDT 24
Finished Jul 21 06:39:32 PM PDT 24
Peak memory 201680 kb
Host smart-fc560e23-c4f7-49f4-a16b-5df30dd2bc96
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447472219 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.2447472219
Directory /workspace/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.877249949
Short name T692
Test name
Test status
Simulation time 11745637999 ps
CPU time 4.84 seconds
Started Jul 21 06:39:19 PM PDT 24
Finished Jul 21 06:39:25 PM PDT 24
Peak memory 201584 kb
Host smart-d58240d8-334a-4b81-9438-83517b3522a4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877249949 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_c
trl_ultra_low_pwr.877249949
Directory /workspace/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_alert_test.3489235137
Short name T757
Test name
Test status
Simulation time 2020264114 ps
CPU time 3.48 seconds
Started Jul 21 06:39:22 PM PDT 24
Finished Jul 21 06:39:26 PM PDT 24
Peak memory 201540 kb
Host smart-ea35008e-bb43-495d-8f63-aea6a32f00e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489235137 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_te
st.3489235137
Directory /workspace/44.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2324806631
Short name T480
Test name
Test status
Simulation time 56433405968 ps
CPU time 144.19 seconds
Started Jul 21 06:39:25 PM PDT 24
Finished Jul 21 06:41:49 PM PDT 24
Peak memory 201572 kb
Host smart-16ff5e02-bc5b-4e94-876c-bcbf0dadc5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324806631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.2
324806631
Directory /workspace/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect.1765605978
Short name T337
Test name
Test status
Simulation time 119760425519 ps
CPU time 309.69 seconds
Started Jul 21 06:39:23 PM PDT 24
Finished Jul 21 06:44:33 PM PDT 24
Peak memory 201768 kb
Host smart-d31fc541-5cb5-407f-ad30-76c777afacad
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765605978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_c
trl_combo_detect.1765605978
Directory /workspace/44.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.928013554
Short name T740
Test name
Test status
Simulation time 28111592657 ps
CPU time 19.26 seconds
Started Jul 21 06:39:22 PM PDT 24
Finished Jul 21 06:39:42 PM PDT 24
Peak memory 201888 kb
Host smart-6f79351a-80fd-4d4d-badf-7d8744c2b137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928013554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_wi
th_pre_cond.928013554
Directory /workspace/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3837822053
Short name T543
Test name
Test status
Simulation time 2881320979 ps
CPU time 8.01 seconds
Started Jul 21 06:39:25 PM PDT 24
Finished Jul 21 06:39:34 PM PDT 24
Peak memory 201516 kb
Host smart-2188c6a4-7b4f-44c0-9b40-524a6d5500b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837822053 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ec_pwr_on_rst.3837822053
Directory /workspace/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_edge_detect.4000714505
Short name T141
Test name
Test status
Simulation time 2821555178 ps
CPU time 7.15 seconds
Started Jul 21 06:39:26 PM PDT 24
Finished Jul 21 06:39:34 PM PDT 24
Peak memory 201504 kb
Host smart-686c39cb-2caf-4c3d-96b9-ae9215130b72
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000714505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ct
rl_edge_detect.4000714505
Directory /workspace/44.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1379604338
Short name T51
Test name
Test status
Simulation time 2638253779 ps
CPU time 1.91 seconds
Started Jul 21 06:39:18 PM PDT 24
Finished Jul 21 06:39:21 PM PDT 24
Peak memory 201560 kb
Host smart-ef94afec-ae2b-42cc-9324-904044d81e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379604338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.1379604338
Directory /workspace/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2973319888
Short name T658
Test name
Test status
Simulation time 2478063680 ps
CPU time 7.22 seconds
Started Jul 21 06:39:19 PM PDT 24
Finished Jul 21 06:39:27 PM PDT 24
Peak memory 201488 kb
Host smart-0b5d678f-76e3-414c-8716-67fbb11812e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973319888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.2973319888
Directory /workspace/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2337030525
Short name T487
Test name
Test status
Simulation time 2338812393 ps
CPU time 1.23 seconds
Started Jul 21 06:39:18 PM PDT 24
Finished Jul 21 06:39:20 PM PDT 24
Peak memory 201556 kb
Host smart-4d7f90c4-6857-4c76-8112-6325f07c7308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337030525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.2337030525
Directory /workspace/44.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2308868571
Short name T670
Test name
Test status
Simulation time 2508880869 ps
CPU time 6.82 seconds
Started Jul 21 06:39:18 PM PDT 24
Finished Jul 21 06:39:26 PM PDT 24
Peak memory 201556 kb
Host smart-b7e44ab4-864c-4347-a514-2e9937397732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308868571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.2308868571
Directory /workspace/44.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_smoke.1001824421
Short name T593
Test name
Test status
Simulation time 2108290348 ps
CPU time 5.79 seconds
Started Jul 21 06:39:20 PM PDT 24
Finished Jul 21 06:39:26 PM PDT 24
Peak memory 201468 kb
Host smart-6de1f5c4-3839-4891-868d-859b2d2024ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001824421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.1001824421
Directory /workspace/44.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all.2513935762
Short name T689
Test name
Test status
Simulation time 7150207119 ps
CPU time 8.74 seconds
Started Jul 21 06:39:26 PM PDT 24
Finished Jul 21 06:39:35 PM PDT 24
Peak memory 201520 kb
Host smart-58ddc680-bbfc-4a34-9ad5-824a9a1c90c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513935762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_s
tress_all.2513935762
Directory /workspace/44.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.578318172
Short name T208
Test name
Test status
Simulation time 293698308371 ps
CPU time 293.01 seconds
Started Jul 21 06:39:24 PM PDT 24
Finished Jul 21 06:44:18 PM PDT 24
Peak memory 210212 kb
Host smart-1c754d9a-65f6-41f8-8f6f-6661bafcdb02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578318172 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.578318172
Directory /workspace/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1224349281
Short name T778
Test name
Test status
Simulation time 4807135737 ps
CPU time 6.58 seconds
Started Jul 21 06:39:24 PM PDT 24
Finished Jul 21 06:39:31 PM PDT 24
Peak memory 201556 kb
Host smart-0fc9d752-4eff-4560-9cb7-996249dc22ab
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224349281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_
ctrl_ultra_low_pwr.1224349281
Directory /workspace/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_alert_test.630889657
Short name T410
Test name
Test status
Simulation time 2034744368 ps
CPU time 1.91 seconds
Started Jul 21 06:39:24 PM PDT 24
Finished Jul 21 06:39:27 PM PDT 24
Peak memory 201536 kb
Host smart-9c2c2dc3-f6b8-4cf5-88b5-89fb8d535ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630889657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_tes
t.630889657
Directory /workspace/45.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1331011462
Short name T450
Test name
Test status
Simulation time 321235599655 ps
CPU time 408.33 seconds
Started Jul 21 06:39:24 PM PDT 24
Finished Jul 21 06:46:13 PM PDT 24
Peak memory 201628 kb
Host smart-99efdb77-ce66-4964-a8b9-e5444dd073f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331011462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.1
331011462
Directory /workspace/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect.2818188328
Short name T91
Test name
Test status
Simulation time 76009338556 ps
CPU time 201.46 seconds
Started Jul 21 06:39:24 PM PDT 24
Finished Jul 21 06:42:46 PM PDT 24
Peak memory 201736 kb
Host smart-b81a3885-cbbb-46fc-8a98-7bd3f37dd1fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818188328 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_c
trl_combo_detect.2818188328
Directory /workspace/45.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.250515759
Short name T96
Test name
Test status
Simulation time 27579810491 ps
CPU time 66.91 seconds
Started Jul 21 06:39:23 PM PDT 24
Finished Jul 21 06:40:31 PM PDT 24
Peak memory 201856 kb
Host smart-5e04d7a6-742b-4342-8c99-fd0435a7d935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250515759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_wi
th_pre_cond.250515759
Directory /workspace/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1123510186
Short name T411
Test name
Test status
Simulation time 1860748986843 ps
CPU time 2239.74 seconds
Started Jul 21 06:39:25 PM PDT 24
Finished Jul 21 07:16:46 PM PDT 24
Peak memory 201516 kb
Host smart-43dbd7ce-b184-4e9a-a1b0-d20e4b7bf40b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123510186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_
ctrl_ec_pwr_on_rst.1123510186
Directory /workspace/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_edge_detect.3856835259
Short name T419
Test name
Test status
Simulation time 2895106907 ps
CPU time 2.92 seconds
Started Jul 21 06:39:26 PM PDT 24
Finished Jul 21 06:39:30 PM PDT 24
Peak memory 201536 kb
Host smart-616e54a1-6f7c-4110-bed9-781a2a4ecdba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856835259 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_edge_detect.3856835259
Directory /workspace/45.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2301932283
Short name T204
Test name
Test status
Simulation time 2655029291 ps
CPU time 1.69 seconds
Started Jul 21 06:39:25 PM PDT 24
Finished Jul 21 06:39:27 PM PDT 24
Peak memory 201580 kb
Host smart-ef375ae6-75b6-499e-8009-9b2113449fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301932283 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.2301932283
Directory /workspace/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3243130696
Short name T118
Test name
Test status
Simulation time 2462918908 ps
CPU time 2.21 seconds
Started Jul 21 06:39:23 PM PDT 24
Finished Jul 21 06:39:25 PM PDT 24
Peak memory 201484 kb
Host smart-cd8f7bea-8bb1-48e2-b1b3-5e181aea1c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243130696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.3243130696
Directory /workspace/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2000436817
Short name T383
Test name
Test status
Simulation time 2234090572 ps
CPU time 6.4 seconds
Started Jul 21 06:39:23 PM PDT 24
Finished Jul 21 06:39:30 PM PDT 24
Peak memory 201540 kb
Host smart-72f38566-9200-4739-af6b-c229b9dd623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000436817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2000436817
Directory /workspace/45.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3443780215
Short name T232
Test name
Test status
Simulation time 2515297745 ps
CPU time 3.83 seconds
Started Jul 21 06:39:26 PM PDT 24
Finished Jul 21 06:39:30 PM PDT 24
Peak memory 201536 kb
Host smart-fe73be22-c0e5-4ce1-af0d-77410ae8dc7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443780215 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.3443780215
Directory /workspace/45.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_smoke.3989816171
Short name T432
Test name
Test status
Simulation time 2110092496 ps
CPU time 5.86 seconds
Started Jul 21 06:39:26 PM PDT 24
Finished Jul 21 06:39:33 PM PDT 24
Peak memory 201488 kb
Host smart-0439acff-d6b7-43b1-a87e-159d25a1880b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989816171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.3989816171
Directory /workspace/45.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all.1181003042
Short name T197
Test name
Test status
Simulation time 8223444463 ps
CPU time 19.89 seconds
Started Jul 21 06:39:23 PM PDT 24
Finished Jul 21 06:39:43 PM PDT 24
Peak memory 201548 kb
Host smart-62d44b90-be69-4ee8-8cb3-9a1fb7c65608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181003042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_s
tress_all.1181003042
Directory /workspace/45.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2204067766
Short name T88
Test name
Test status
Simulation time 112428086144 ps
CPU time 72.5 seconds
Started Jul 21 06:39:24 PM PDT 24
Finished Jul 21 06:40:37 PM PDT 24
Peak memory 218452 kb
Host smart-48951862-701d-4433-93be-a56eed3fe27d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204067766 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.2204067766
Directory /workspace/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.24064854
Short name T113
Test name
Test status
Simulation time 2766670678 ps
CPU time 2.14 seconds
Started Jul 21 06:39:24 PM PDT 24
Finished Jul 21 06:39:27 PM PDT 24
Peak memory 201548 kb
Host smart-a840ee7e-bd1b-49e0-90e2-6d8ced585cb6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24064854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ct
rl_ultra_low_pwr.24064854
Directory /workspace/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_alert_test.1750229024
Short name T424
Test name
Test status
Simulation time 2035389354 ps
CPU time 1.88 seconds
Started Jul 21 06:39:24 PM PDT 24
Finished Jul 21 06:39:27 PM PDT 24
Peak memory 201520 kb
Host smart-84ebaef0-66f6-4e6b-a768-1b906048213b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1750229024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_te
st.1750229024
Directory /workspace/46.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1357396471
Short name T736
Test name
Test status
Simulation time 3534860933 ps
CPU time 10.21 seconds
Started Jul 21 06:39:26 PM PDT 24
Finished Jul 21 06:39:37 PM PDT 24
Peak memory 201536 kb
Host smart-b6bbcea5-9a14-492d-96eb-904c4202dbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357396471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.1
357396471
Directory /workspace/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3972232468
Short name T254
Test name
Test status
Simulation time 82494339472 ps
CPU time 204.33 seconds
Started Jul 21 06:39:27 PM PDT 24
Finished Jul 21 06:42:52 PM PDT 24
Peak memory 201860 kb
Host smart-fec42250-ad24-4891-a72d-97a5ef2e06a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972232468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_w
ith_pre_cond.3972232468
Directory /workspace/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.81956264
Short name T124
Test name
Test status
Simulation time 21285641834 ps
CPU time 13.79 seconds
Started Jul 21 06:39:24 PM PDT 24
Finished Jul 21 06:39:38 PM PDT 24
Peak memory 201560 kb
Host smart-2700511d-120b-4cd1-9cdd-b9d104bf32b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81956264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_ec_pwr_on_rst.81956264
Directory /workspace/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_edge_detect.4183134363
Short name T602
Test name
Test status
Simulation time 3051493205 ps
CPU time 6.35 seconds
Started Jul 21 06:39:25 PM PDT 24
Finished Jul 21 06:39:32 PM PDT 24
Peak memory 201576 kb
Host smart-338e9551-5768-4b0a-ae5b-9646c799824c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183134363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ct
rl_edge_detect.4183134363
Directory /workspace/46.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3124504271
Short name T388
Test name
Test status
Simulation time 2611186621 ps
CPU time 7.08 seconds
Started Jul 21 06:39:22 PM PDT 24
Finished Jul 21 06:39:30 PM PDT 24
Peak memory 201516 kb
Host smart-973427be-02af-4d07-a752-7a2d8e2bccc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124504271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.3124504271
Directory /workspace/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2293991860
Short name T703
Test name
Test status
Simulation time 2551000363 ps
CPU time 1.09 seconds
Started Jul 21 06:39:26 PM PDT 24
Finished Jul 21 06:39:28 PM PDT 24
Peak memory 201528 kb
Host smart-a5d5e84f-ea88-459a-9b6b-08705d249af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293991860 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.2293991860
Directory /workspace/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2979927491
Short name T776
Test name
Test status
Simulation time 2242042903 ps
CPU time 3.53 seconds
Started Jul 21 06:39:26 PM PDT 24
Finished Jul 21 06:39:31 PM PDT 24
Peak memory 201544 kb
Host smart-be7e3711-8719-40ca-94e7-3be7478f988c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979927491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.2979927491
Directory /workspace/46.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2842966370
Short name T298
Test name
Test status
Simulation time 2554955531 ps
CPU time 1.66 seconds
Started Jul 21 06:39:24 PM PDT 24
Finished Jul 21 06:39:26 PM PDT 24
Peak memory 201556 kb
Host smart-912c6845-3e3f-49de-a60b-76a809cdcf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842966370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.2842966370
Directory /workspace/46.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_smoke.2823428090
Short name T489
Test name
Test status
Simulation time 2119858459 ps
CPU time 3.54 seconds
Started Jul 21 06:39:24 PM PDT 24
Finished Jul 21 06:39:29 PM PDT 24
Peak memory 201480 kb
Host smart-f798045b-c6dd-46a2-ac8c-c723a8bf06b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823428090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.2823428090
Directory /workspace/46.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all.764744829
Short name T148
Test name
Test status
Simulation time 14552636268 ps
CPU time 19.29 seconds
Started Jul 21 06:39:21 PM PDT 24
Finished Jul 21 06:39:41 PM PDT 24
Peak memory 201492 kb
Host smart-e4ea2260-507f-4049-86cf-dfa02d0740dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764744829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_
stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_st
ress_all.764744829
Directory /workspace/46.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1782505600
Short name T304
Test name
Test status
Simulation time 1342447309225 ps
CPU time 191.94 seconds
Started Jul 21 06:39:24 PM PDT 24
Finished Jul 21 06:42:36 PM PDT 24
Peak memory 218340 kb
Host smart-e880da59-a90c-4996-adac-6406fbb760ed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782505600 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.1782505600
Directory /workspace/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3822691286
Short name T617
Test name
Test status
Simulation time 6975777658 ps
CPU time 7.47 seconds
Started Jul 21 06:39:26 PM PDT 24
Finished Jul 21 06:39:34 PM PDT 24
Peak memory 201516 kb
Host smart-31d340a7-f751-4bff-b694-64fe307fbe7e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822691286 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_
ctrl_ultra_low_pwr.3822691286
Directory /workspace/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_alert_test.2304889523
Short name T664
Test name
Test status
Simulation time 2021583744 ps
CPU time 3.11 seconds
Started Jul 21 06:39:29 PM PDT 24
Finished Jul 21 06:39:32 PM PDT 24
Peak memory 201532 kb
Host smart-82de4a51-d37d-455f-9c8a-98b9c8ee5833
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304889523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_te
st.2304889523
Directory /workspace/47.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.782914665
Short name T559
Test name
Test status
Simulation time 3728336745 ps
CPU time 2.93 seconds
Started Jul 21 06:39:27 PM PDT 24
Finished Jul 21 06:39:31 PM PDT 24
Peak memory 201636 kb
Host smart-b1d6a0fa-5355-4c93-bf7c-973b27eb3923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782914665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.782914665
Directory /workspace/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_combo_detect.2447111383
Short name T257
Test name
Test status
Simulation time 121512496679 ps
CPU time 297.91 seconds
Started Jul 21 06:39:28 PM PDT 24
Finished Jul 21 06:44:26 PM PDT 24
Peak memory 201744 kb
Host smart-7f9978a8-350e-45e0-97b7-511c7f76419f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447111383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_combo_detect.2447111383
Directory /workspace/47.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.218355718
Short name T312
Test name
Test status
Simulation time 5189239262 ps
CPU time 14.33 seconds
Started Jul 21 06:39:29 PM PDT 24
Finished Jul 21 06:39:44 PM PDT 24
Peak memory 201496 kb
Host smart-4fc599de-ed6f-42a5-8332-80c994819972
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218355718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_c
trl_ec_pwr_on_rst.218355718
Directory /workspace/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_edge_detect.4136231566
Short name T205
Test name
Test status
Simulation time 3741795392 ps
CPU time 2.15 seconds
Started Jul 21 06:39:27 PM PDT 24
Finished Jul 21 06:39:30 PM PDT 24
Peak memory 201556 kb
Host smart-888ac69d-e65f-428d-b9c1-3155845bdba6
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136231566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ct
rl_edge_detect.4136231566
Directory /workspace/47.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.906131260
Short name T716
Test name
Test status
Simulation time 2611179516 ps
CPU time 7.85 seconds
Started Jul 21 06:39:31 PM PDT 24
Finished Jul 21 06:39:40 PM PDT 24
Peak memory 201536 kb
Host smart-afedd690-ba2a-4d12-a4b4-9f5bf8fe5ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906131260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.906131260
Directory /workspace/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.823557884
Short name T127
Test name
Test status
Simulation time 2471202156 ps
CPU time 2.21 seconds
Started Jul 21 06:39:26 PM PDT 24
Finished Jul 21 06:39:29 PM PDT 24
Peak memory 201544 kb
Host smart-7a7e4d59-a956-4f9d-8940-e07468ec1502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823557884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.823557884
Directory /workspace/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.4249639397
Short name T53
Test name
Test status
Simulation time 2127465660 ps
CPU time 2 seconds
Started Jul 21 06:39:29 PM PDT 24
Finished Jul 21 06:39:31 PM PDT 24
Peak memory 201408 kb
Host smart-f8d218d9-9fd8-486f-a80d-b32b26afe893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249639397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.4249639397
Directory /workspace/47.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_pin_override_test.210493068
Short name T752
Test name
Test status
Simulation time 2508640889 ps
CPU time 6.99 seconds
Started Jul 21 06:39:27 PM PDT 24
Finished Jul 21 06:39:34 PM PDT 24
Peak memory 201528 kb
Host smart-89cd7d37-50f9-4565-afa3-c8466f1f8645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210493068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.210493068
Directory /workspace/47.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_smoke.33769541
Short name T308
Test name
Test status
Simulation time 2113430245 ps
CPU time 6.03 seconds
Started Jul 21 06:39:25 PM PDT 24
Finished Jul 21 06:39:32 PM PDT 24
Peak memory 201460 kb
Host smart-c8daa7cb-0abe-4b10-88d4-b2aea226de8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33769541 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.33769541
Directory /workspace/47.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all.2002091377
Short name T589
Test name
Test status
Simulation time 651525138213 ps
CPU time 133.23 seconds
Started Jul 21 06:39:25 PM PDT 24
Finished Jul 21 06:41:39 PM PDT 24
Peak memory 201560 kb
Host smart-7420dbd8-bc97-4a7f-8aac-f959feea0835
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002091377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_s
tress_all.2002091377
Directory /workspace/47.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3330598846
Short name T114
Test name
Test status
Simulation time 82143699781 ps
CPU time 53.31 seconds
Started Jul 21 06:39:29 PM PDT 24
Finished Jul 21 06:40:23 PM PDT 24
Peak memory 210092 kb
Host smart-37c14b70-249b-4394-b00b-3567d1778b44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330598846 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.3330598846
Directory /workspace/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2507024516
Short name T21
Test name
Test status
Simulation time 7085684804 ps
CPU time 7.84 seconds
Started Jul 21 06:39:30 PM PDT 24
Finished Jul 21 06:39:38 PM PDT 24
Peak memory 201512 kb
Host smart-4058b847-0b08-4461-b702-7d9e7e0d9ac9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507024516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_
ctrl_ultra_low_pwr.2507024516
Directory /workspace/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_alert_test.1541665378
Short name T669
Test name
Test status
Simulation time 2014207455 ps
CPU time 4.38 seconds
Started Jul 21 06:39:30 PM PDT 24
Finished Jul 21 06:39:35 PM PDT 24
Peak memory 201500 kb
Host smart-9a540ce4-561a-489e-b3d8-19d1afd6d645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541665378 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_te
st.1541665378
Directory /workspace/48.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3054744701
Short name T465
Test name
Test status
Simulation time 3813181246 ps
CPU time 11.12 seconds
Started Jul 21 06:39:28 PM PDT 24
Finished Jul 21 06:39:39 PM PDT 24
Peak memory 201640 kb
Host smart-1989640b-64ee-491a-8732-ea1917c89b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054744701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.3
054744701
Directory /workspace/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect.2381446687
Short name T707
Test name
Test status
Simulation time 211812058146 ps
CPU time 141.6 seconds
Started Jul 21 06:39:28 PM PDT 24
Finished Jul 21 06:41:50 PM PDT 24
Peak memory 201824 kb
Host smart-b7e6e19d-66af-4de2-a254-bf520bf24c0d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381446687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_c
trl_combo_detect.2381446687
Directory /workspace/48.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1203354156
Short name T71
Test name
Test status
Simulation time 80626863559 ps
CPU time 107.19 seconds
Started Jul 21 06:39:28 PM PDT 24
Finished Jul 21 06:41:16 PM PDT 24
Peak memory 201832 kb
Host smart-f6e51fc7-78f4-40b0-97b9-8d9036988f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203354156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_w
ith_pre_cond.1203354156
Directory /workspace/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1131828776
Short name T779
Test name
Test status
Simulation time 4548667924 ps
CPU time 12.03 seconds
Started Jul 21 06:39:27 PM PDT 24
Finished Jul 21 06:39:40 PM PDT 24
Peak memory 201512 kb
Host smart-ff8bc5a7-26be-4eb1-8ddf-db4f4ca0313d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131828776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ec_pwr_on_rst.1131828776
Directory /workspace/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_edge_detect.3571207699
Short name T235
Test name
Test status
Simulation time 184077267356 ps
CPU time 329.4 seconds
Started Jul 21 06:39:29 PM PDT 24
Finished Jul 21 06:45:00 PM PDT 24
Peak memory 201544 kb
Host smart-66526da8-1ec0-4f66-b4e7-358e37fe442f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571207699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ct
rl_edge_detect.3571207699
Directory /workspace/48.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3060517086
Short name T498
Test name
Test status
Simulation time 2610247513 ps
CPU time 7.13 seconds
Started Jul 21 06:39:28 PM PDT 24
Finished Jul 21 06:39:36 PM PDT 24
Peak memory 201440 kb
Host smart-960578ec-0e41-44ab-b248-ed0f044e161e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060517086 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.3060517086
Directory /workspace/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3354650456
Short name T406
Test name
Test status
Simulation time 2472787038 ps
CPU time 3.68 seconds
Started Jul 21 06:39:27 PM PDT 24
Finished Jul 21 06:39:31 PM PDT 24
Peak memory 201492 kb
Host smart-34d0e496-c697-4fc7-9e60-0fdfe9efa020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354650456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.3354650456
Directory /workspace/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3366933349
Short name T558
Test name
Test status
Simulation time 2029557111 ps
CPU time 4.86 seconds
Started Jul 21 06:39:31 PM PDT 24
Finished Jul 21 06:39:36 PM PDT 24
Peak memory 201660 kb
Host smart-24c40449-e528-489e-aaa6-6826dc318362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366933349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.3366933349
Directory /workspace/48.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3817737010
Short name T380
Test name
Test status
Simulation time 2528534018 ps
CPU time 2.44 seconds
Started Jul 21 06:39:27 PM PDT 24
Finished Jul 21 06:39:30 PM PDT 24
Peak memory 201516 kb
Host smart-d0f879bf-58e0-45c2-b589-8fd3278e448a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817737010 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.3817737010
Directory /workspace/48.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_smoke.3977026863
Short name T418
Test name
Test status
Simulation time 2111649333 ps
CPU time 5.91 seconds
Started Jul 21 06:39:26 PM PDT 24
Finished Jul 21 06:39:33 PM PDT 24
Peak memory 201524 kb
Host smart-3ec0a5e6-bcd9-4508-8618-65e31574c0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977026863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3977026863
Directory /workspace/48.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all.3387494757
Short name T552
Test name
Test status
Simulation time 37760127658 ps
CPU time 95.12 seconds
Started Jul 21 06:39:30 PM PDT 24
Finished Jul 21 06:41:05 PM PDT 24
Peak memory 201544 kb
Host smart-8e964cbf-4e4c-4175-a6da-d2e761717893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3387494757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_s
tress_all.3387494757
Directory /workspace/48.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1950754608
Short name T89
Test name
Test status
Simulation time 80063624563 ps
CPU time 95.33 seconds
Started Jul 21 06:39:30 PM PDT 24
Finished Jul 21 06:41:06 PM PDT 24
Peak memory 210392 kb
Host smart-e9244de9-20b3-4310-bc2b-87914ab11389
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950754608 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.1950754608
Directory /workspace/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1278748969
Short name T695
Test name
Test status
Simulation time 96179228448 ps
CPU time 7.69 seconds
Started Jul 21 06:39:29 PM PDT 24
Finished Jul 21 06:39:37 PM PDT 24
Peak memory 201576 kb
Host smart-1859040b-d201-4c08-af96-3bd79c58c127
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278748969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_
ctrl_ultra_low_pwr.1278748969
Directory /workspace/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_alert_test.1795450599
Short name T660
Test name
Test status
Simulation time 2013659301 ps
CPU time 5.71 seconds
Started Jul 21 06:39:38 PM PDT 24
Finished Jul 21 06:39:44 PM PDT 24
Peak memory 201572 kb
Host smart-82c234c8-2647-4d9d-8679-9f4a6fdc5edd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795450599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_te
st.1795450599
Directory /workspace/49.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3770672808
Short name T5
Test name
Test status
Simulation time 3792067481 ps
CPU time 1.74 seconds
Started Jul 21 06:39:38 PM PDT 24
Finished Jul 21 06:39:40 PM PDT 24
Peak memory 201668 kb
Host smart-c7be809b-18b9-45ce-bbcc-2caf41644b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770672808 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.3
770672808
Directory /workspace/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect.897563972
Short name T246
Test name
Test status
Simulation time 195148805759 ps
CPU time 523.45 seconds
Started Jul 21 06:39:37 PM PDT 24
Finished Jul 21 06:48:21 PM PDT 24
Peak memory 201796 kb
Host smart-056dc7aa-41fb-4b3f-b45f-dad11c95cda9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897563972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_combo_detect.897563972
Directory /workspace/49.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1202745592
Short name T93
Test name
Test status
Simulation time 23843875848 ps
CPU time 31.71 seconds
Started Jul 21 06:39:36 PM PDT 24
Finished Jul 21 06:40:08 PM PDT 24
Peak memory 201880 kb
Host smart-3dc0bfd6-f9fa-4902-9880-9597a1722eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202745592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_w
ith_pre_cond.1202745592
Directory /workspace/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.194849968
Short name T444
Test name
Test status
Simulation time 4805625481 ps
CPU time 8.96 seconds
Started Jul 21 06:39:29 PM PDT 24
Finished Jul 21 06:39:39 PM PDT 24
Peak memory 201540 kb
Host smart-4e8534bd-01f8-4d5a-a307-65f49f4e4f30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194849968 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_c
trl_ec_pwr_on_rst.194849968
Directory /workspace/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_edge_detect.1923745114
Short name T157
Test name
Test status
Simulation time 3092187479 ps
CPU time 6.13 seconds
Started Jul 21 06:39:38 PM PDT 24
Finished Jul 21 06:39:44 PM PDT 24
Peak memory 201460 kb
Host smart-b10cad17-a2c5-474e-b2b7-3f1b56dc81b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923745114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ct
rl_edge_detect.1923745114
Directory /workspace/49.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1608890080
Short name T483
Test name
Test status
Simulation time 2609639112 ps
CPU time 7.52 seconds
Started Jul 21 06:39:28 PM PDT 24
Finished Jul 21 06:39:36 PM PDT 24
Peak memory 201568 kb
Host smart-21dae103-99a1-4401-932f-5accd4484603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608890080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.1608890080
Directory /workspace/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4054596470
Short name T66
Test name
Test status
Simulation time 2480471828 ps
CPU time 7.15 seconds
Started Jul 21 06:39:32 PM PDT 24
Finished Jul 21 06:39:39 PM PDT 24
Peak memory 201540 kb
Host smart-fbb710b8-7f59-4efe-94c5-b64a7c72bfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054596470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.4054596470
Directory /workspace/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1002909885
Short name T64
Test name
Test status
Simulation time 2219310568 ps
CPU time 6.25 seconds
Started Jul 21 06:39:29 PM PDT 24
Finished Jul 21 06:39:36 PM PDT 24
Peak memory 201432 kb
Host smart-2a1217af-7ceb-4371-87f2-11f3e60a53ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002909885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.1002909885
Directory /workspace/49.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_pin_override_test.871660164
Short name T640
Test name
Test status
Simulation time 2509938805 ps
CPU time 7.49 seconds
Started Jul 21 06:39:28 PM PDT 24
Finished Jul 21 06:39:36 PM PDT 24
Peak memory 201564 kb
Host smart-5687dea3-be79-48a8-b37c-50f9f41c5118
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871660164 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.871660164
Directory /workspace/49.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_smoke.3351176065
Short name T699
Test name
Test status
Simulation time 2136289038 ps
CPU time 1.94 seconds
Started Jul 21 06:39:28 PM PDT 24
Finished Jul 21 06:39:30 PM PDT 24
Peak memory 200716 kb
Host smart-5fb46dbb-001a-4482-9bec-cdff05528ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351176065 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.3351176065
Directory /workspace/49.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all.1347161050
Short name T223
Test name
Test status
Simulation time 21727187501 ps
CPU time 11.3 seconds
Started Jul 21 06:39:37 PM PDT 24
Finished Jul 21 06:39:49 PM PDT 24
Peak memory 201604 kb
Host smart-a98f8465-4a03-4545-99ea-b28013251877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347161050 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_s
tress_all.1347161050
Directory /workspace/49.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1088985675
Short name T626
Test name
Test status
Simulation time 115206828338 ps
CPU time 140.79 seconds
Started Jul 21 06:39:36 PM PDT 24
Finished Jul 21 06:41:57 PM PDT 24
Peak memory 210276 kb
Host smart-c0430561-11e7-4e70-8b10-1457e37c23e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088985675 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.1088985675
Directory /workspace/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.4149595163
Short name T475
Test name
Test status
Simulation time 4286065418 ps
CPU time 3.59 seconds
Started Jul 21 06:39:40 PM PDT 24
Finished Jul 21 06:39:44 PM PDT 24
Peak memory 201496 kb
Host smart-3b2a94c2-8c54-4f7a-b604-e318e9070009
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149595163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_
ctrl_ultra_low_pwr.4149595163
Directory /workspace/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_alert_test.340819366
Short name T221
Test name
Test status
Simulation time 2029701989 ps
CPU time 1.82 seconds
Started Jul 21 06:37:47 PM PDT 24
Finished Jul 21 06:37:50 PM PDT 24
Peak memory 201512 kb
Host smart-262b9a09-dd11-42cd-9366-f38ccc0626e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340819366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test
.340819366
Directory /workspace/5.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2685307698
Short name T531
Test name
Test status
Simulation time 3310437671 ps
CPU time 2.68 seconds
Started Jul 21 06:37:49 PM PDT 24
Finished Jul 21 06:37:53 PM PDT 24
Peak memory 201636 kb
Host smart-6a6a6bb5-9a56-45d8-a5b2-0da933bb77a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685307698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.2685307698
Directory /workspace/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect.2431502428
Short name T224
Test name
Test status
Simulation time 92425447866 ps
CPU time 225.54 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:41:39 PM PDT 24
Peak memory 201208 kb
Host smart-bd735dbc-8aa0-4110-bb2b-032e058a7139
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431502428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_combo_detect.2431502428
Directory /workspace/5.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1239731192
Short name T637
Test name
Test status
Simulation time 27579264407 ps
CPU time 75.58 seconds
Started Jul 21 06:37:48 PM PDT 24
Finished Jul 21 06:39:04 PM PDT 24
Peak memory 201860 kb
Host smart-cd5aa3c9-619d-4995-b5d9-23999551e774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239731192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_wi
th_pre_cond.1239731192
Directory /workspace/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.671808397
Short name T393
Test name
Test status
Simulation time 2715331252 ps
CPU time 2.32 seconds
Started Jul 21 06:37:48 PM PDT 24
Finished Jul 21 06:37:52 PM PDT 24
Peak memory 201580 kb
Host smart-2f0d1102-2a26-4f96-809b-49cdce122e99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671808397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ct
rl_ec_pwr_on_rst.671808397
Directory /workspace/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_edge_detect.2567021933
Short name T150
Test name
Test status
Simulation time 4211801263 ps
CPU time 2.46 seconds
Started Jul 21 06:37:50 PM PDT 24
Finished Jul 21 06:37:55 PM PDT 24
Peak memory 201536 kb
Host smart-f9192b08-81b3-4796-bdba-f9a4b0865084
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567021933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctr
l_edge_detect.2567021933
Directory /workspace/5.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.275433364
Short name T422
Test name
Test status
Simulation time 2610736070 ps
CPU time 7.47 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:38:01 PM PDT 24
Peak memory 201472 kb
Host smart-e75f7c59-0ce5-48ac-b4a9-1af84e6403ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275433364 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.275433364
Directory /workspace/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.229778988
Short name T690
Test name
Test status
Simulation time 2471229618 ps
CPU time 2.24 seconds
Started Jul 21 06:37:54 PM PDT 24
Finished Jul 21 06:37:58 PM PDT 24
Peak memory 201548 kb
Host smart-7e9c960a-ce1f-4a9d-bb08-d9bd5539df21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229778988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.229778988
Directory /workspace/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.151032235
Short name T183
Test name
Test status
Simulation time 2103686743 ps
CPU time 2 seconds
Started Jul 21 06:37:52 PM PDT 24
Finished Jul 21 06:37:57 PM PDT 24
Peak memory 201476 kb
Host smart-00a9c5c5-060a-4628-ac6f-0ff1b9183d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151032235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.151032235
Directory /workspace/5.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1087534092
Short name T610
Test name
Test status
Simulation time 2522458847 ps
CPU time 2.94 seconds
Started Jul 21 06:37:50 PM PDT 24
Finished Jul 21 06:37:55 PM PDT 24
Peak memory 201556 kb
Host smart-9744e784-da68-4407-91db-18e05c8b046e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087534092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.1087534092
Directory /workspace/5.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_smoke.2201324319
Short name T641
Test name
Test status
Simulation time 2136119261 ps
CPU time 1.86 seconds
Started Jul 21 06:37:54 PM PDT 24
Finished Jul 21 06:37:58 PM PDT 24
Peak memory 201476 kb
Host smart-68db948f-1aaf-4937-bf71-a4973796a064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201324319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.2201324319
Directory /workspace/5.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_stress_all.92481234
Short name T713
Test name
Test status
Simulation time 14272648177 ps
CPU time 9.66 seconds
Started Jul 21 06:37:54 PM PDT 24
Finished Jul 21 06:38:06 PM PDT 24
Peak memory 201544 kb
Host smart-75256b0a-e715-4c56-941c-97d9a9c48842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92481234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stre
ss_all.92481234
Directory /workspace/5.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3154029831
Short name T630
Test name
Test status
Simulation time 3156974640210 ps
CPU time 256.89 seconds
Started Jul 21 06:37:47 PM PDT 24
Finished Jul 21 06:42:04 PM PDT 24
Peak memory 201532 kb
Host smart-20380cd2-2a2f-4f06-ad18-c78fab4c881a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154029831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_c
trl_ultra_low_pwr.3154029831
Directory /workspace/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2512260058
Short name T618
Test name
Test status
Simulation time 47044717233 ps
CPU time 122.18 seconds
Started Jul 21 06:39:37 PM PDT 24
Finished Jul 21 06:41:40 PM PDT 24
Peak memory 201832 kb
Host smart-ba96dd07-c31b-494d-b00e-7253dc0848d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512260058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_w
ith_pre_cond.2512260058
Directory /workspace/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2647587570
Short name T477
Test name
Test status
Simulation time 78562536623 ps
CPU time 15.6 seconds
Started Jul 21 06:39:36 PM PDT 24
Finished Jul 21 06:39:52 PM PDT 24
Peak memory 201828 kb
Host smart-099787a3-0e4f-4043-b855-7d3e7c3c110e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647587570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_w
ith_pre_cond.2647587570
Directory /workspace/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.941941057
Short name T503
Test name
Test status
Simulation time 36732915151 ps
CPU time 88.56 seconds
Started Jul 21 06:39:38 PM PDT 24
Finished Jul 21 06:41:07 PM PDT 24
Peak memory 201840 kb
Host smart-e029f1d5-7f94-4deb-b3b7-13aa0df960e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941941057 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_wi
th_pre_cond.941941057
Directory /workspace/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2617462890
Short name T349
Test name
Test status
Simulation time 57533543055 ps
CPU time 37.62 seconds
Started Jul 21 06:39:37 PM PDT 24
Finished Jul 21 06:40:15 PM PDT 24
Peak memory 201872 kb
Host smart-82f8ee92-ecbb-442a-a315-ec0377220673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617462890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_w
ith_pre_cond.2617462890
Directory /workspace/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.852435372
Short name T250
Test name
Test status
Simulation time 75708121041 ps
CPU time 195.42 seconds
Started Jul 21 06:39:44 PM PDT 24
Finished Jul 21 06:43:01 PM PDT 24
Peak memory 201864 kb
Host smart-c2d8bd11-a6b3-425e-a2b5-fb5829a04683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852435372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_wi
th_pre_cond.852435372
Directory /workspace/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.449433734
Short name T755
Test name
Test status
Simulation time 86083241844 ps
CPU time 103.77 seconds
Started Jul 21 06:39:34 PM PDT 24
Finished Jul 21 06:41:18 PM PDT 24
Peak memory 201812 kb
Host smart-1c648cd1-f27a-4077-96a6-a4378555d13f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449433734 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_wi
th_pre_cond.449433734
Directory /workspace/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3781812531
Short name T613
Test name
Test status
Simulation time 24862227597 ps
CPU time 14.34 seconds
Started Jul 21 06:39:33 PM PDT 24
Finished Jul 21 06:39:48 PM PDT 24
Peak memory 201896 kb
Host smart-1a80c834-aa91-41c2-b781-dfb257d0d80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781812531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_w
ith_pre_cond.3781812531
Directory /workspace/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.833943701
Short name T219
Test name
Test status
Simulation time 109055962763 ps
CPU time 293.35 seconds
Started Jul 21 06:39:34 PM PDT 24
Finished Jul 21 06:44:28 PM PDT 24
Peak memory 201892 kb
Host smart-abe2ff5e-a22d-494e-ad7a-9de03114317c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833943701 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_wi
th_pre_cond.833943701
Directory /workspace/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_alert_test.230948426
Short name T549
Test name
Test status
Simulation time 2016883279 ps
CPU time 5.28 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:37:59 PM PDT 24
Peak memory 201464 kb
Host smart-fd91b015-ca4c-4479-aba0-5812356cc12b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230948426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test
.230948426
Directory /workspace/6.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.144146219
Short name T408
Test name
Test status
Simulation time 3722634630 ps
CPU time 4.01 seconds
Started Jul 21 06:37:48 PM PDT 24
Finished Jul 21 06:37:53 PM PDT 24
Peak memory 201672 kb
Host smart-cc46a0d3-6cd5-4da7-a5f3-0dff9f7412be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144146219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.144146219
Directory /workspace/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect.3403581466
Short name T59
Test name
Test status
Simulation time 148678076663 ps
CPU time 189.02 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:41:02 PM PDT 24
Peak memory 201848 kb
Host smart-08d659df-253e-46c9-b90f-330963ed33f1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403581466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_combo_detect.3403581466
Directory /workspace/6.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1305455711
Short name T370
Test name
Test status
Simulation time 252414460028 ps
CPU time 329.4 seconds
Started Jul 21 06:37:50 PM PDT 24
Finished Jul 21 06:43:20 PM PDT 24
Peak memory 201788 kb
Host smart-3d52f3fc-c66e-4ff8-8c68-dae9766497f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305455711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_wi
th_pre_cond.1305455711
Directory /workspace/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1872131261
Short name T416
Test name
Test status
Simulation time 2806619569 ps
CPU time 1 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:37:55 PM PDT 24
Peak memory 201520 kb
Host smart-ee61e5f2-e572-416f-a047-f07857739746
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872131261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_c
trl_ec_pwr_on_rst.1872131261
Directory /workspace/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1414354090
Short name T12
Test name
Test status
Simulation time 4760961085 ps
CPU time 10.18 seconds
Started Jul 21 06:37:55 PM PDT 24
Finished Jul 21 06:38:07 PM PDT 24
Peak memory 201592 kb
Host smart-34c2a84b-2016-4001-9ea4-f2f7666edc15
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414354090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctr
l_edge_detect.1414354090
Directory /workspace/6.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1110026944
Short name T130
Test name
Test status
Simulation time 2611158024 ps
CPU time 7.29 seconds
Started Jul 21 06:37:54 PM PDT 24
Finished Jul 21 06:38:03 PM PDT 24
Peak memory 201540 kb
Host smart-008c74e5-a3b1-4f33-916d-0705e4c57426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110026944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.1110026944
Directory /workspace/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.735569695
Short name T582
Test name
Test status
Simulation time 2471122827 ps
CPU time 6.98 seconds
Started Jul 21 06:37:50 PM PDT 24
Finished Jul 21 06:37:59 PM PDT 24
Peak memory 201560 kb
Host smart-6cd33c0a-670f-41a4-b26c-e0419e10bfe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735569695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.735569695
Directory /workspace/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_access_test.530269338
Short name T717
Test name
Test status
Simulation time 2049929814 ps
CPU time 5.55 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:37:59 PM PDT 24
Peak memory 201268 kb
Host smart-c45685eb-99de-47ee-9a02-d2da4d2cffb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530269338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.530269338
Directory /workspace/6.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.538960413
Short name T174
Test name
Test status
Simulation time 2644899645 ps
CPU time 1.15 seconds
Started Jul 21 06:37:47 PM PDT 24
Finished Jul 21 06:37:49 PM PDT 24
Peak memory 201500 kb
Host smart-af8d660e-f728-4c28-ab64-ade56ec11657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538960413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.538960413
Directory /workspace/6.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_smoke.1327067275
Short name T464
Test name
Test status
Simulation time 2108404581 ps
CPU time 5.93 seconds
Started Jul 21 06:37:55 PM PDT 24
Finished Jul 21 06:38:02 PM PDT 24
Peak memory 201464 kb
Host smart-a373285d-59ad-406d-8fbd-ddaba4302e6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327067275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.1327067275
Directory /workspace/6.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_stress_all.2514462102
Short name T138
Test name
Test status
Simulation time 11796234338 ps
CPU time 8.45 seconds
Started Jul 21 06:37:54 PM PDT 24
Finished Jul 21 06:38:04 PM PDT 24
Peak memory 201540 kb
Host smart-5e9182af-5f69-483f-8445-71567f28aa18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514462102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_st
ress_all.2514462102
Directory /workspace/6.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.262733513
Short name T376
Test name
Test status
Simulation time 248484580401 ps
CPU time 26.61 seconds
Started Jul 21 06:37:52 PM PDT 24
Finished Jul 21 06:38:21 PM PDT 24
Peak memory 201564 kb
Host smart-2a5b6035-638b-4ff2-922e-235cd86c66db
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262733513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ct
rl_ultra_low_pwr.262733513
Directory /workspace/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.302562988
Short name T351
Test name
Test status
Simulation time 56035804323 ps
CPU time 140.27 seconds
Started Jul 21 06:39:34 PM PDT 24
Finished Jul 21 06:41:55 PM PDT 24
Peak memory 201904 kb
Host smart-00b68b33-c02c-4fab-915b-3b4e656e9388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302562988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_wi
th_pre_cond.302562988
Directory /workspace/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3921754972
Short name T94
Test name
Test status
Simulation time 23589303001 ps
CPU time 31.9 seconds
Started Jul 21 06:39:34 PM PDT 24
Finished Jul 21 06:40:06 PM PDT 24
Peak memory 201848 kb
Host smart-493fd907-49d8-4ee6-84ce-b3055c976b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921754972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_w
ith_pre_cond.3921754972
Directory /workspace/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1621794043
Short name T359
Test name
Test status
Simulation time 141229631994 ps
CPU time 362.14 seconds
Started Jul 21 06:39:36 PM PDT 24
Finished Jul 21 06:45:38 PM PDT 24
Peak memory 201852 kb
Host smart-88ca30d2-a4e7-4c76-81f1-de037ab2038e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621794043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_w
ith_pre_cond.1621794043
Directory /workspace/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.707516753
Short name T240
Test name
Test status
Simulation time 87721135400 ps
CPU time 117.52 seconds
Started Jul 21 06:39:35 PM PDT 24
Finished Jul 21 06:41:33 PM PDT 24
Peak memory 201884 kb
Host smart-44c48546-a14d-4884-9d86-4e4b4c42ce5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707516753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_wi
th_pre_cond.707516753
Directory /workspace/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3612738288
Short name T348
Test name
Test status
Simulation time 136606269469 ps
CPU time 100.8 seconds
Started Jul 21 06:39:38 PM PDT 24
Finished Jul 21 06:41:19 PM PDT 24
Peak memory 201944 kb
Host smart-b985938a-1e1e-4a9a-93e5-ce211b2bddda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612738288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_w
ith_pre_cond.3612738288
Directory /workspace/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1057327980
Short name T338
Test name
Test status
Simulation time 42072976583 ps
CPU time 53.88 seconds
Started Jul 21 06:39:36 PM PDT 24
Finished Jul 21 06:40:31 PM PDT 24
Peak memory 201860 kb
Host smart-53106af5-24f2-4d61-905e-8421e6167035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057327980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_w
ith_pre_cond.1057327980
Directory /workspace/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_alert_test.415592330
Short name T111
Test name
Test status
Simulation time 2009897287 ps
CPU time 5.78 seconds
Started Jul 21 06:37:57 PM PDT 24
Finished Jul 21 06:38:04 PM PDT 24
Peak memory 201544 kb
Host smart-83f2c586-326f-4d9e-bfb6-3396ef7b1aba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415592330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test
.415592330
Directory /workspace/7.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.303052837
Short name T730
Test name
Test status
Simulation time 3450585194 ps
CPU time 2.76 seconds
Started Jul 21 06:37:55 PM PDT 24
Finished Jul 21 06:38:00 PM PDT 24
Peak memory 201600 kb
Host smart-ab44991a-c77e-4b23-a79b-465d8b7b601f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303052837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.303052837
Directory /workspace/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect.667164413
Short name T646
Test name
Test status
Simulation time 158692961018 ps
CPU time 412.24 seconds
Started Jul 21 06:37:58 PM PDT 24
Finished Jul 21 06:44:51 PM PDT 24
Peak memory 201796 kb
Host smart-6a1f669b-ad33-498b-ae35-8fda32f507b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667164413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_combo_detect.667164413
Directory /workspace/7.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.945947474
Short name T634
Test name
Test status
Simulation time 50317641375 ps
CPU time 128.2 seconds
Started Jul 21 06:37:55 PM PDT 24
Finished Jul 21 06:40:05 PM PDT 24
Peak memory 201928 kb
Host smart-cd801d17-9b5b-494f-b9c5-254fe9b1cace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945947474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_wit
h_pre_cond.945947474
Directory /workspace/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2968016392
Short name T706
Test name
Test status
Simulation time 4369306153 ps
CPU time 5.03 seconds
Started Jul 21 06:37:55 PM PDT 24
Finished Jul 21 06:38:02 PM PDT 24
Peak memory 201548 kb
Host smart-00f242b7-d999-4fa2-a271-563a8ba9eee1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968016392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ec_pwr_on_rst.2968016392
Directory /workspace/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_edge_detect.2150364279
Short name T136
Test name
Test status
Simulation time 3202185579 ps
CPU time 2.71 seconds
Started Jul 21 06:37:53 PM PDT 24
Finished Jul 21 06:37:58 PM PDT 24
Peak memory 201492 kb
Host smart-f7870776-8018-409a-b3ab-14c82ce72637
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150364279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctr
l_edge_detect.2150364279
Directory /workspace/7.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.413220321
Short name T609
Test name
Test status
Simulation time 2626174897 ps
CPU time 2.38 seconds
Started Jul 21 06:37:50 PM PDT 24
Finished Jul 21 06:37:55 PM PDT 24
Peak memory 201556 kb
Host smart-b65bf0c1-e0e2-4595-99f9-94f46b9e43a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=413220321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.413220321
Directory /workspace/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2698429241
Short name T22
Test name
Test status
Simulation time 2469966484 ps
CPU time 6.79 seconds
Started Jul 21 06:37:51 PM PDT 24
Finished Jul 21 06:38:01 PM PDT 24
Peak memory 201544 kb
Host smart-b4f38bd1-b6c9-4b38-8048-4516f32adc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698429241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.2698429241
Directory /workspace/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1516359361
Short name T473
Test name
Test status
Simulation time 2077397522 ps
CPU time 3.2 seconds
Started Jul 21 06:37:47 PM PDT 24
Finished Jul 21 06:37:51 PM PDT 24
Peak memory 201456 kb
Host smart-a6b392f6-a0c9-4e94-b533-821e3901b472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516359361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1516359361
Directory /workspace/7.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_pin_override_test.4002922622
Short name T764
Test name
Test status
Simulation time 2587845571 ps
CPU time 1.18 seconds
Started Jul 21 06:37:52 PM PDT 24
Finished Jul 21 06:37:55 PM PDT 24
Peak memory 201544 kb
Host smart-b1c28854-272f-4755-b9a8-ac86d73ec021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002922622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.4002922622
Directory /workspace/7.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_smoke.3877330929
Short name T555
Test name
Test status
Simulation time 2148233963 ps
CPU time 1.33 seconds
Started Jul 21 06:37:54 PM PDT 24
Finished Jul 21 06:37:58 PM PDT 24
Peak memory 201356 kb
Host smart-ef4df1e5-dc2b-45aa-bc7c-af896edd2621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877330929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.3877330929
Directory /workspace/7.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all.1581765197
Short name T727
Test name
Test status
Simulation time 8087717363 ps
CPU time 5.58 seconds
Started Jul 21 06:37:53 PM PDT 24
Finished Jul 21 06:38:01 PM PDT 24
Peak memory 201548 kb
Host smart-1c3c7593-1668-45db-938f-1fd658784c97
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581765197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_st
ress_all.1581765197
Directory /workspace/7.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2493899054
Short name T293
Test name
Test status
Simulation time 32960739651 ps
CPU time 41.66 seconds
Started Jul 21 06:37:53 PM PDT 24
Finished Jul 21 06:38:37 PM PDT 24
Peak memory 209924 kb
Host smart-d436036e-b6f0-4c1f-912d-4f85eaa280df
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493899054 -assert
nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.2493899054
Directory /workspace/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1328251896
Short name T762
Test name
Test status
Simulation time 5014341799 ps
CPU time 7.29 seconds
Started Jul 21 06:37:54 PM PDT 24
Finished Jul 21 06:38:04 PM PDT 24
Peak memory 201532 kb
Host smart-d20da639-71ba-4971-86cc-bad8782abce2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328251896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_c
trl_ultra_low_pwr.1328251896
Directory /workspace/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.4283860074
Short name T576
Test name
Test status
Simulation time 39469086825 ps
CPU time 65.37 seconds
Started Jul 21 06:39:37 PM PDT 24
Finished Jul 21 06:40:43 PM PDT 24
Peak memory 201788 kb
Host smart-a3928d13-3c0d-4c57-a95a-977829ed5292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4283860074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_w
ith_pre_cond.4283860074
Directory /workspace/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3875653134
Short name T368
Test name
Test status
Simulation time 146623705385 ps
CPU time 85.44 seconds
Started Jul 21 06:39:37 PM PDT 24
Finished Jul 21 06:41:03 PM PDT 24
Peak memory 201884 kb
Host smart-c40b096c-e9b9-4d32-8972-df1f5c3a252c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875653134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_w
ith_pre_cond.3875653134
Directory /workspace/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2658254911
Short name T220
Test name
Test status
Simulation time 31721236051 ps
CPU time 8.71 seconds
Started Jul 21 06:39:35 PM PDT 24
Finished Jul 21 06:39:44 PM PDT 24
Peak memory 201780 kb
Host smart-5a2cd78b-656a-4bd2-977d-5ceb7774b45e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658254911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_w
ith_pre_cond.2658254911
Directory /workspace/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2260877122
Short name T785
Test name
Test status
Simulation time 31966692964 ps
CPU time 22.17 seconds
Started Jul 21 06:39:33 PM PDT 24
Finished Jul 21 06:39:55 PM PDT 24
Peak memory 201888 kb
Host smart-70d82ec2-e0eb-49de-85af-f3e5d409e04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260877122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_w
ith_pre_cond.2260877122
Directory /workspace/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.415030829
Short name T353
Test name
Test status
Simulation time 136465693530 ps
CPU time 362.83 seconds
Started Jul 21 06:39:35 PM PDT 24
Finished Jul 21 06:45:38 PM PDT 24
Peak memory 201804 kb
Host smart-43ea823f-db82-49cf-ad29-f2fe33b94cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415030829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_wi
th_pre_cond.415030829
Directory /workspace/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1341466547
Short name T786
Test name
Test status
Simulation time 26083024809 ps
CPU time 65.02 seconds
Started Jul 21 06:39:36 PM PDT 24
Finished Jul 21 06:40:42 PM PDT 24
Peak memory 201928 kb
Host smart-8c848fd0-ae46-40cf-9e22-aae29c451ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341466547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_w
ith_pre_cond.1341466547
Directory /workspace/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_alert_test.2551137782
Short name T132
Test name
Test status
Simulation time 2035895489 ps
CPU time 1.61 seconds
Started Jul 21 06:37:54 PM PDT 24
Finished Jul 21 06:37:58 PM PDT 24
Peak memory 201572 kb
Host smart-3f5037e6-db8e-472f-8821-c8169d5694fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551137782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_tes
t.2551137782
Directory /workspace/8.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2290795113
Short name T578
Test name
Test status
Simulation time 3550011899 ps
CPU time 1.41 seconds
Started Jul 21 06:37:52 PM PDT 24
Finished Jul 21 06:37:56 PM PDT 24
Peak memory 201596 kb
Host smart-849101be-524e-4027-a128-8f2db6b8bdb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290795113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.2290795113
Directory /workspace/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_combo_detect.2861738960
Short name T34
Test name
Test status
Simulation time 31933318394 ps
CPU time 41.55 seconds
Started Jul 21 06:37:52 PM PDT 24
Finished Jul 21 06:38:36 PM PDT 24
Peak memory 201800 kb
Host smart-a734e274-3356-4ba8-a09d-788deec1b61a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861738960 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ct
rl_combo_detect.2861738960
Directory /workspace/8.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2205755735
Short name T60
Test name
Test status
Simulation time 5055680590 ps
CPU time 7.34 seconds
Started Jul 21 06:37:58 PM PDT 24
Finished Jul 21 06:38:06 PM PDT 24
Peak memory 201536 kb
Host smart-56344ee4-a1cc-4955-a08b-024ba57e9f3e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205755735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ec_pwr_on_rst.2205755735
Directory /workspace/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_edge_detect.1636726984
Short name T145
Test name
Test status
Simulation time 4212057979 ps
CPU time 2.21 seconds
Started Jul 21 06:37:55 PM PDT 24
Finished Jul 21 06:37:59 PM PDT 24
Peak memory 201532 kb
Host smart-b1ec0a74-6f0d-48c8-9569-1baaad16259e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636726984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctr
l_edge_detect.1636726984
Directory /workspace/8.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2909982436
Short name T135
Test name
Test status
Simulation time 2619782036 ps
CPU time 3.96 seconds
Started Jul 21 06:37:53 PM PDT 24
Finished Jul 21 06:37:59 PM PDT 24
Peak memory 201540 kb
Host smart-18688ed4-984e-4463-ba6c-2553f1b2bf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909982436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.2909982436
Directory /workspace/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2896057446
Short name T499
Test name
Test status
Simulation time 2476833719 ps
CPU time 7.3 seconds
Started Jul 21 06:37:56 PM PDT 24
Finished Jul 21 06:38:04 PM PDT 24
Peak memory 201556 kb
Host smart-b29e86e2-2dec-4df6-8dcd-014cfddc6d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896057446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.2896057446
Directory /workspace/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1866746544
Short name T683
Test name
Test status
Simulation time 2048733087 ps
CPU time 5.56 seconds
Started Jul 21 06:37:52 PM PDT 24
Finished Jul 21 06:38:00 PM PDT 24
Peak memory 201448 kb
Host smart-4771d5f0-f7ba-4418-ba88-73dd3057ab19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866746544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.1866746544
Directory /workspace/8.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2071383747
Short name T540
Test name
Test status
Simulation time 2524926540 ps
CPU time 2.35 seconds
Started Jul 21 06:37:54 PM PDT 24
Finished Jul 21 06:37:58 PM PDT 24
Peak memory 201492 kb
Host smart-24845fa9-f897-4b4d-bd89-24266bfc603a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071383747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.2071383747
Directory /workspace/8.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_smoke.2838727417
Short name T407
Test name
Test status
Simulation time 2126535602 ps
CPU time 2.07 seconds
Started Jul 21 06:37:58 PM PDT 24
Finished Jul 21 06:38:01 PM PDT 24
Peak memory 201468 kb
Host smart-d4f111e7-8c1f-4abc-856a-205c7bf1e3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838727417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.2838727417
Directory /workspace/8.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.751057269
Short name T144
Test name
Test status
Simulation time 106285412543 ps
CPU time 65.54 seconds
Started Jul 21 06:37:54 PM PDT 24
Finished Jul 21 06:39:01 PM PDT 24
Peak memory 210220 kb
Host smart-8b3e85d8-03eb-4045-99f4-7b28f46c5062
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751057269 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.751057269
Directory /workspace/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3804457782
Short name T505
Test name
Test status
Simulation time 4834176528 ps
CPU time 2.01 seconds
Started Jul 21 06:37:58 PM PDT 24
Finished Jul 21 06:38:00 PM PDT 24
Peak memory 201544 kb
Host smart-541ab0ce-fbde-4fbd-a5bd-b2e891ed5761
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804457782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_c
trl_ultra_low_pwr.3804457782
Directory /workspace/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1173804710
Short name T656
Test name
Test status
Simulation time 27833460168 ps
CPU time 74.88 seconds
Started Jul 21 06:39:35 PM PDT 24
Finished Jul 21 06:40:50 PM PDT 24
Peak memory 201832 kb
Host smart-b6ac6b75-ce84-41d1-bf00-3077a63cb5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173804710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_w
ith_pre_cond.1173804710
Directory /workspace/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.595703720
Short name T119
Test name
Test status
Simulation time 27831261794 ps
CPU time 67.31 seconds
Started Jul 21 06:39:45 PM PDT 24
Finished Jul 21 06:40:54 PM PDT 24
Peak memory 202040 kb
Host smart-ca3139e6-b8f1-429e-8a11-3bfc08b9aa13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595703720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_wi
th_pre_cond.595703720
Directory /workspace/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1481659442
Short name T355
Test name
Test status
Simulation time 88650694925 ps
CPU time 109.6 seconds
Started Jul 21 06:39:43 PM PDT 24
Finished Jul 21 06:41:34 PM PDT 24
Peak memory 201780 kb
Host smart-5ea2621b-91e4-45c8-8adb-241b597c499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481659442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_w
ith_pre_cond.1481659442
Directory /workspace/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.744474891
Short name T766
Test name
Test status
Simulation time 32191222366 ps
CPU time 41.74 seconds
Started Jul 21 06:39:40 PM PDT 24
Finished Jul 21 06:40:23 PM PDT 24
Peak memory 201836 kb
Host smart-4143ce97-7c2c-4cf3-b184-55ece631dd73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744474891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_wi
th_pre_cond.744474891
Directory /workspace/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1899236892
Short name T688
Test name
Test status
Simulation time 43781900182 ps
CPU time 61.36 seconds
Started Jul 21 06:39:42 PM PDT 24
Finished Jul 21 06:40:44 PM PDT 24
Peak memory 201860 kb
Host smart-9560433d-f216-4378-bfe0-6ed0da3541c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899236892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_w
ith_pre_cond.1899236892
Directory /workspace/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1406009508
Short name T92
Test name
Test status
Simulation time 24832557562 ps
CPU time 66.01 seconds
Started Jul 21 06:39:41 PM PDT 24
Finished Jul 21 06:40:47 PM PDT 24
Peak memory 201888 kb
Host smart-75e6be90-2a50-42bf-b6e1-303b63dd4575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406009508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_w
ith_pre_cond.1406009508
Directory /workspace/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.4153402258
Short name T635
Test name
Test status
Simulation time 26586227945 ps
CPU time 33.66 seconds
Started Jul 21 06:39:42 PM PDT 24
Finished Jul 21 06:40:16 PM PDT 24
Peak memory 201880 kb
Host smart-408d1781-85db-49d5-9501-f2decb68816b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153402258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_w
ith_pre_cond.4153402258
Directory /workspace/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3606198931
Short name T11
Test name
Test status
Simulation time 131285072294 ps
CPU time 354.45 seconds
Started Jul 21 06:39:42 PM PDT 24
Finished Jul 21 06:45:37 PM PDT 24
Peak memory 201944 kb
Host smart-6c3d5173-48f9-4886-81d1-d4a068512701
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606198931 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_w
ith_pre_cond.3606198931
Directory /workspace/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_alert_test.3737210203
Short name T599
Test name
Test status
Simulation time 2013855585 ps
CPU time 5.78 seconds
Started Jul 21 06:37:56 PM PDT 24
Finished Jul 21 06:38:03 PM PDT 24
Peak memory 201568 kb
Host smart-def86918-7018-46d3-b758-9cd69de4d910
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737210203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_tes
t.3737210203
Directory /workspace/9.sysrst_ctrl_alert_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.4127232406
Short name T787
Test name
Test status
Simulation time 2801252609 ps
CPU time 7.92 seconds
Started Jul 21 06:37:56 PM PDT 24
Finished Jul 21 06:38:06 PM PDT 24
Peak memory 201624 kb
Host smart-10831d3d-b13b-46bd-8c4c-9437fecd287e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127232406 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.4127232406
Directory /workspace/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3159782008
Short name T334
Test name
Test status
Simulation time 150146093160 ps
CPU time 353.1 seconds
Started Jul 21 06:37:55 PM PDT 24
Finished Jul 21 06:43:50 PM PDT 24
Peak memory 201804 kb
Host smart-98871ea3-79ba-45e6-87c9-2cd4b4670296
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159782008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_combo_detect.3159782008
Directory /workspace/9.sysrst_ctrl_combo_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3693092611
Short name T694
Test name
Test status
Simulation time 25853282398 ps
CPU time 17.57 seconds
Started Jul 21 06:37:52 PM PDT 24
Finished Jul 21 06:38:12 PM PDT 24
Peak memory 201900 kb
Host smart-d6523a23-c313-4509-a377-ed5837476133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693092611 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_wi
th_pre_cond.3693092611
Directory /workspace/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.148692302
Short name T390
Test name
Test status
Simulation time 4087850466 ps
CPU time 5.91 seconds
Started Jul 21 06:37:53 PM PDT 24
Finished Jul 21 06:38:01 PM PDT 24
Peak memory 201552 kb
Host smart-12e9c330-a512-4601-8c14-13853fe9acfe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148692302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ct
rl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ct
rl_ec_pwr_on_rst.148692302
Directory /workspace/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3339866972
Short name T423
Test name
Test status
Simulation time 3001947687 ps
CPU time 2.23 seconds
Started Jul 21 06:37:58 PM PDT 24
Finished Jul 21 06:38:01 PM PDT 24
Peak memory 201544 kb
Host smart-a3d1a4ba-bec1-4718-b995-9ecd5d5b0dea
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3339866972 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_c
trl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_edge_detect.3339866972
Directory /workspace/9.sysrst_ctrl_edge_detect/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3509993954
Short name T676
Test name
Test status
Simulation time 2614956662 ps
CPU time 4.19 seconds
Started Jul 21 06:37:58 PM PDT 24
Finished Jul 21 06:38:03 PM PDT 24
Peak memory 201544 kb
Host smart-b211aa3d-a9a4-4fd0-941f-903e0c33721c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509993954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.3509993954
Directory /workspace/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.978833843
Short name T481
Test name
Test status
Simulation time 2461556281 ps
CPU time 6.73 seconds
Started Jul 21 06:37:55 PM PDT 24
Finished Jul 21 06:38:03 PM PDT 24
Peak memory 201496 kb
Host smart-7183a483-42f8-4073-bdcc-e1b6bbda168a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978833843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.978833843
Directory /workspace/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_access_test.331059592
Short name T702
Test name
Test status
Simulation time 2109808980 ps
CPU time 1.78 seconds
Started Jul 21 06:37:52 PM PDT 24
Finished Jul 21 06:37:57 PM PDT 24
Peak memory 201436 kb
Host smart-43bec14e-6541-4f13-89c8-acfb90e3cd3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331059592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.331059592
Directory /workspace/9.sysrst_ctrl_pin_access_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2801431100
Short name T172
Test name
Test status
Simulation time 2530081685 ps
CPU time 2.3 seconds
Started Jul 21 06:37:58 PM PDT 24
Finished Jul 21 06:38:01 PM PDT 24
Peak memory 201476 kb
Host smart-baa56bb8-207b-43d4-8112-76e53a8cafb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801431100 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.2801431100
Directory /workspace/9.sysrst_ctrl_pin_override_test/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_smoke.3130314706
Short name T494
Test name
Test status
Simulation time 2115098389 ps
CPU time 3.38 seconds
Started Jul 21 06:37:56 PM PDT 24
Finished Jul 21 06:38:00 PM PDT 24
Peak memory 201612 kb
Host smart-1b8037dd-47c8-4990-bb55-3ea5c567a119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130314706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.3130314706
Directory /workspace/9.sysrst_ctrl_smoke/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all.1047577154
Short name T173
Test name
Test status
Simulation time 14829547689 ps
CPU time 38.76 seconds
Started Jul 21 06:37:56 PM PDT 24
Finished Jul 21 06:38:36 PM PDT 24
Peak memory 201608 kb
Host smart-35280bd5-5a22-4cef-afc0-29691e65e495
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047577154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl
_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_st
ress_all.1047577154
Directory /workspace/9.sysrst_ctrl_stress_all/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.112737792
Short name T291
Test name
Test status
Simulation time 18866586775 ps
CPU time 46.67 seconds
Started Jul 21 06:37:55 PM PDT 24
Finished Jul 21 06:38:43 PM PDT 24
Peak memory 210136 kb
Host smart-de130165-94a4-4cfc-af9e-b91bd8634ca9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112737792 -assert n
opostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.112737792
Directory /workspace/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.36233969
Short name T62
Test name
Test status
Simulation time 12618790446 ps
CPU time 2.15 seconds
Started Jul 21 06:37:58 PM PDT 24
Finished Jul 21 06:38:01 PM PDT 24
Peak memory 201560 kb
Host smart-3f9773b5-5815-4a48-9b52-7e5c1ff08a25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36233969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctr
l_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctr
l_ultra_low_pwr.36233969
Directory /workspace/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3834896710
Short name T25
Test name
Test status
Simulation time 25605219564 ps
CPU time 16.72 seconds
Started Jul 21 06:39:41 PM PDT 24
Finished Jul 21 06:39:58 PM PDT 24
Peak memory 201912 kb
Host smart-d4abf200-7c90-45b9-84a2-9c0445add42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834896710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_w
ith_pre_cond.3834896710
Directory /workspace/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2652894971
Short name T352
Test name
Test status
Simulation time 61152999545 ps
CPU time 15.72 seconds
Started Jul 21 06:39:40 PM PDT 24
Finished Jul 21 06:39:56 PM PDT 24
Peak memory 201880 kb
Host smart-2fb781eb-652e-4a5c-aed7-52ffc3776c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652894971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_w
ith_pre_cond.2652894971
Directory /workspace/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.177268171
Short name T661
Test name
Test status
Simulation time 22616100828 ps
CPU time 12.49 seconds
Started Jul 21 06:39:49 PM PDT 24
Finished Jul 21 06:40:05 PM PDT 24
Peak memory 201880 kb
Host smart-b9ad61c5-ce61-4107-a86d-6806e7832ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177268171 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_wi
th_pre_cond.177268171
Directory /workspace/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.4285525116
Short name T644
Test name
Test status
Simulation time 114012192812 ps
CPU time 33.76 seconds
Started Jul 21 06:39:39 PM PDT 24
Finished Jul 21 06:40:14 PM PDT 24
Peak memory 201868 kb
Host smart-2a8b9920-d57e-43d7-9e2f-b57e81455a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285525116 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_w
ith_pre_cond.4285525116
Directory /workspace/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2741840645
Short name T347
Test name
Test status
Simulation time 78693271452 ps
CPU time 54.16 seconds
Started Jul 21 06:39:40 PM PDT 24
Finished Jul 21 06:40:34 PM PDT 24
Peak memory 201860 kb
Host smart-0f56c6c1-bf2a-410c-91e8-1eafff5f177d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741840645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_w
ith_pre_cond.2741840645
Directory /workspace/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1137784994
Short name T537
Test name
Test status
Simulation time 73091415722 ps
CPU time 48.77 seconds
Started Jul 21 06:39:41 PM PDT 24
Finished Jul 21 06:40:31 PM PDT 24
Peak memory 201828 kb
Host smart-82c40779-133e-44d6-b5a0-546c2fc2f211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137784994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_w
ith_pre_cond.1137784994
Directory /workspace/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.16995723
Short name T367
Test name
Test status
Simulation time 20617622884 ps
CPU time 8.35 seconds
Started Jul 21 06:39:40 PM PDT 24
Finished Jul 21 06:39:49 PM PDT 24
Peak memory 201880 kb
Host smart-0f46e480-1024-4894-a67c-cdadcc09a3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16995723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_wit
h_pre_cond.16995723
Directory /workspace/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
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