Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.92 98.81 96.71 100.00 96.15 98.30 99.42 89.03


Total tests in report: 915
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
53.93 53.93 76.41 76.41 62.59 62.59 65.53 65.53 11.54 11.54 77.67 77.67 63.49 63.49 20.26 20.26 /workspace/coverage/default/8.sysrst_ctrl_stress_all.380724280
75.75 21.82 94.55 18.14 85.16 22.57 72.15 6.62 71.15 59.62 94.23 16.56 90.08 26.59 22.92 2.67 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2854437610
81.52 5.77 95.52 0.97 88.30 3.13 92.24 20.09 76.92 5.77 95.08 0.85 92.20 2.12 30.41 7.49 /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1029734268
86.09 4.57 97.44 1.92 91.71 3.41 92.69 0.46 79.49 2.56 96.97 1.89 94.41 2.22 49.95 19.54 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2795096850
87.58 1.48 97.56 0.11 92.09 0.38 97.26 4.57 79.49 0.00 96.97 0.00 94.51 0.10 55.18 5.23 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.872077887
88.79 1.21 97.63 0.07 93.35 1.26 97.95 0.68 79.49 0.00 97.08 0.11 94.51 0.00 61.54 6.36 /workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1493914282
89.99 1.20 97.67 0.04 93.38 0.03 97.95 0.00 80.13 0.64 97.12 0.04 94.99 0.48 68.72 7.18 /workspace/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3451345648
90.84 0.85 97.80 0.13 93.88 0.51 97.95 0.00 82.05 1.92 97.23 0.11 97.01 2.02 69.95 1.23 /workspace/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2294782728
91.62 0.79 97.80 0.00 94.01 0.13 97.95 0.00 82.05 0.00 97.23 0.00 97.21 0.19 75.13 5.18 /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1614891232
92.12 0.50 97.89 0.09 94.01 0.00 97.95 0.00 85.26 3.21 97.41 0.18 97.21 0.00 75.13 0.00 /workspace/coverage/default/17.sysrst_ctrl_edge_detect.953190545
92.61 0.49 97.98 0.09 94.19 0.18 97.95 0.00 85.26 0.00 97.41 0.00 97.21 0.00 78.31 3.18 /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2627208841
92.99 0.38 98.08 0.09 94.29 0.10 97.95 0.00 87.18 1.92 97.52 0.11 97.40 0.19 78.51 0.21 /workspace/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.2390769534
93.33 0.34 98.17 0.09 94.34 0.05 97.95 0.00 89.10 1.92 97.63 0.11 97.59 0.19 78.51 0.00 /workspace/coverage/default/31.sysrst_ctrl_edge_detect.1260499984
93.66 0.33 98.28 0.11 94.41 0.08 97.95 0.00 90.38 1.28 97.78 0.15 97.78 0.19 79.03 0.51 /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3555372347
93.98 0.32 98.36 0.07 94.44 0.03 97.95 0.00 92.31 1.92 97.89 0.11 97.88 0.10 79.03 0.00 /workspace/coverage/default/2.sysrst_ctrl_stress_all.1852351336
94.29 0.31 98.36 0.00 94.46 0.03 99.77 1.83 92.31 0.00 97.89 0.00 97.98 0.10 79.28 0.26 /workspace/coverage/default/3.sysrst_ctrl_sec_cm.3683078081
94.58 0.28 98.40 0.04 94.67 0.20 99.77 0.00 92.31 0.00 97.89 0.00 97.98 0.00 81.03 1.74 /workspace/coverage/default/37.sysrst_ctrl_stress_all.2886265808
94.82 0.24 98.45 0.06 94.72 0.05 99.77 0.00 92.95 0.64 97.93 0.04 98.07 0.10 81.85 0.82 /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2207602119
95.02 0.20 98.47 0.02 94.77 0.05 99.77 0.00 92.95 0.00 97.97 0.04 98.36 0.29 82.82 0.97 /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2729664145
95.18 0.17 98.47 0.00 94.87 0.10 99.77 0.00 92.95 0.00 97.97 0.00 99.04 0.67 83.23 0.41 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.563451975
95.35 0.17 98.53 0.06 94.87 0.00 99.77 0.00 92.95 0.00 97.97 0.00 99.04 0.00 84.36 1.13 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3560092950
95.52 0.16 98.56 0.04 95.20 0.33 99.77 0.00 93.59 0.64 98.00 0.04 99.13 0.10 84.36 0.00 /workspace/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2929427186
95.67 0.15 98.60 0.04 95.25 0.05 99.77 0.00 94.23 0.64 98.04 0.04 99.23 0.10 84.56 0.21 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.42089320
95.80 0.13 98.60 0.00 96.08 0.83 99.77 0.00 94.23 0.00 98.04 0.00 99.23 0.00 84.67 0.10 /workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.3843864347
95.93 0.13 98.64 0.04 96.11 0.03 99.77 0.00 94.87 0.64 98.08 0.04 99.33 0.10 84.72 0.05 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.213647273
96.04 0.11 98.64 0.00 96.11 0.00 99.77 0.00 94.87 0.00 98.08 0.00 99.33 0.00 85.49 0.77 /workspace/coverage/default/22.sysrst_ctrl_combo_detect.3390944422
96.15 0.11 98.66 0.02 96.11 0.00 99.77 0.00 95.51 0.64 98.11 0.04 99.33 0.00 85.54 0.05 /workspace/coverage/default/38.sysrst_ctrl_edge_detect.3069400919
96.25 0.10 98.68 0.02 96.11 0.00 99.77 0.00 96.15 0.64 98.15 0.04 99.33 0.00 85.54 0.00 /workspace/coverage/default/1.sysrst_ctrl_edge_detect.3222509121
96.34 0.10 98.68 0.00 96.11 0.00 99.77 0.00 96.15 0.00 98.15 0.00 99.33 0.00 86.21 0.67 /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2690746145
96.40 0.06 98.68 0.00 96.11 0.00 99.77 0.00 96.15 0.00 98.15 0.00 99.33 0.00 86.62 0.41 /workspace/coverage/default/33.sysrst_ctrl_stress_all.232788254
96.45 0.05 98.73 0.06 96.18 0.08 100.00 0.23 96.15 0.00 98.15 0.00 99.33 0.00 86.62 0.00 /workspace/coverage/default/11.sysrst_ctrl_alert_test.1979899044
96.50 0.05 98.77 0.04 96.33 0.15 100.00 0.00 96.15 0.00 98.23 0.07 99.42 0.10 86.62 0.00 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.4204209015
96.55 0.04 98.77 0.00 96.33 0.00 100.00 0.00 96.15 0.00 98.23 0.00 99.42 0.00 86.92 0.31 /workspace/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.205599332
96.58 0.04 98.77 0.00 96.33 0.00 100.00 0.00 96.15 0.00 98.23 0.00 99.42 0.00 87.18 0.26 /workspace/coverage/default/23.sysrst_ctrl_combo_detect.446258193
96.61 0.03 98.81 0.04 96.33 0.00 100.00 0.00 96.15 0.00 98.30 0.07 99.42 0.00 87.28 0.10 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.673462617
96.64 0.03 98.81 0.00 96.33 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 87.49 0.21 /workspace/coverage/default/14.sysrst_ctrl_combo_detect.1251545713
96.67 0.03 98.81 0.00 96.33 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 87.69 0.21 /workspace/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2300455814
96.69 0.02 98.81 0.00 96.33 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 87.85 0.15 /workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.1231775410
96.72 0.02 98.81 0.00 96.33 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.00 0.15 /workspace/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3120229643
96.74 0.02 98.81 0.00 96.39 0.05 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.10 0.10 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.89059082
96.76 0.02 98.81 0.00 96.54 0.15 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.10 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.4078187196
96.78 0.02 98.81 0.00 96.56 0.03 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.21 0.10 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3513169905
96.79 0.01 98.81 0.00 96.56 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.31 0.10 /workspace/coverage/default/16.sysrst_ctrl_combo_detect.508159130
96.81 0.01 98.81 0.00 96.56 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.41 0.10 /workspace/coverage/default/46.sysrst_ctrl_combo_detect.749267692
96.82 0.01 98.81 0.00 96.56 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.51 0.10 /workspace/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.4099069261
96.83 0.01 98.81 0.00 96.59 0.03 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.56 0.05 /workspace/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1450364008
96.84 0.01 98.81 0.00 96.59 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.62 0.05 /workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3309832976
96.85 0.01 98.81 0.00 96.59 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.67 0.05 /workspace/coverage/default/0.sysrst_ctrl_auto_blk_key_output.2777350373
96.86 0.01 98.81 0.00 96.59 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.72 0.05 /workspace/coverage/default/13.sysrst_ctrl_combo_detect.2868405396
96.86 0.01 98.81 0.00 96.59 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.77 0.05 /workspace/coverage/default/14.sysrst_ctrl_ultra_low_pwr.4242475546
96.87 0.01 98.81 0.00 96.59 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.82 0.05 /workspace/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1406475748
96.88 0.01 98.81 0.00 96.59 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.87 0.05 /workspace/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.171551215
96.88 0.01 98.81 0.00 96.59 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.92 0.05 /workspace/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2575817860
96.89 0.01 98.81 0.00 96.59 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 88.97 0.05 /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.4114593367
96.90 0.01 98.81 0.00 96.59 0.00 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 89.03 0.05 /workspace/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.448469916
96.90 0.01 98.81 0.00 96.61 0.03 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 89.03 0.00 /workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.156679248
96.91 0.01 98.81 0.00 96.64 0.03 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 89.03 0.00 /workspace/coverage/default/0.sysrst_ctrl_feature_disable.4039643741
96.91 0.01 98.81 0.00 96.66 0.03 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 89.03 0.00 /workspace/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.3667607504
96.91 0.01 98.81 0.00 96.69 0.03 100.00 0.00 96.15 0.00 98.30 0.00 99.42 0.00 89.03 0.00 /workspace/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.3766668202


Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.3056009317
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.2824923860
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1363717883
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.2603747616
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3876541104
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3540967620
/workspace/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.2708223060
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3706236947
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.697153897
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.3050668275
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1149712071
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2308357586
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.1877789066
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.2801881286
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2236465724
/workspace/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.182563541
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.3965682261
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1182139985
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.805744530
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.3132110310
/workspace/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.3294441911
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.944991183
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.3543871485
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.638492459
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.1971974683
/workspace/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.2827518604
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2898021433
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.1228899144
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1909679807
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.3439974291
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2867470953
/workspace/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.221678096
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.1362988085
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3371607599
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3370395253
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.2277039582
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2051249651
/workspace/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.704128308
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1803066813
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.1412605197
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.1443715494
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.423045524
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.1543683818
/workspace/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.2010089637
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.3656066004
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.955227591
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2011241446
/workspace/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.3891080992
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3954663270
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2325473127
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.3370092739
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3455584079
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.1662258159
/workspace/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.3173324844
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.4911933
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.2993879177
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.4071711962
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.2075708509
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1111123905
/workspace/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3251593852
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.930817601
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.3355442136
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.118395230
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.3509435465
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2345856222
/workspace/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2532879467
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.990120426
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.3369296340
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.4009357940
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.3316951289
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.3716401335
/workspace/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.3795456937
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.1206583858
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2453928898
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.1176727056
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2389779521
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2646149854
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.2431332315
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.3062198702
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.900293715
/workspace/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.1781287653
/workspace/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.531049734
/workspace/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1561796912
/workspace/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.1244006469
/workspace/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.59685085
/workspace/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.760352317
/workspace/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1282232322
/workspace/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3617097288
/workspace/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.3863738225
/workspace/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1919130349
/workspace/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.954661837
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.465081711
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.1424158462
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.647327263
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.1817793899
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3086166316
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.780209822
/workspace/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.1063585892
/workspace/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.2637116428
/workspace/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2141767009
/workspace/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.3678671572
/workspace/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.1208080209
/workspace/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3597470832
/workspace/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.2362178432
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/workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.684654010
/workspace/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1749652841
/workspace/coverage/default/43.sysrst_ctrl_edge_detect.3963818046
/workspace/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2407667973
/workspace/coverage/default/43.sysrst_ctrl_in_out_inverted.3001006441
/workspace/coverage/default/43.sysrst_ctrl_pin_access_test.3749254064
/workspace/coverage/default/43.sysrst_ctrl_pin_override_test.2735487883
/workspace/coverage/default/43.sysrst_ctrl_smoke.2392305898
/workspace/coverage/default/43.sysrst_ctrl_stress_all.1560357395
/workspace/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2447472219
/workspace/coverage/default/43.sysrst_ctrl_ultra_low_pwr.877249949
/workspace/coverage/default/44.sysrst_ctrl_alert_test.3489235137
/workspace/coverage/default/44.sysrst_ctrl_auto_blk_key_output.2324806631
/workspace/coverage/default/44.sysrst_ctrl_combo_detect.1765605978
/workspace/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.928013554
/workspace/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3837822053
/workspace/coverage/default/44.sysrst_ctrl_edge_detect.4000714505
/workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1379604338
/workspace/coverage/default/44.sysrst_ctrl_in_out_inverted.2973319888
/workspace/coverage/default/44.sysrst_ctrl_pin_access_test.2337030525
/workspace/coverage/default/44.sysrst_ctrl_pin_override_test.2308868571
/workspace/coverage/default/44.sysrst_ctrl_smoke.1001824421
/workspace/coverage/default/44.sysrst_ctrl_stress_all.2513935762
/workspace/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.578318172
/workspace/coverage/default/44.sysrst_ctrl_ultra_low_pwr.1224349281
/workspace/coverage/default/45.sysrst_ctrl_alert_test.630889657
/workspace/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1331011462
/workspace/coverage/default/45.sysrst_ctrl_combo_detect.2818188328
/workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.250515759
/workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1123510186
/workspace/coverage/default/45.sysrst_ctrl_edge_detect.3856835259
/workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2301932283
/workspace/coverage/default/45.sysrst_ctrl_in_out_inverted.3243130696
/workspace/coverage/default/45.sysrst_ctrl_pin_access_test.2000436817
/workspace/coverage/default/45.sysrst_ctrl_pin_override_test.3443780215
/workspace/coverage/default/45.sysrst_ctrl_smoke.3989816171
/workspace/coverage/default/45.sysrst_ctrl_stress_all.1181003042
/workspace/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2204067766
/workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.24064854
/workspace/coverage/default/46.sysrst_ctrl_alert_test.1750229024
/workspace/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1357396471
/workspace/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.3972232468
/workspace/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.81956264
/workspace/coverage/default/46.sysrst_ctrl_edge_detect.4183134363
/workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3124504271
/workspace/coverage/default/46.sysrst_ctrl_in_out_inverted.2293991860
/workspace/coverage/default/46.sysrst_ctrl_pin_access_test.2979927491
/workspace/coverage/default/46.sysrst_ctrl_pin_override_test.2842966370
/workspace/coverage/default/46.sysrst_ctrl_smoke.2823428090
/workspace/coverage/default/46.sysrst_ctrl_stress_all.764744829
/workspace/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1782505600
/workspace/coverage/default/46.sysrst_ctrl_ultra_low_pwr.3822691286
/workspace/coverage/default/47.sysrst_ctrl_alert_test.2304889523
/workspace/coverage/default/47.sysrst_ctrl_auto_blk_key_output.782914665
/workspace/coverage/default/47.sysrst_ctrl_combo_detect.2447111383
/workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.218355718
/workspace/coverage/default/47.sysrst_ctrl_edge_detect.4136231566
/workspace/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.906131260
/workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.823557884
/workspace/coverage/default/47.sysrst_ctrl_pin_access_test.4249639397
/workspace/coverage/default/47.sysrst_ctrl_pin_override_test.210493068
/workspace/coverage/default/47.sysrst_ctrl_smoke.33769541
/workspace/coverage/default/47.sysrst_ctrl_stress_all.2002091377
/workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3330598846
/workspace/coverage/default/47.sysrst_ctrl_ultra_low_pwr.2507024516
/workspace/coverage/default/48.sysrst_ctrl_alert_test.1541665378
/workspace/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3054744701
/workspace/coverage/default/48.sysrst_ctrl_combo_detect.2381446687
/workspace/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.1203354156
/workspace/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.1131828776
/workspace/coverage/default/48.sysrst_ctrl_edge_detect.3571207699
/workspace/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3060517086
/workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3354650456
/workspace/coverage/default/48.sysrst_ctrl_pin_access_test.3366933349
/workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3817737010
/workspace/coverage/default/48.sysrst_ctrl_smoke.3977026863
/workspace/coverage/default/48.sysrst_ctrl_stress_all.3387494757
/workspace/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1950754608
/workspace/coverage/default/48.sysrst_ctrl_ultra_low_pwr.1278748969
/workspace/coverage/default/49.sysrst_ctrl_alert_test.1795450599
/workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3770672808
/workspace/coverage/default/49.sysrst_ctrl_combo_detect.897563972
/workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1202745592
/workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.194849968
/workspace/coverage/default/49.sysrst_ctrl_edge_detect.1923745114
/workspace/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1608890080
/workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4054596470
/workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1002909885
/workspace/coverage/default/49.sysrst_ctrl_pin_override_test.871660164
/workspace/coverage/default/49.sysrst_ctrl_smoke.3351176065
/workspace/coverage/default/49.sysrst_ctrl_stress_all.1347161050
/workspace/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.1088985675
/workspace/coverage/default/49.sysrst_ctrl_ultra_low_pwr.4149595163
/workspace/coverage/default/5.sysrst_ctrl_alert_test.340819366
/workspace/coverage/default/5.sysrst_ctrl_auto_blk_key_output.2685307698
/workspace/coverage/default/5.sysrst_ctrl_combo_detect.2431502428
/workspace/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1239731192
/workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.671808397
/workspace/coverage/default/5.sysrst_ctrl_edge_detect.2567021933
/workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.275433364
/workspace/coverage/default/5.sysrst_ctrl_in_out_inverted.229778988
/workspace/coverage/default/5.sysrst_ctrl_pin_access_test.151032235
/workspace/coverage/default/5.sysrst_ctrl_pin_override_test.1087534092
/workspace/coverage/default/5.sysrst_ctrl_smoke.2201324319
/workspace/coverage/default/5.sysrst_ctrl_stress_all.92481234
/workspace/coverage/default/5.sysrst_ctrl_ultra_low_pwr.3154029831
/workspace/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.2512260058
/workspace/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.2647587570
/workspace/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.941941057
/workspace/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.2617462890
/workspace/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.852435372
/workspace/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.449433734
/workspace/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.3781812531
/workspace/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.833943701
/workspace/coverage/default/6.sysrst_ctrl_alert_test.230948426
/workspace/coverage/default/6.sysrst_ctrl_auto_blk_key_output.144146219
/workspace/coverage/default/6.sysrst_ctrl_combo_detect.3403581466
/workspace/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1305455711
/workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1872131261
/workspace/coverage/default/6.sysrst_ctrl_edge_detect.1414354090
/workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1110026944
/workspace/coverage/default/6.sysrst_ctrl_in_out_inverted.735569695
/workspace/coverage/default/6.sysrst_ctrl_pin_access_test.530269338
/workspace/coverage/default/6.sysrst_ctrl_pin_override_test.538960413
/workspace/coverage/default/6.sysrst_ctrl_smoke.1327067275
/workspace/coverage/default/6.sysrst_ctrl_stress_all.2514462102
/workspace/coverage/default/6.sysrst_ctrl_ultra_low_pwr.262733513
/workspace/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.302562988
/workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3921754972
/workspace/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.1621794043
/workspace/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.707516753
/workspace/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3612738288
/workspace/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.1057327980
/workspace/coverage/default/7.sysrst_ctrl_alert_test.415592330
/workspace/coverage/default/7.sysrst_ctrl_auto_blk_key_output.303052837
/workspace/coverage/default/7.sysrst_ctrl_combo_detect.667164413
/workspace/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.945947474
/workspace/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2968016392
/workspace/coverage/default/7.sysrst_ctrl_edge_detect.2150364279
/workspace/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.413220321
/workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2698429241
/workspace/coverage/default/7.sysrst_ctrl_pin_access_test.1516359361
/workspace/coverage/default/7.sysrst_ctrl_pin_override_test.4002922622
/workspace/coverage/default/7.sysrst_ctrl_smoke.3877330929
/workspace/coverage/default/7.sysrst_ctrl_stress_all.1581765197
/workspace/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.2493899054
/workspace/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1328251896
/workspace/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.4283860074
/workspace/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3875653134
/workspace/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.2658254911
/workspace/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2260877122
/workspace/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.415030829
/workspace/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1341466547
/workspace/coverage/default/8.sysrst_ctrl_alert_test.2551137782
/workspace/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2290795113
/workspace/coverage/default/8.sysrst_ctrl_combo_detect.2861738960
/workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2205755735
/workspace/coverage/default/8.sysrst_ctrl_edge_detect.1636726984
/workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2909982436
/workspace/coverage/default/8.sysrst_ctrl_in_out_inverted.2896057446
/workspace/coverage/default/8.sysrst_ctrl_pin_access_test.1866746544
/workspace/coverage/default/8.sysrst_ctrl_pin_override_test.2071383747
/workspace/coverage/default/8.sysrst_ctrl_smoke.2838727417
/workspace/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.751057269
/workspace/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3804457782
/workspace/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1173804710
/workspace/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.595703720
/workspace/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1481659442
/workspace/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.744474891
/workspace/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1899236892
/workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1406009508
/workspace/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.4153402258
/workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3606198931
/workspace/coverage/default/9.sysrst_ctrl_alert_test.3737210203
/workspace/coverage/default/9.sysrst_ctrl_auto_blk_key_output.4127232406
/workspace/coverage/default/9.sysrst_ctrl_combo_detect.3159782008
/workspace/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3693092611
/workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.148692302
/workspace/coverage/default/9.sysrst_ctrl_edge_detect.3339866972
/workspace/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.3509993954
/workspace/coverage/default/9.sysrst_ctrl_in_out_inverted.978833843
/workspace/coverage/default/9.sysrst_ctrl_pin_access_test.331059592
/workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2801431100
/workspace/coverage/default/9.sysrst_ctrl_smoke.3130314706
/workspace/coverage/default/9.sysrst_ctrl_stress_all.1047577154
/workspace/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.112737792
/workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.36233969
/workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3834896710
/workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2652894971
/workspace/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.177268171
/workspace/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.4285525116
/workspace/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.2741840645
/workspace/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1137784994
/workspace/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.16995723




Total test records in report: 915
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html

TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T5 /workspace/coverage/default/49.sysrst_ctrl_auto_blk_key_output.3770672808 Jul 21 06:39:38 PM PDT 24 Jul 21 06:39:40 PM PDT 24 3792067481 ps
T1 /workspace/coverage/default/8.sysrst_ctrl_stress_all.380724280 Jul 21 06:37:58 PM PDT 24 Jul 21 06:47:41 PM PDT 24 211597208275 ps
T6 /workspace/coverage/default/38.sysrst_ctrl_in_out_inverted.2550207906 Jul 21 06:38:58 PM PDT 24 Jul 21 06:39:01 PM PDT 24 2486245866 ps
T2 /workspace/coverage/default/39.sysrst_ctrl_edge_detect.3007579644 Jul 21 06:39:02 PM PDT 24 Jul 21 06:39:05 PM PDT 24 3465411530 ps
T3 /workspace/coverage/default/22.sysrst_ctrl_combo_detect.3390944422 Jul 21 06:38:30 PM PDT 24 Jul 21 06:40:46 PM PDT 24 199236346825 ps
T7 /workspace/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.1656470589 Jul 21 06:37:46 PM PDT 24 Jul 21 06:37:54 PM PDT 24 2402185511 ps
T13 /workspace/coverage/default/12.sysrst_ctrl_auto_blk_key_output.4187674714 Jul 21 06:38:00 PM PDT 24 Jul 21 06:38:12 PM PDT 24 3526107635 ps
T14 /workspace/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.4087275263 Jul 21 06:38:03 PM PDT 24 Jul 21 06:38:07 PM PDT 24 3575785968 ps
T15 /workspace/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.2747074905 Jul 21 06:39:16 PM PDT 24 Jul 21 06:40:11 PM PDT 24 19876879658 ps
T4 /workspace/coverage/default/28.sysrst_ctrl_edge_detect.3455099081 Jul 21 06:38:40 PM PDT 24 Jul 21 06:38:46 PM PDT 24 3316893613 ps
T16 /workspace/coverage/default/28.sysrst_ctrl_auto_blk_key_output.4291951706 Jul 21 06:38:40 PM PDT 24 Jul 21 06:44:48 PM PDT 24 300933497328 ps
T22 /workspace/coverage/default/7.sysrst_ctrl_in_out_inverted.2698429241 Jul 21 06:37:51 PM PDT 24 Jul 21 06:38:01 PM PDT 24 2469966484 ps
T8 /workspace/coverage/default/24.sysrst_ctrl_edge_detect.1333604505 Jul 21 06:38:34 PM PDT 24 Jul 21 06:38:44 PM PDT 24 3435988556 ps
T24 /workspace/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.1532824224 Jul 21 06:39:04 PM PDT 24 Jul 21 06:39:12 PM PDT 24 2609767552 ps
T69 /workspace/coverage/default/11.sysrst_ctrl_stress_all.3664141153 Jul 21 06:38:02 PM PDT 24 Jul 21 06:38:26 PM PDT 24 8939044285 ps
T9 /workspace/coverage/default/29.sysrst_ctrl_edge_detect.1065771611 Jul 21 06:38:44 PM PDT 24 Jul 21 06:38:51 PM PDT 24 2506392927 ps
T25 /workspace/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.3834896710 Jul 21 06:39:41 PM PDT 24 Jul 21 06:39:58 PM PDT 24 25605219564 ps
T50 /workspace/coverage/default/3.sysrst_ctrl_sec_cm.3683078081 Jul 21 06:37:51 PM PDT 24 Jul 21 06:38:00 PM PDT 24 22212696600 ps
T51 /workspace/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.1379604338 Jul 21 06:39:18 PM PDT 24 Jul 21 06:39:21 PM PDT 24 2638253779 ps
T52 /workspace/coverage/default/2.sysrst_ctrl_pin_access_test.2421876936 Jul 21 06:37:37 PM PDT 24 Jul 21 06:37:41 PM PDT 24 2112278690 ps
T53 /workspace/coverage/default/47.sysrst_ctrl_pin_access_test.4249639397 Jul 21 06:39:29 PM PDT 24 Jul 21 06:39:31 PM PDT 24 2127465660 ps
T10 /workspace/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1029734268 Jul 21 06:38:09 PM PDT 24 Jul 21 06:39:04 PM PDT 24 27008179294 ps
T54 /workspace/coverage/default/28.sysrst_ctrl_pin_override_test.1514269255 Jul 21 06:38:40 PM PDT 24 Jul 21 06:38:46 PM PDT 24 2510094119 ps
T55 /workspace/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.4231607142 Jul 21 06:38:40 PM PDT 24 Jul 21 06:38:49 PM PDT 24 2609472917 ps
T56 /workspace/coverage/default/29.sysrst_ctrl_smoke.4280534141 Jul 21 06:38:46 PM PDT 24 Jul 21 06:38:49 PM PDT 24 2131902430 ps
T57 /workspace/coverage/default/26.sysrst_ctrl_pin_override_test.2638317128 Jul 21 06:38:37 PM PDT 24 Jul 21 06:38:45 PM PDT 24 2511161041 ps
T11 /workspace/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3606198931 Jul 21 06:39:42 PM PDT 24 Jul 21 06:45:37 PM PDT 24 131285072294 ps
T60 /workspace/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2205755735 Jul 21 06:37:58 PM PDT 24 Jul 21 06:38:06 PM PDT 24 5055680590 ps
T12 /workspace/coverage/default/6.sysrst_ctrl_edge_detect.1414354090 Jul 21 06:37:55 PM PDT 24 Jul 21 06:38:07 PM PDT 24 4760961085 ps
T61 /workspace/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.3678896856 Jul 21 06:37:51 PM PDT 24 Jul 21 06:37:55 PM PDT 24 4521708067 ps
T64 /workspace/coverage/default/49.sysrst_ctrl_pin_access_test.1002909885 Jul 21 06:39:29 PM PDT 24 Jul 21 06:39:36 PM PDT 24 2219310568 ps
T26 /workspace/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.872077887 Jul 21 06:39:42 PM PDT 24 Jul 21 06:40:44 PM PDT 24 70512914077 ps
T110 /workspace/coverage/default/31.sysrst_ctrl_smoke.3104739889 Jul 21 06:38:45 PM PDT 24 Jul 21 06:38:48 PM PDT 24 2128961506 ps
T45 /workspace/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.3212442819 Jul 21 06:38:45 PM PDT 24 Jul 21 06:42:43 PM PDT 24 89774219205 ps
T111 /workspace/coverage/default/7.sysrst_ctrl_alert_test.415592330 Jul 21 06:37:57 PM PDT 24 Jul 21 06:38:04 PM PDT 24 2009897287 ps
T70 /workspace/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.4160179271 Jul 21 06:38:38 PM PDT 24 Jul 21 06:38:44 PM PDT 24 2616987071 ps
T165 /workspace/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.4186148897 Jul 21 06:38:13 PM PDT 24 Jul 21 06:38:21 PM PDT 24 2607990060 ps
T23 /workspace/coverage/default/40.sysrst_ctrl_stress_all.78191222 Jul 21 06:39:11 PM PDT 24 Jul 21 06:39:33 PM PDT 24 16762619332 ps
T30 /workspace/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.89059082 Jul 21 06:38:35 PM PDT 24 Jul 21 06:40:34 PM PDT 24 100350195638 ps
T46 /workspace/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2671142432 Jul 21 06:38:03 PM PDT 24 Jul 21 06:38:10 PM PDT 24 3415377102 ps
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T66 /workspace/coverage/default/49.sysrst_ctrl_in_out_inverted.4054596470 Jul 21 06:39:32 PM PDT 24 Jul 21 06:39:39 PM PDT 24 2480471828 ps
T31 /workspace/coverage/default/13.sysrst_ctrl_stress_all.3457860988 Jul 21 06:38:06 PM PDT 24 Jul 21 06:38:20 PM PDT 24 11338812693 ps
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T20 /workspace/coverage/default/1.sysrst_ctrl_feature_disable.2854437610 Jul 21 06:37:44 PM PDT 24 Jul 21 06:39:34 PM PDT 24 41133128300 ps
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T183 /workspace/coverage/default/5.sysrst_ctrl_pin_access_test.151032235 Jul 21 06:37:52 PM PDT 24 Jul 21 06:37:57 PM PDT 24 2103686743 ps
T39 /workspace/coverage/default/18.sysrst_ctrl_stress_all.3803971895 Jul 21 06:38:17 PM PDT 24 Jul 21 06:39:37 PM PDT 24 666475203644 ps
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T48 /workspace/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2611798645 Jul 21 06:38:14 PM PDT 24 Jul 21 06:38:16 PM PDT 24 3817923778 ps
T49 /workspace/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1356844355 Jul 21 06:38:56 PM PDT 24 Jul 21 06:38:59 PM PDT 24 3325628495 ps
T104 /workspace/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2253762530 Jul 21 06:38:15 PM PDT 24 Jul 21 06:38:19 PM PDT 24 2633720988 ps
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T62 /workspace/coverage/default/9.sysrst_ctrl_ultra_low_pwr.36233969 Jul 21 06:37:58 PM PDT 24 Jul 21 06:38:01 PM PDT 24 12618790446 ps
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T379 /workspace/coverage/default/3.sysrst_ctrl_pin_override_test.1157851209 Jul 21 06:37:45 PM PDT 24 Jul 21 06:37:48 PM PDT 24 2532908196 ps
T382 /workspace/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.2791418526 Jul 21 06:38:19 PM PDT 24 Jul 21 06:38:23 PM PDT 24 4599176427 ps
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T366 /workspace/coverage/default/23.sysrst_ctrl_stress_all.1982232002 Jul 21 06:38:29 PM PDT 24 Jul 21 06:38:37 PM PDT 24 11452582554 ps
T32 /workspace/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3551116274 Jul 21 06:39:13 PM PDT 24 Jul 21 06:39:17 PM PDT 24 9750673004 ps
T135 /workspace/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2909982436 Jul 21 06:37:53 PM PDT 24 Jul 21 06:37:59 PM PDT 24 2619782036 ps
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T43 /workspace/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.3513169905 Jul 21 06:38:05 PM PDT 24 Jul 21 06:46:06 PM PDT 24 183239465492 ps
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T380 /workspace/coverage/default/48.sysrst_ctrl_pin_override_test.3817737010 Jul 21 06:39:27 PM PDT 24 Jul 21 06:39:30 PM PDT 24 2528534018 ps
T388 /workspace/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.3124504271 Jul 21 06:39:22 PM PDT 24 Jul 21 06:39:30 PM PDT 24 2611186621 ps
T68 /workspace/coverage/default/2.sysrst_ctrl_in_out_inverted.260903163 Jul 21 06:37:43 PM PDT 24 Jul 21 06:37:46 PM PDT 24 2498452935 ps
T242 /workspace/coverage/default/35.sysrst_ctrl_combo_detect.233794264 Jul 21 06:38:59 PM PDT 24 Jul 21 06:39:49 PM PDT 24 73814553473 ps
T263 /workspace/coverage/default/2.sysrst_ctrl_sec_cm.3620480892 Jul 21 06:37:46 PM PDT 24 Jul 21 06:39:32 PM PDT 24 42011210923 ps
T389 /workspace/coverage/default/26.sysrst_ctrl_auto_blk_key_output.847414530 Jul 21 06:38:33 PM PDT 24 Jul 21 06:38:36 PM PDT 24 3443540433 ps
T390 /workspace/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.148692302 Jul 21 06:37:53 PM PDT 24 Jul 21 06:38:01 PM PDT 24 4087850466 ps
T37 /workspace/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2795096850 Jul 21 06:38:12 PM PDT 24 Jul 21 06:39:43 PM PDT 24 1372948142180 ps
T41 /workspace/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.4055399425 Jul 21 06:38:46 PM PDT 24 Jul 21 06:39:50 PM PDT 24 50606650000 ps
T38 /workspace/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2020240291 Jul 21 06:38:59 PM PDT 24 Jul 21 06:39:05 PM PDT 24 18542469490 ps
T224 /workspace/coverage/default/5.sysrst_ctrl_combo_detect.2431502428 Jul 21 06:37:51 PM PDT 24 Jul 21 06:41:39 PM PDT 24 92425447866 ps
T225 /workspace/coverage/default/3.sysrst_ctrl_in_out_inverted.375999533 Jul 21 06:37:45 PM PDT 24 Jul 21 06:37:51 PM PDT 24 2449441628 ps
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T86 /workspace/coverage/default/30.sysrst_ctrl_edge_detect.3497974771 Jul 21 06:38:46 PM PDT 24 Jul 21 06:38:52 PM PDT 24 3283137149 ps
T188 /workspace/coverage/default/31.sysrst_ctrl_in_out_inverted.1253780501 Jul 21 06:38:49 PM PDT 24 Jul 21 06:38:51 PM PDT 24 2485961676 ps
T140 /workspace/coverage/default/25.sysrst_ctrl_stress_all.3071778614 Jul 21 06:38:36 PM PDT 24 Jul 21 06:39:04 PM PDT 24 13423660205 ps
T109 /workspace/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1458266692 Jul 21 06:38:09 PM PDT 24 Jul 21 06:38:20 PM PDT 24 3598471590 ps
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T75 /workspace/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.213647273 Jul 21 06:37:48 PM PDT 24 Jul 21 06:38:52 PM PDT 24 111885745570 ps
T189 /workspace/coverage/default/36.sysrst_ctrl_in_out_inverted.4229006755 Jul 21 06:38:58 PM PDT 24 Jul 21 06:39:05 PM PDT 24 2459946980 ps
T190 /workspace/coverage/default/32.sysrst_ctrl_combo_detect.3225112869 Jul 21 06:38:47 PM PDT 24 Jul 21 06:41:46 PM PDT 24 68938695482 ps
T191 /workspace/coverage/default/42.sysrst_ctrl_in_out_inverted.4002201672 Jul 21 06:39:16 PM PDT 24 Jul 21 06:39:19 PM PDT 24 2494392324 ps
T192 /workspace/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.194548766 Jul 21 06:38:20 PM PDT 24 Jul 21 06:38:22 PM PDT 24 2697204741 ps
T391 /workspace/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.163659282 Jul 21 06:38:56 PM PDT 24 Jul 21 06:39:08 PM PDT 24 4045719023 ps
T151 /workspace/coverage/default/34.sysrst_ctrl_edge_detect.1752571123 Jul 21 06:38:54 PM PDT 24 Jul 21 06:38:56 PM PDT 24 4635743179 ps
T375 /workspace/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2039800961 Jul 21 06:38:39 PM PDT 24 Jul 21 06:45:44 PM PDT 24 636904889714 ps
T72 /workspace/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.496499646 Jul 21 06:39:15 PM PDT 24 Jul 21 06:39:46 PM PDT 24 45659725011 ps
T44 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.3498246415 Jul 21 06:37:49 PM PDT 24 Jul 21 06:38:21 PM PDT 24 50722468381 ps
T76 /workspace/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.673462617 Jul 21 06:38:19 PM PDT 24 Jul 21 06:39:48 PM PDT 24 143222608387 ps
T35 /workspace/coverage/default/2.sysrst_ctrl_combo_detect.203812489 Jul 21 06:37:43 PM PDT 24 Jul 21 06:44:56 PM PDT 24 174782065836 ps
T392 /workspace/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.3777587584 Jul 21 06:38:22 PM PDT 24 Jul 21 06:38:35 PM PDT 24 4128193099 ps
T393 /workspace/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.671808397 Jul 21 06:37:48 PM PDT 24 Jul 21 06:37:52 PM PDT 24 2715331252 ps
T296 /workspace/coverage/default/23.sysrst_ctrl_in_out_inverted.2989407219 Jul 21 06:38:37 PM PDT 24 Jul 21 06:38:40 PM PDT 24 2501056072 ps
T248 /workspace/coverage/default/20.sysrst_ctrl_combo_detect.2878753370 Jul 21 06:38:17 PM PDT 24 Jul 21 06:45:08 PM PDT 24 160427712802 ps
T394 /workspace/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.3748880561 Jul 21 06:38:58 PM PDT 24 Jul 21 06:39:03 PM PDT 24 5170583123 ps
T166 /workspace/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2126494960 Jul 21 06:38:42 PM PDT 24 Jul 21 06:40:07 PM PDT 24 33976395098 ps
T307 /workspace/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3327653743 Jul 21 06:38:22 PM PDT 24 Jul 21 06:38:27 PM PDT 24 2618052004 ps
T308 /workspace/coverage/default/47.sysrst_ctrl_smoke.33769541 Jul 21 06:39:25 PM PDT 24 Jul 21 06:39:32 PM PDT 24 2113430245 ps
T309 /workspace/coverage/default/11.sysrst_ctrl_alert_test.1979899044 Jul 21 06:38:02 PM PDT 24 Jul 21 06:38:09 PM PDT 24 2010962009 ps
T310 /workspace/coverage/default/27.sysrst_ctrl_pin_access_test.3407445508 Jul 21 06:38:38 PM PDT 24 Jul 21 06:38:45 PM PDT 24 2197500512 ps
T311 /workspace/coverage/default/12.sysrst_ctrl_pin_override_test.219165888 Jul 21 06:38:05 PM PDT 24 Jul 21 06:38:13 PM PDT 24 2509133121 ps
T312 /workspace/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.218355718 Jul 21 06:39:29 PM PDT 24 Jul 21 06:39:44 PM PDT 24 5189239262 ps
T313 /workspace/coverage/default/37.sysrst_ctrl_pin_access_test.299929742 Jul 21 06:38:58 PM PDT 24 Jul 21 06:39:01 PM PDT 24 2084020389 ps
T314 /workspace/coverage/default/30.sysrst_ctrl_pin_override_test.1224968298 Jul 21 06:38:48 PM PDT 24 Jul 21 06:38:56 PM PDT 24 2513318067 ps
T315 /workspace/coverage/default/20.sysrst_ctrl_stress_all.1709266128 Jul 21 06:38:20 PM PDT 24 Jul 21 06:38:40 PM PDT 24 6731162015 ps
T395 /workspace/coverage/default/2.sysrst_ctrl_ultra_low_pwr.2154743451 Jul 21 06:37:51 PM PDT 24 Jul 21 06:37:56 PM PDT 24 6784572928 ps
T300 /workspace/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2435918843 Jul 21 06:38:08 PM PDT 24 Jul 21 06:38:10 PM PDT 24 3064886930 ps
T396 /workspace/coverage/default/43.sysrst_ctrl_stress_all.1560357395 Jul 21 06:39:19 PM PDT 24 Jul 21 06:39:37 PM PDT 24 8740741829 ps
T243 /workspace/coverage/default/34.sysrst_ctrl_combo_detect.3685681758 Jul 21 06:38:55 PM PDT 24 Jul 21 06:39:26 PM PDT 24 39808818352 ps
T397 /workspace/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.4086784271 Jul 21 06:38:29 PM PDT 24 Jul 21 06:38:37 PM PDT 24 2605729813 ps
T77 /workspace/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.1614891232 Jul 21 06:37:36 PM PDT 24 Jul 21 06:38:56 PM PDT 24 64774371685 ps
T73 /workspace/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1330687837 Jul 21 06:39:11 PM PDT 24 Jul 21 06:39:39 PM PDT 24 24836504442 ps
T171 /workspace/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3529539497 Jul 21 06:38:29 PM PDT 24 Jul 21 06:38:33 PM PDT 24 2630564533 ps
T172 /workspace/coverage/default/9.sysrst_ctrl_pin_override_test.2801431100 Jul 21 06:37:58 PM PDT 24 Jul 21 06:38:01 PM PDT 24 2530081685 ps
T173 /workspace/coverage/default/9.sysrst_ctrl_stress_all.1047577154 Jul 21 06:37:56 PM PDT 24 Jul 21 06:38:36 PM PDT 24 14829547689 ps
T115 /workspace/coverage/default/12.sysrst_ctrl_stress_all.153030449 Jul 21 06:38:03 PM PDT 24 Jul 21 06:38:14 PM PDT 24 15399656747 ps
T174 /workspace/coverage/default/6.sysrst_ctrl_pin_override_test.538960413 Jul 21 06:37:47 PM PDT 24 Jul 21 06:37:49 PM PDT 24 2644899645 ps
T175 /workspace/coverage/default/18.sysrst_ctrl_pin_override_test.1499591280 Jul 21 06:38:22 PM PDT 24 Jul 21 06:38:30 PM PDT 24 2511828763 ps
T176 /workspace/coverage/default/28.sysrst_ctrl_smoke.2417969546 Jul 21 06:38:38 PM PDT 24 Jul 21 06:38:40 PM PDT 24 2172611700 ps
T177 /workspace/coverage/default/40.sysrst_ctrl_alert_test.916996278 Jul 21 06:39:13 PM PDT 24 Jul 21 06:39:19 PM PDT 24 2013094574 ps
T398 /workspace/coverage/default/23.sysrst_ctrl_pin_access_test.1958609945 Jul 21 06:38:29 PM PDT 24 Jul 21 06:38:32 PM PDT 24 2201178766 ps
T92 /workspace/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.1406009508 Jul 21 06:39:41 PM PDT 24 Jul 21 06:40:47 PM PDT 24 24832557562 ps
T399 /workspace/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3893145834 Jul 21 06:38:30 PM PDT 24 Jul 21 06:38:33 PM PDT 24 3945110133 ps
T290 /workspace/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.3204132929 Jul 21 06:39:16 PM PDT 24 Jul 21 06:40:24 PM PDT 24 32588982504 ps
T400 /workspace/coverage/default/42.sysrst_ctrl_smoke.1243341932 Jul 21 06:39:19 PM PDT 24 Jul 21 06:39:23 PM PDT 24 2122546476 ps
T401 /workspace/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3043358684 Jul 21 06:38:28 PM PDT 24 Jul 21 06:38:31 PM PDT 24 3634401878 ps
T402 /workspace/coverage/default/41.sysrst_ctrl_in_out_inverted.2194215333 Jul 21 06:39:10 PM PDT 24 Jul 21 06:39:12 PM PDT 24 2517556778 ps
T93 /workspace/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1202745592 Jul 21 06:39:36 PM PDT 24 Jul 21 06:40:08 PM PDT 24 23843875848 ps
T403 /workspace/coverage/default/37.sysrst_ctrl_alert_test.4152537774 Jul 21 06:39:00 PM PDT 24 Jul 21 06:39:04 PM PDT 24 2020469693 ps
T301 /workspace/coverage/default/13.sysrst_ctrl_ultra_low_pwr.2754573900 Jul 21 06:38:13 PM PDT 24 Jul 21 06:38:16 PM PDT 24 4843930369 ps
T404 /workspace/coverage/default/26.sysrst_ctrl_pin_access_test.3702336902 Jul 21 06:38:34 PM PDT 24 Jul 21 06:38:41 PM PDT 24 2178969971 ps
T405 /workspace/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3966642866 Jul 21 06:38:20 PM PDT 24 Jul 21 06:38:28 PM PDT 24 2776470326 ps
T152 /workspace/coverage/default/11.sysrst_ctrl_edge_detect.3049709593 Jul 21 06:38:00 PM PDT 24 Jul 21 06:38:04 PM PDT 24 3682821329 ps
T94 /workspace/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.3921754972 Jul 21 06:39:34 PM PDT 24 Jul 21 06:40:06 PM PDT 24 23589303001 ps
T406 /workspace/coverage/default/48.sysrst_ctrl_in_out_inverted.3354650456 Jul 21 06:39:27 PM PDT 24 Jul 21 06:39:31 PM PDT 24 2472787038 ps
T237 /workspace/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2627208841 Jul 21 06:39:35 PM PDT 24 Jul 21 06:44:27 PM PDT 24 214863509671 ps
T407 /workspace/coverage/default/8.sysrst_ctrl_smoke.2838727417 Jul 21 06:37:58 PM PDT 24 Jul 21 06:38:01 PM PDT 24 2126535602 ps
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T78 /workspace/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2729664145 Jul 21 06:37:50 PM PDT 24 Jul 21 06:42:38 PM PDT 24 147781227870 ps
T238 /workspace/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.423463428 Jul 21 06:38:16 PM PDT 24 Jul 21 06:44:28 PM PDT 24 156481804412 ps
T180 /workspace/coverage/default/15.sysrst_ctrl_edge_detect.4211306267 Jul 21 06:38:12 PM PDT 24 Jul 21 06:38:18 PM PDT 24 3089015932 ps
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T410 /workspace/coverage/default/45.sysrst_ctrl_alert_test.630889657 Jul 21 06:39:24 PM PDT 24 Jul 21 06:39:27 PM PDT 24 2034744368 ps
T178 /workspace/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.863313010 Jul 21 06:38:52 PM PDT 24 Jul 21 06:40:09 PM PDT 24 75523078861 ps
T411 /workspace/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1123510186 Jul 21 06:39:25 PM PDT 24 Jul 21 07:16:46 PM PDT 24 1860748986843 ps
T412 /workspace/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.2834372992 Jul 21 06:38:13 PM PDT 24 Jul 21 06:38:22 PM PDT 24 2611402733 ps
T413 /workspace/coverage/default/13.sysrst_ctrl_alert_test.2950491526 Jul 21 06:38:14 PM PDT 24 Jul 21 06:38:20 PM PDT 24 2011399684 ps
T414 /workspace/coverage/default/16.sysrst_ctrl_pin_override_test.2512584772 Jul 21 06:38:09 PM PDT 24 Jul 21 06:38:17 PM PDT 24 2514709658 ps
T239 /workspace/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.2408646587 Jul 21 06:38:55 PM PDT 24 Jul 21 06:39:44 PM PDT 24 78321558488 ps
T415 /workspace/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.409801519 Jul 21 06:38:56 PM PDT 24 Jul 21 06:39:04 PM PDT 24 2613202341 ps
T416 /workspace/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1872131261 Jul 21 06:37:51 PM PDT 24 Jul 21 06:37:55 PM PDT 24 2806619569 ps
T112 /workspace/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3014491032 Jul 21 06:38:03 PM PDT 24 Jul 21 06:38:06 PM PDT 24 8573740124 ps
T417 /workspace/coverage/default/38.sysrst_ctrl_alert_test.916538361 Jul 21 06:39:04 PM PDT 24 Jul 21 06:39:06 PM PDT 24 2045981332 ps
T418 /workspace/coverage/default/48.sysrst_ctrl_smoke.3977026863 Jul 21 06:39:26 PM PDT 24 Jul 21 06:39:33 PM PDT 24 2111649333 ps
T419 /workspace/coverage/default/45.sysrst_ctrl_edge_detect.3856835259 Jul 21 06:39:26 PM PDT 24 Jul 21 06:39:30 PM PDT 24 2895106907 ps
T420 /workspace/coverage/default/38.sysrst_ctrl_smoke.3399765718 Jul 21 06:39:01 PM PDT 24 Jul 21 06:39:05 PM PDT 24 2111377604 ps
T84 /workspace/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3555372347 Jul 21 06:38:34 PM PDT 24 Jul 21 06:38:55 PM PDT 24 80353519249 ps
T127 /workspace/coverage/default/47.sysrst_ctrl_in_out_inverted.823557884 Jul 21 06:39:26 PM PDT 24 Jul 21 06:39:29 PM PDT 24 2471202156 ps
T128 /workspace/coverage/default/40.sysrst_ctrl_pin_access_test.3693591275 Jul 21 06:39:12 PM PDT 24 Jul 21 06:39:15 PM PDT 24 2257455868 ps
T129 /workspace/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.684654010 Jul 21 06:39:18 PM PDT 24 Jul 21 06:39:45 PM PDT 24 68357644697 ps
T113 /workspace/coverage/default/45.sysrst_ctrl_ultra_low_pwr.24064854 Jul 21 06:39:24 PM PDT 24 Jul 21 06:39:27 PM PDT 24 2766670678 ps
T130 /workspace/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1110026944 Jul 21 06:37:54 PM PDT 24 Jul 21 06:38:03 PM PDT 24 2611158024 ps
T114 /workspace/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3330598846 Jul 21 06:39:29 PM PDT 24 Jul 21 06:40:23 PM PDT 24 82143699781 ps
T131 /workspace/coverage/default/12.sysrst_ctrl_pin_access_test.2553875289 Jul 21 06:38:02 PM PDT 24 Jul 21 06:38:05 PM PDT 24 2225068370 ps
T132 /workspace/coverage/default/8.sysrst_ctrl_alert_test.2551137782 Jul 21 06:37:54 PM PDT 24 Jul 21 06:37:58 PM PDT 24 2035895489 ps
T133 /workspace/coverage/default/33.sysrst_ctrl_in_out_inverted.1507093194 Jul 21 06:38:56 PM PDT 24 Jul 21 06:39:04 PM PDT 24 2456946357 ps
T207 /workspace/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.716381538 Jul 21 06:38:12 PM PDT 24 Jul 21 06:41:26 PM PDT 24 143457369384 ps
T421 /workspace/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2991664242 Jul 21 06:38:46 PM PDT 24 Jul 21 06:38:54 PM PDT 24 4757349334 ps
T80 /workspace/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.42089320 Jul 21 06:38:53 PM PDT 24 Jul 21 06:40:06 PM PDT 24 113066508289 ps
T141 /workspace/coverage/default/44.sysrst_ctrl_edge_detect.4000714505 Jul 21 06:39:26 PM PDT 24 Jul 21 06:39:34 PM PDT 24 2821555178 ps
T199 /workspace/coverage/default/42.sysrst_ctrl_pin_access_test.4008635698 Jul 21 06:39:16 PM PDT 24 Jul 21 06:39:18 PM PDT 24 2213128730 ps
T200 /workspace/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2690746145 Jul 21 06:37:55 PM PDT 24 Jul 21 06:41:21 PM PDT 24 82080890491 ps
T95 /workspace/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.2207602119 Jul 21 06:39:41 PM PDT 24 Jul 21 06:41:09 PM PDT 24 63872935895 ps
T201 /workspace/coverage/default/0.sysrst_ctrl_stress_all.1779302927 Jul 21 06:37:41 PM PDT 24 Jul 21 06:38:19 PM PDT 24 14375605104 ps
T202 /workspace/coverage/default/33.sysrst_ctrl_pin_override_test.467625060 Jul 21 06:38:54 PM PDT 24 Jul 21 06:38:59 PM PDT 24 2517484371 ps
T203 /workspace/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1010151267 Jul 21 06:38:50 PM PDT 24 Jul 21 06:39:16 PM PDT 24 42241967106 ps
T139 /workspace/coverage/default/21.sysrst_ctrl_stress_all.2814864931 Jul 21 06:38:20 PM PDT 24 Jul 21 06:38:27 PM PDT 24 9319625851 ps
T204 /workspace/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2301932283 Jul 21 06:39:25 PM PDT 24 Jul 21 06:39:27 PM PDT 24 2655029291 ps
T422 /workspace/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.275433364 Jul 21 06:37:51 PM PDT 24 Jul 21 06:38:01 PM PDT 24 2610736070 ps
T96 /workspace/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.250515759 Jul 21 06:39:23 PM PDT 24 Jul 21 06:40:31 PM PDT 24 27579810491 ps
T423 /workspace/coverage/default/9.sysrst_ctrl_edge_detect.3339866972 Jul 21 06:37:58 PM PDT 24 Jul 21 06:38:01 PM PDT 24 3001947687 ps
T181 /workspace/coverage/default/42.sysrst_ctrl_edge_detect.3327475305 Jul 21 06:39:18 PM PDT 24 Jul 21 06:39:27 PM PDT 24 3956571379 ps
T424 /workspace/coverage/default/46.sysrst_ctrl_alert_test.1750229024 Jul 21 06:39:24 PM PDT 24 Jul 21 06:39:27 PM PDT 24 2035389354 ps
T425 /workspace/coverage/default/17.sysrst_ctrl_pin_access_test.3335282212 Jul 21 06:38:31 PM PDT 24 Jul 21 06:38:34 PM PDT 24 2256901053 ps
T82 /workspace/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.4114593367 Jul 21 06:39:44 PM PDT 24 Jul 21 06:40:29 PM PDT 24 67222414753 ps
T426 /workspace/coverage/default/39.sysrst_ctrl_in_out_inverted.1901790355 Jul 21 06:39:04 PM PDT 24 Jul 21 06:39:06 PM PDT 24 2487184162 ps
T427 /workspace/coverage/default/29.sysrst_ctrl_alert_test.4020655633 Jul 21 06:38:46 PM PDT 24 Jul 21 06:38:49 PM PDT 24 2036003899 ps
T428 /workspace/coverage/default/24.sysrst_ctrl_pin_access_test.2120484393 Jul 21 06:38:37 PM PDT 24 Jul 21 06:38:44 PM PDT 24 2235185080 ps
T429 /workspace/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.2716795133 Jul 21 06:39:13 PM PDT 24 Jul 21 06:39:15 PM PDT 24 2646273313 ps
T334 /workspace/coverage/default/9.sysrst_ctrl_combo_detect.3159782008 Jul 21 06:37:55 PM PDT 24 Jul 21 06:43:50 PM PDT 24 150146093160 ps
T430 /workspace/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3093528922 Jul 21 06:37:44 PM PDT 24 Jul 21 06:37:48 PM PDT 24 2526806834 ps
T431 /workspace/coverage/default/21.sysrst_ctrl_alert_test.3580270259 Jul 21 06:38:29 PM PDT 24 Jul 21 06:38:32 PM PDT 24 2026053128 ps
T432 /workspace/coverage/default/45.sysrst_ctrl_smoke.3989816171 Jul 21 06:39:26 PM PDT 24 Jul 21 06:39:33 PM PDT 24 2110092496 ps
T244 /workspace/coverage/default/10.sysrst_ctrl_combo_detect.2094104159 Jul 21 06:38:01 PM PDT 24 Jul 21 06:38:39 PM PDT 24 52365972208 ps
T433 /workspace/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.4074970238 Jul 21 06:38:17 PM PDT 24 Jul 21 06:38:22 PM PDT 24 5196347116 ps
T193 /workspace/coverage/default/32.sysrst_ctrl_edge_detect.1042975036 Jul 21 06:38:48 PM PDT 24 Jul 21 06:38:51 PM PDT 24 3759519103 ps
T251 /workspace/coverage/default/21.sysrst_ctrl_combo_detect.3723401267 Jul 21 06:38:27 PM PDT 24 Jul 21 06:42:48 PM PDT 24 99280462454 ps
T434 /workspace/coverage/default/24.sysrst_ctrl_pin_override_test.2673990607 Jul 21 06:38:27 PM PDT 24 Jul 21 06:38:32 PM PDT 24 2513521969 ps
T435 /workspace/coverage/default/10.sysrst_ctrl_in_out_inverted.1182942615 Jul 21 06:38:01 PM PDT 24 Jul 21 06:38:03 PM PDT 24 2528665076 ps
T362 /workspace/coverage/default/28.sysrst_ctrl_combo_detect.4153456084 Jul 21 06:38:43 PM PDT 24 Jul 21 06:40:59 PM PDT 24 103396503233 ps
T436 /workspace/coverage/default/10.sysrst_ctrl_edge_detect.1823779352 Jul 21 06:38:03 PM PDT 24 Jul 21 06:38:05 PM PDT 24 3021506449 ps
T437 /workspace/coverage/default/16.sysrst_ctrl_pin_access_test.1418422675 Jul 21 06:38:12 PM PDT 24 Jul 21 06:38:15 PM PDT 24 2269757920 ps
T245 /workspace/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.450049163 Jul 21 06:38:27 PM PDT 24 Jul 21 06:40:10 PM PDT 24 78023424574 ps
T241 /workspace/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3560092950 Jul 21 06:39:36 PM PDT 24 Jul 21 06:42:03 PM PDT 24 96760378503 ps
T377 /workspace/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2770059950 Jul 21 06:38:45 PM PDT 24 Jul 21 06:41:30 PM PDT 24 1262900206878 ps
T217 /workspace/coverage/default/0.sysrst_ctrl_edge_detect.1603079851 Jul 21 06:37:51 PM PDT 24 Jul 21 06:38:02 PM PDT 24 3216620197 ps
T287 /workspace/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2471420415 Jul 21 06:38:37 PM PDT 24 Jul 21 06:38:46 PM PDT 24 3385675494 ps
T438 /workspace/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.633411028 Jul 21 06:38:16 PM PDT 24 Jul 21 06:38:22 PM PDT 24 3233257199 ps
T83 /workspace/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2892418104 Jul 21 06:37:45 PM PDT 24 Jul 21 06:38:33 PM PDT 24 36186706733 ps
T350 /workspace/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.3796457169 Jul 21 06:38:01 PM PDT 24 Jul 21 06:40:36 PM PDT 24 55629780386 ps
T302 /workspace/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2887013778 Jul 21 06:38:39 PM PDT 24 Jul 21 06:39:15 PM PDT 24 131571326565 ps
T439 /workspace/coverage/default/31.sysrst_ctrl_alert_test.1867710464 Jul 21 06:38:51 PM PDT 24 Jul 21 06:38:57 PM PDT 24 2012473063 ps
T197 /workspace/coverage/default/45.sysrst_ctrl_stress_all.1181003042 Jul 21 06:39:23 PM PDT 24 Jul 21 06:39:43 PM PDT 24 8223444463 ps
T440 /workspace/coverage/default/10.sysrst_ctrl_stress_all.1496092578 Jul 21 06:38:00 PM PDT 24 Jul 21 06:38:06 PM PDT 24 6455010163 ps
T97 /workspace/coverage/default/37.sysrst_ctrl_stress_all.2886265808 Jul 21 06:38:59 PM PDT 24 Jul 21 06:40:38 PM PDT 24 323160425557 ps
T441 /workspace/coverage/default/18.sysrst_ctrl_smoke.3813354012 Jul 21 06:38:13 PM PDT 24 Jul 21 06:38:17 PM PDT 24 2118539957 ps
T442 /workspace/coverage/default/15.sysrst_ctrl_in_out_inverted.2882219489 Jul 21 06:38:12 PM PDT 24 Jul 21 06:38:17 PM PDT 24 2474587334 ps
T303 /workspace/coverage/default/42.sysrst_ctrl_stress_all.1742487954 Jul 21 06:39:18 PM PDT 24 Jul 21 06:39:46 PM PDT 24 16419313471 ps
T443 /workspace/coverage/default/14.sysrst_ctrl_pin_override_test.1994072561 Jul 21 06:38:17 PM PDT 24 Jul 21 06:38:21 PM PDT 24 2518652717 ps
T352 /workspace/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2652894971 Jul 21 06:39:40 PM PDT 24 Jul 21 06:39:56 PM PDT 24 61152999545 ps
T444 /workspace/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.194849968 Jul 21 06:39:29 PM PDT 24 Jul 21 06:39:39 PM PDT 24 4805625481 ps
T445 /workspace/coverage/default/3.sysrst_ctrl_combo_detect.4279048172 Jul 21 06:37:47 PM PDT 24 Jul 21 06:39:26 PM PDT 24 146354629357 ps
T446 /workspace/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2065274087 Jul 21 06:39:20 PM PDT 24 Jul 21 06:39:29 PM PDT 24 3305414887 ps
T167 /workspace/coverage/default/25.sysrst_ctrl_edge_detect.3315717686 Jul 21 06:38:41 PM PDT 24 Jul 21 06:38:45 PM PDT 24 5609979588 ps
T142 /workspace/coverage/default/16.sysrst_ctrl_edge_detect.1524893443 Jul 21 06:38:08 PM PDT 24 Jul 21 06:38:11 PM PDT 24 4110177023 ps
T447 /workspace/coverage/default/32.sysrst_ctrl_pin_override_test.1076441401 Jul 21 06:38:47 PM PDT 24 Jul 21 06:38:56 PM PDT 24 2510355327 ps
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