Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
881 |
1 |
|
|
T7 |
12 |
|
T22 |
11 |
|
T10 |
11 |
| auto[1] |
879 |
1 |
|
|
T7 |
8 |
|
T22 |
9 |
|
T10 |
9 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
877 |
1 |
|
|
T7 |
7 |
|
T22 |
8 |
|
T10 |
11 |
| auto[1] |
883 |
1 |
|
|
T7 |
13 |
|
T22 |
12 |
|
T10 |
9 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
851 |
1 |
|
|
T7 |
11 |
|
T22 |
13 |
|
T10 |
11 |
| auto[1] |
909 |
1 |
|
|
T7 |
9 |
|
T22 |
7 |
|
T10 |
9 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
884 |
1 |
|
|
T7 |
10 |
|
T22 |
12 |
|
T10 |
8 |
| auto[1] |
876 |
1 |
|
|
T7 |
10 |
|
T22 |
8 |
|
T10 |
12 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
901 |
1 |
|
|
T7 |
11 |
|
T22 |
10 |
|
T10 |
11 |
| auto[1] |
859 |
1 |
|
|
T7 |
9 |
|
T22 |
10 |
|
T10 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
853 |
1 |
|
|
T7 |
7 |
|
T22 |
9 |
|
T10 |
11 |
| auto[1] |
907 |
1 |
|
|
T7 |
13 |
|
T22 |
11 |
|
T10 |
9 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
868 |
1 |
|
|
T7 |
7 |
|
T22 |
8 |
|
T10 |
12 |
| auto[1] |
892 |
1 |
|
|
T7 |
13 |
|
T22 |
12 |
|
T10 |
8 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
876 |
1 |
|
|
T7 |
13 |
|
T22 |
8 |
|
T10 |
9 |
| auto[1] |
884 |
1 |
|
|
T7 |
7 |
|
T22 |
12 |
|
T10 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T7 |
10 |
|
T22 |
11 |
|
T10 |
9 |
| auto[1] |
867 |
1 |
|
|
T7 |
10 |
|
T22 |
9 |
|
T10 |
11 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
887 |
1 |
|
|
T7 |
13 |
|
T22 |
11 |
|
T10 |
11 |
| auto[1] |
873 |
1 |
|
|
T7 |
7 |
|
T22 |
9 |
|
T10 |
9 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
881 |
1 |
|
|
T7 |
10 |
|
T22 |
12 |
|
T10 |
9 |
| auto[1] |
879 |
1 |
|
|
T7 |
10 |
|
T22 |
8 |
|
T10 |
11 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
867 |
1 |
|
|
T7 |
13 |
|
T22 |
9 |
|
T10 |
10 |
| auto[1] |
893 |
1 |
|
|
T7 |
7 |
|
T22 |
11 |
|
T10 |
10 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
906 |
1 |
|
|
T7 |
11 |
|
T22 |
10 |
|
T10 |
12 |
| auto[1] |
854 |
1 |
|
|
T7 |
9 |
|
T22 |
10 |
|
T10 |
8 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
877 |
1 |
|
|
T7 |
7 |
|
T22 |
8 |
|
T10 |
11 |
| auto[1] |
883 |
1 |
|
|
T7 |
13 |
|
T22 |
12 |
|
T10 |
9 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
904 |
1 |
|
|
T7 |
10 |
|
T22 |
9 |
|
T10 |
13 |
| auto[1] |
856 |
1 |
|
|
T7 |
10 |
|
T22 |
11 |
|
T10 |
7 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
861 |
1 |
|
|
T7 |
7 |
|
T22 |
4 |
|
T10 |
12 |
| auto[1] |
899 |
1 |
|
|
T7 |
13 |
|
T22 |
16 |
|
T10 |
8 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
891 |
1 |
|
|
T7 |
10 |
|
T22 |
10 |
|
T10 |
12 |
| auto[1] |
869 |
1 |
|
|
T7 |
10 |
|
T22 |
10 |
|
T10 |
8 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
889 |
1 |
|
|
T7 |
14 |
|
T22 |
7 |
|
T10 |
8 |
| auto[1] |
871 |
1 |
|
|
T7 |
6 |
|
T22 |
13 |
|
T10 |
12 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
882 |
1 |
|
|
T7 |
9 |
|
T22 |
7 |
|
T10 |
11 |
| auto[1] |
878 |
1 |
|
|
T7 |
11 |
|
T22 |
13 |
|
T10 |
9 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
902 |
1 |
|
|
T7 |
11 |
|
T22 |
9 |
|
T10 |
14 |
| auto[1] |
858 |
1 |
|
|
T7 |
9 |
|
T22 |
11 |
|
T10 |
6 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
893 |
1 |
|
|
T7 |
11 |
|
T22 |
6 |
|
T10 |
10 |
| auto[1] |
867 |
1 |
|
|
T7 |
9 |
|
T22 |
14 |
|
T10 |
10 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
862 |
1 |
|
|
T7 |
11 |
|
T22 |
10 |
|
T10 |
10 |
| auto[1] |
898 |
1 |
|
|
T7 |
9 |
|
T22 |
10 |
|
T10 |
10 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
914 |
1 |
|
|
T7 |
10 |
|
T22 |
13 |
|
T10 |
6 |
| auto[1] |
846 |
1 |
|
|
T7 |
10 |
|
T22 |
7 |
|
T10 |
14 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
867 |
1 |
|
|
T7 |
13 |
|
T22 |
9 |
|
T10 |
10 |
| auto[1] |
893 |
1 |
|
|
T7 |
7 |
|
T22 |
11 |
|
T10 |
10 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
442 |
1 |
|
|
T7 |
7 |
|
T22 |
5 |
|
T10 |
6 |
| auto[0] |
auto[1] |
462 |
1 |
|
|
T7 |
3 |
|
T22 |
4 |
|
T10 |
7 |
| auto[1] |
auto[0] |
409 |
1 |
|
|
T7 |
4 |
|
T22 |
8 |
|
T10 |
5 |
| auto[1] |
auto[1] |
447 |
1 |
|
|
T7 |
6 |
|
T22 |
3 |
|
T10 |
2 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
437 |
1 |
|
|
T7 |
5 |
|
T22 |
2 |
|
T10 |
4 |
| auto[0] |
auto[1] |
424 |
1 |
|
|
T7 |
2 |
|
T22 |
2 |
|
T10 |
8 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T7 |
5 |
|
T22 |
10 |
|
T10 |
4 |
| auto[1] |
auto[1] |
452 |
1 |
|
|
T7 |
8 |
|
T22 |
6 |
|
T10 |
4 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
471 |
1 |
|
|
T7 |
5 |
|
T22 |
6 |
|
T10 |
6 |
| auto[0] |
auto[1] |
420 |
1 |
|
|
T7 |
5 |
|
T22 |
4 |
|
T10 |
6 |
| auto[1] |
auto[0] |
430 |
1 |
|
|
T7 |
6 |
|
T22 |
4 |
|
T10 |
5 |
| auto[1] |
auto[1] |
439 |
1 |
|
|
T7 |
4 |
|
T22 |
6 |
|
T10 |
3 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
446 |
1 |
|
|
T7 |
5 |
|
T22 |
4 |
|
T10 |
4 |
| auto[0] |
auto[1] |
443 |
1 |
|
|
T7 |
9 |
|
T22 |
3 |
|
T10 |
4 |
| auto[1] |
auto[0] |
407 |
1 |
|
|
T7 |
2 |
|
T22 |
5 |
|
T10 |
7 |
| auto[1] |
auto[1] |
464 |
1 |
|
|
T7 |
4 |
|
T22 |
8 |
|
T10 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
439 |
1 |
|
|
T7 |
5 |
|
T22 |
2 |
|
T10 |
6 |
| auto[0] |
auto[1] |
443 |
1 |
|
|
T7 |
4 |
|
T22 |
5 |
|
T10 |
5 |
| auto[1] |
auto[0] |
429 |
1 |
|
|
T7 |
2 |
|
T22 |
6 |
|
T10 |
6 |
| auto[1] |
auto[1] |
449 |
1 |
|
|
T7 |
9 |
|
T22 |
7 |
|
T10 |
3 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
453 |
1 |
|
|
T7 |
9 |
|
T22 |
3 |
|
T10 |
6 |
| auto[0] |
auto[1] |
449 |
1 |
|
|
T7 |
2 |
|
T22 |
6 |
|
T10 |
8 |
| auto[1] |
auto[0] |
423 |
1 |
|
|
T7 |
4 |
|
T22 |
5 |
|
T10 |
3 |
| auto[1] |
auto[1] |
435 |
1 |
|
|
T7 |
5 |
|
T22 |
6 |
|
T10 |
3 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
442 |
1 |
|
|
T7 |
8 |
|
T22 |
5 |
|
T10 |
6 |
| auto[0] |
auto[1] |
420 |
1 |
|
|
T7 |
3 |
|
T22 |
5 |
|
T10 |
4 |
| auto[1] |
auto[0] |
445 |
1 |
|
|
T7 |
5 |
|
T22 |
6 |
|
T10 |
5 |
| auto[1] |
auto[1] |
453 |
1 |
|
|
T7 |
4 |
|
T22 |
4 |
|
T10 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
465 |
1 |
|
|
T7 |
6 |
|
T22 |
7 |
|
T10 |
3 |
| auto[0] |
auto[1] |
449 |
1 |
|
|
T7 |
4 |
|
T22 |
6 |
|
T10 |
3 |
| auto[1] |
auto[0] |
416 |
1 |
|
|
T7 |
4 |
|
T22 |
5 |
|
T10 |
6 |
| auto[1] |
auto[1] |
430 |
1 |
|
|
T7 |
6 |
|
T22 |
2 |
|
T10 |
8 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
434 |
1 |
|
|
T7 |
7 |
|
T22 |
5 |
|
T10 |
6 |
| auto[0] |
auto[1] |
472 |
1 |
|
|
T7 |
4 |
|
T22 |
5 |
|
T10 |
6 |
| auto[1] |
auto[0] |
447 |
1 |
|
|
T7 |
5 |
|
T22 |
6 |
|
T10 |
5 |
| auto[1] |
auto[1] |
407 |
1 |
|
|
T7 |
4 |
|
T22 |
4 |
|
T10 |
3 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
877 |
1 |
|
|
T7 |
7 |
|
T22 |
8 |
|
T10 |
11 |
| auto[1] |
auto[1] |
883 |
1 |
|
|
T7 |
13 |
|
T22 |
12 |
|
T10 |
9 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
435 |
1 |
|
|
T7 |
5 |
|
T22 |
2 |
|
T10 |
7 |
| auto[0] |
auto[1] |
458 |
1 |
|
|
T7 |
6 |
|
T22 |
4 |
|
T10 |
3 |
| auto[1] |
auto[0] |
458 |
1 |
|
|
T7 |
5 |
|
T22 |
9 |
|
T10 |
2 |
| auto[1] |
auto[1] |
409 |
1 |
|
|
T7 |
4 |
|
T22 |
5 |
|
T10 |
8 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
867 |
1 |
|
|
T7 |
13 |
|
T22 |
9 |
|
T10 |
10 |
| auto[1] |
auto[1] |
893 |
1 |
|
|
T7 |
7 |
|
T22 |
11 |
|
T10 |
10 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
161 |
1 |
|
|
T10 |
9 |
|
T37 |
12 |
|
T108 |
14 |
| auto[1] |
139 |
1 |
|
|
T10 |
11 |
|
T37 |
8 |
|
T108 |
6 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
156 |
1 |
|
|
T10 |
10 |
|
T37 |
9 |
|
T108 |
10 |
| auto[1] |
144 |
1 |
|
|
T10 |
10 |
|
T37 |
11 |
|
T108 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
145 |
1 |
|
|
T10 |
15 |
|
T37 |
6 |
|
T108 |
9 |
| auto[1] |
155 |
1 |
|
|
T10 |
5 |
|
T37 |
14 |
|
T108 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
153 |
1 |
|
|
T10 |
9 |
|
T37 |
6 |
|
T108 |
10 |
| auto[1] |
147 |
1 |
|
|
T10 |
11 |
|
T37 |
14 |
|
T108 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
162 |
1 |
|
|
T10 |
12 |
|
T37 |
8 |
|
T108 |
11 |
| auto[1] |
138 |
1 |
|
|
T10 |
8 |
|
T37 |
12 |
|
T108 |
9 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
149 |
1 |
|
|
T10 |
6 |
|
T37 |
9 |
|
T108 |
9 |
| auto[1] |
151 |
1 |
|
|
T10 |
14 |
|
T37 |
11 |
|
T108 |
11 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T10 |
7 |
|
T37 |
12 |
|
T108 |
10 |
| auto[1] |
157 |
1 |
|
|
T10 |
13 |
|
T37 |
8 |
|
T108 |
10 |
Summary for Variable cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
151 |
1 |
|
|
T10 |
8 |
|
T37 |
10 |
|
T108 |
9 |
| auto[1] |
149 |
1 |
|
|
T10 |
12 |
|
T37 |
10 |
|
T108 |
11 |
Summary for Variable cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T10 |
12 |
|
T37 |
12 |
|
T108 |
8 |
| auto[1] |
135 |
1 |
|
|
T10 |
8 |
|
T37 |
8 |
|
T108 |
12 |
Summary for Variable cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
145 |
1 |
|
|
T10 |
10 |
|
T37 |
9 |
|
T108 |
8 |
| auto[1] |
155 |
1 |
|
|
T10 |
10 |
|
T37 |
11 |
|
T108 |
12 |
Summary for Variable cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
141 |
1 |
|
|
T10 |
9 |
|
T37 |
8 |
|
T108 |
8 |
| auto[1] |
159 |
1 |
|
|
T10 |
11 |
|
T37 |
12 |
|
T108 |
12 |
Summary for Variable cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T10 |
11 |
|
T37 |
12 |
|
T108 |
14 |
| auto[1] |
135 |
1 |
|
|
T10 |
9 |
|
T37 |
8 |
|
T108 |
6 |
Summary for Variable cp_ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
150 |
1 |
|
|
T10 |
8 |
|
T37 |
9 |
|
T108 |
12 |
| auto[1] |
150 |
1 |
|
|
T10 |
12 |
|
T37 |
11 |
|
T108 |
8 |
Summary for Variable cp_bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
156 |
1 |
|
|
T10 |
10 |
|
T37 |
9 |
|
T108 |
10 |
| auto[1] |
144 |
1 |
|
|
T10 |
10 |
|
T37 |
11 |
|
T108 |
10 |
Summary for Variable cp_key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
158 |
1 |
|
|
T10 |
7 |
|
T37 |
11 |
|
T108 |
9 |
| auto[1] |
142 |
1 |
|
|
T10 |
13 |
|
T37 |
9 |
|
T108 |
11 |
Summary for Variable cp_key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
140 |
1 |
|
|
T10 |
7 |
|
T37 |
7 |
|
T108 |
10 |
| auto[1] |
160 |
1 |
|
|
T10 |
13 |
|
T37 |
13 |
|
T108 |
10 |
Summary for Variable cp_key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
152 |
1 |
|
|
T10 |
7 |
|
T37 |
10 |
|
T108 |
6 |
| auto[1] |
148 |
1 |
|
|
T10 |
13 |
|
T37 |
10 |
|
T108 |
14 |
Summary for Variable cp_key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
147 |
1 |
|
|
T10 |
9 |
|
T37 |
11 |
|
T108 |
10 |
| auto[1] |
153 |
1 |
|
|
T10 |
11 |
|
T37 |
9 |
|
T108 |
10 |
Summary for Variable cp_key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
137 |
1 |
|
|
T10 |
9 |
|
T37 |
8 |
|
T108 |
9 |
| auto[1] |
163 |
1 |
|
|
T10 |
11 |
|
T37 |
12 |
|
T108 |
11 |
Summary for Variable cp_key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_key2_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
143 |
1 |
|
|
T10 |
8 |
|
T37 |
6 |
|
T108 |
12 |
| auto[1] |
157 |
1 |
|
|
T10 |
12 |
|
T37 |
14 |
|
T108 |
8 |
Summary for Variable cp_lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_lid_open
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
157 |
1 |
|
|
T10 |
11 |
|
T37 |
10 |
|
T108 |
11 |
| auto[1] |
143 |
1 |
|
|
T10 |
9 |
|
T37 |
10 |
|
T108 |
9 |
Summary for Variable cp_pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
136 |
1 |
|
|
T10 |
6 |
|
T37 |
13 |
|
T108 |
12 |
| auto[1] |
164 |
1 |
|
|
T10 |
14 |
|
T37 |
7 |
|
T108 |
8 |
Summary for Variable cp_pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_pwrb_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
154 |
1 |
|
|
T10 |
11 |
|
T37 |
12 |
|
T108 |
8 |
| auto[1] |
146 |
1 |
|
|
T10 |
9 |
|
T37 |
8 |
|
T108 |
12 |
Summary for Variable cp_z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cp_z3_wakeup
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
165 |
1 |
|
|
T10 |
11 |
|
T37 |
12 |
|
T108 |
14 |
| auto[1] |
135 |
1 |
|
|
T10 |
9 |
|
T37 |
8 |
|
T108 |
6 |
Summary for Cross key0_inXval
Samples crossed: cp_key0_in cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_inXval
Bins
| cp_key0_in | cfg.vif.key0_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
79 |
1 |
|
|
T10 |
6 |
|
T37 |
5 |
|
T108 |
2 |
| auto[0] |
auto[1] |
79 |
1 |
|
|
T10 |
1 |
|
T37 |
6 |
|
T108 |
7 |
| auto[1] |
auto[0] |
66 |
1 |
|
|
T10 |
9 |
|
T37 |
1 |
|
T108 |
7 |
| auto[1] |
auto[1] |
76 |
1 |
|
|
T10 |
4 |
|
T37 |
8 |
|
T108 |
4 |
Summary for Cross key0_outXval
Samples crossed: cp_key0_out cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key0_outXval
Bins
| cp_key0_out | cfg.vif.key0_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
74 |
1 |
|
|
T10 |
3 |
|
T37 |
3 |
|
T108 |
3 |
| auto[0] |
auto[1] |
66 |
1 |
|
|
T10 |
4 |
|
T37 |
4 |
|
T108 |
7 |
| auto[1] |
auto[0] |
79 |
1 |
|
|
T10 |
6 |
|
T37 |
3 |
|
T108 |
7 |
| auto[1] |
auto[1] |
81 |
1 |
|
|
T10 |
7 |
|
T37 |
10 |
|
T108 |
3 |
Summary for Cross key1_inXval
Samples crossed: cp_key1_in cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_inXval
Bins
| cp_key1_in | cfg.vif.key1_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
85 |
1 |
|
|
T10 |
3 |
|
T37 |
3 |
|
T108 |
3 |
| auto[0] |
auto[1] |
67 |
1 |
|
|
T10 |
4 |
|
T37 |
7 |
|
T108 |
3 |
| auto[1] |
auto[0] |
77 |
1 |
|
|
T10 |
9 |
|
T37 |
5 |
|
T108 |
8 |
| auto[1] |
auto[1] |
71 |
1 |
|
|
T10 |
4 |
|
T37 |
5 |
|
T108 |
6 |
Summary for Cross key1_outXval
Samples crossed: cp_key1_out cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key1_outXval
Bins
| cp_key1_out | cfg.vif.key1_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T10 |
1 |
|
T37 |
4 |
|
T108 |
4 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T10 |
8 |
|
T37 |
7 |
|
T108 |
6 |
| auto[1] |
auto[0] |
73 |
1 |
|
|
T10 |
5 |
|
T37 |
5 |
|
T108 |
5 |
| auto[1] |
auto[1] |
80 |
1 |
|
|
T10 |
6 |
|
T37 |
4 |
|
T108 |
5 |
Summary for Cross key2_inXval
Samples crossed: cp_key2_in cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_inXval
Bins
| cp_key2_in | cfg.vif.key2_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
69 |
1 |
|
|
T10 |
3 |
|
T37 |
5 |
|
T108 |
5 |
| auto[0] |
auto[1] |
68 |
1 |
|
|
T10 |
6 |
|
T37 |
3 |
|
T108 |
4 |
| auto[1] |
auto[0] |
74 |
1 |
|
|
T10 |
4 |
|
T37 |
7 |
|
T108 |
5 |
| auto[1] |
auto[1] |
89 |
1 |
|
|
T10 |
7 |
|
T37 |
5 |
|
T108 |
6 |
Summary for Cross key2_outXval
Samples crossed: cp_key2_out cfg.vif.key2_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for key2_outXval
Bins
| cp_key2_out | cfg.vif.key2_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
76 |
1 |
|
|
T10 |
3 |
|
T37 |
3 |
|
T108 |
6 |
| auto[0] |
auto[1] |
67 |
1 |
|
|
T10 |
5 |
|
T37 |
3 |
|
T108 |
6 |
| auto[1] |
auto[0] |
75 |
1 |
|
|
T10 |
5 |
|
T37 |
7 |
|
T108 |
3 |
| auto[1] |
auto[1] |
82 |
1 |
|
|
T10 |
7 |
|
T37 |
7 |
|
T108 |
5 |
Summary for Cross pwrb_inXval
Samples crossed: cp_pwrb_in cfg.vif.pwrb_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_inXval
Bins
| cp_pwrb_in | cfg.vif.pwrb_in | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
60 |
1 |
|
|
T10 |
3 |
|
T37 |
7 |
|
T108 |
5 |
| auto[0] |
auto[1] |
76 |
1 |
|
|
T10 |
3 |
|
T37 |
6 |
|
T108 |
7 |
| auto[1] |
auto[0] |
85 |
1 |
|
|
T10 |
7 |
|
T37 |
2 |
|
T108 |
3 |
| auto[1] |
auto[1] |
79 |
1 |
|
|
T10 |
7 |
|
T37 |
5 |
|
T108 |
5 |
Summary for Cross pwrb_outXval
Samples crossed: cp_pwrb_out cfg.vif.pwrb_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for pwrb_outXval
Bins
| cp_pwrb_out | cfg.vif.pwrb_out | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
67 |
1 |
|
|
T10 |
5 |
|
T37 |
6 |
|
T108 |
3 |
| auto[0] |
auto[1] |
87 |
1 |
|
|
T10 |
6 |
|
T37 |
6 |
|
T108 |
5 |
| auto[1] |
auto[0] |
74 |
1 |
|
|
T10 |
4 |
|
T37 |
2 |
|
T108 |
5 |
| auto[1] |
auto[1] |
72 |
1 |
|
|
T10 |
5 |
|
T37 |
6 |
|
T108 |
7 |
Summary for Cross ac_presentXval
Samples crossed: cp_ac_present cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for ac_presentXval
Bins
| cp_ac_present | cfg.vif.ac_present | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
79 |
1 |
|
|
T10 |
1 |
|
T37 |
5 |
|
T108 |
10 |
| auto[0] |
auto[1] |
71 |
1 |
|
|
T10 |
7 |
|
T37 |
4 |
|
T108 |
2 |
| auto[1] |
auto[0] |
82 |
1 |
|
|
T10 |
8 |
|
T37 |
7 |
|
T108 |
4 |
| auto[1] |
auto[1] |
68 |
1 |
|
|
T10 |
4 |
|
T37 |
4 |
|
T108 |
4 |
Summary for Cross bat_disableXval
Samples crossed: cp_bat_disable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for bat_disableXval
Bins
| cp_bat_disable | cfg.vif.bat_disable | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
156 |
1 |
|
|
T10 |
10 |
|
T37 |
9 |
|
T108 |
10 |
| auto[1] |
auto[1] |
144 |
1 |
|
|
T10 |
10 |
|
T37 |
11 |
|
T108 |
10 |
User Defined Cross Bins for bat_disableXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Cross lid_openXval
Samples crossed: cp_lid_open cfg.vif.lid_open
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
4 |
0 |
4 |
100.00 |
|
Automatically Generated Cross Bins for lid_openXval
Bins
| cp_lid_open | cfg.vif.lid_open | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
91 |
1 |
|
|
T10 |
10 |
|
T37 |
7 |
|
T108 |
5 |
| auto[0] |
auto[1] |
66 |
1 |
|
|
T10 |
1 |
|
T37 |
3 |
|
T108 |
6 |
| auto[1] |
auto[0] |
74 |
1 |
|
|
T10 |
2 |
|
T37 |
5 |
|
T108 |
3 |
| auto[1] |
auto[1] |
69 |
1 |
|
|
T10 |
7 |
|
T37 |
5 |
|
T108 |
6 |
Summary for Cross z3_wakeupXval
Samples crossed: cp_z3_wakeup cfg.vif.z3_wakeup
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| TOTAL |
2 |
0 |
2 |
100.00 |
|
| Automatically Generated Cross Bins |
2 |
0 |
2 |
100.00 |
|
| User Defined Cross Bins |
0 |
0 |
0 |
|
|
Automatically Generated Cross Bins for z3_wakeupXval
Bins
| cp_z3_wakeup | cfg.vif.z3_wakeup | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
auto[0] |
165 |
1 |
|
|
T10 |
11 |
|
T37 |
12 |
|
T108 |
14 |
| auto[1] |
auto[1] |
135 |
1 |
|
|
T10 |
9 |
|
T37 |
8 |
|
T108 |
6 |
User Defined Cross Bins for z3_wakeupXval
Excluded/Illegal bins
| NAME | COUNT | STATUS |
| invalid0 |
0 |
Excluded |
| invalid1 |
0 |
Excluded |
Summary for Variable cfg.vif.ac_present
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.ac_present
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
51 |
1 |
|
|
T37 |
11 |
|
T108 |
9 |
|
T153 |
9 |
| auto[1] |
49 |
1 |
|
|
T37 |
9 |
|
T108 |
11 |
|
T153 |
11 |
Summary for Variable cfg.vif.bat_disable
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.bat_disable
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
48 |
1 |
|
|
T37 |
7 |
|
T108 |
13 |
|
T153 |
10 |
| auto[1] |
52 |
1 |
|
|
T37 |
13 |
|
T108 |
7 |
|
T153 |
10 |
Summary for Variable cfg.vif.key0_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
54 |
1 |
|
|
T37 |
12 |
|
T108 |
12 |
|
T153 |
9 |
| auto[1] |
46 |
1 |
|
|
T37 |
8 |
|
T108 |
8 |
|
T153 |
11 |
Summary for Variable cfg.vif.key0_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key0_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
48 |
1 |
|
|
T37 |
11 |
|
T108 |
9 |
|
T153 |
10 |
| auto[1] |
52 |
1 |
|
|
T37 |
9 |
|
T108 |
11 |
|
T153 |
10 |
Summary for Variable cfg.vif.key1_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
44 |
1 |
|
|
T37 |
12 |
|
T108 |
10 |
|
T153 |
4 |
| auto[1] |
56 |
1 |
|
|
T37 |
8 |
|
T108 |
10 |
|
T153 |
16 |
Summary for Variable cfg.vif.key1_out
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key1_out
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
63 |
1 |
|
|
T37 |
8 |
|
T108 |
16 |
|
T153 |
12 |
| auto[1] |
37 |
1 |
|
|
T37 |
12 |
|
T108 |
4 |
|
T153 |
8 |
Summary for Variable cfg.vif.key2_in
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for cfg.vif.key2_in
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
52 |
1 |
|
|
T37 |
11 |
|
T108 |
12 |
|
T153 |
10 |
| auto[1] |
48 |
1 |
|
|
T37 |
9 |
|
T108 |
8 |
|
T153 |
10 |