Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
91.46	91.46	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	91.46	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
91.46	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	7	55	88.71

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	7	24	77.42	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1659

1

T1

15

T3

1

T8

31

auto[1]

593

1

T1

5

T8

9

T9

17

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1625

1

T1

17

T3

1

T8

40

auto[1]

627

1

T1

3

T9

9

T11

1

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1753

1

T1

20

T8

40

T9

16

auto[1]

499

1

T3

1

T9

12

T11

6

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1723

1

T1

15

T3

1

T8

22

auto[1]

529

1

T1

5

T8

18

T9

4

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2088

1

T1

17

T3

1

T8

40

auto[1]

164

1

T1

3

T12

1

T13

5

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2087

1

T1

13

T3

1

T8

31

auto[1]

165

1

T1

7

T8

9

T10

1

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2069

1

T1

16

T3

1

T8

31

auto[1]

183

1

T1

4

T8

9

T10

1

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2063

1

T1

17

T3

1

T8

40

auto[1]

189

1

T1

3

T10

1

T13

5

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1991

1

T1

20

T3

1

T8

22

auto[1]

261

1

T8

18

T12

1

T13

5

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1761

1

T1

15

T8

40

T9

20

auto[1]

491

1

T1

5

T3

1

T9

8

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	7	24	77.42	7
Automatically Generated Cross Bins	31	7	24	77.42	7
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Element holes

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[auto[0]]	[auto[1]]	*	[auto[1]]	--	--	2

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[0]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel

cp_precondition_key1_in_sel

cp_precondition_key2_in_sel

cp_precondition_pwrb_in_sel

cp_precondition_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[0]

848

1

T3

1

T9

28

T11

8

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

30

1

T12

1

T106

1

T282

5

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

61

1

T12

1

T49

4

T229

6

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

33

1

T50

1

T298

4

T389

28

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

75

1

T1

3

T49

2

T82

8

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T51

2

T390

4

T379

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

27

1

T391

11

T392

2

T393

1

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

6

1

T386

2

T388

4

-

-

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

40

1

T50

1

T120

3

T229

12

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

21

1

T229

7

T282

2

T390

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

21

1

T8

4

T298

2

T278

1

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

13

1

T212

1

T83

3

T288

5

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

6

1

T394

6

-

-

-

-

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T278

1

T395

5

T391

6

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T83

1

T288

2

-

-

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

44

1

T13

1

T120

1

T395

4

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

13

1

T1

3

T396

4

T397

2

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

26

1

T8

3

T50

1

T398

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

11

1

T51

3

T399

1

T387

3

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

3

1

T390

1

T192

2

-

-

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

13

1

T1

4

T400

1

T83

8

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

2

1

T49

1

T298

1

-

-

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

3

1

T394

3

-

-

-

-

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

4

1

T10

1

T398

2

T401

1

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

119

1

T49

2

T150

13

T278

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

77

1

T1

2

T10

1

T13

1

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

43

1

T9

7

T34

3

T300

3

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

121

1

T8

3

T49

4

T50

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

60

1

T1

2

T8

4

T11

2

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

51

1

T1

3

T150

3

T128

4

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

21

1

T47

1

T376

4

T41

1

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

84

1

T9

10

T51

2

T389

14

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

44

1

T47

1

T51

3

T39

2

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

26

1

T3

1

T390

4

T300

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

31

1

T120

2

T109

2

T378

4

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

44

1

T11

5

T50

1

T333

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

16

1

T9

2

T290

2

T398

2

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

7

1

T100

1

T376

3

T41

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T286

1

T266

1

T338

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

120

1

T150

10

T39

2

T278

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

82

1

T1

3

T9

7

T377

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

55

1

T376

6

T107

5

T282

5

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

31

1

T47

1

T376

3

T34

1

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

61

1

T289

6

T206

7

T181

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

12

1

T9

1

T128

2

T382

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

16

1

T9

1

T377

3

T335

2

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

10

1

T402

2

T157

1

T382

1

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

65

1

T12

1

T34

2

T298

4

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

33

1

T150

3

T379

2

T212

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

9

1

T377

2

T403

1

T404

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

27

1

T34

1

T289

1

T405

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

33

1

T12

1

T99

8

T106

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

10

1

T107

1

T291

1

T404

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T11

1

T80

3

T104

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

3

1

T99

1

T206

1

T406

1

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded