Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T5

7

T23

11

T67

8

auto[1]

1059

1

T5

13

T23

9

T67

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

498

1

T5

5

T23

6

T67

5

from_0to1

495

1

T5

5

T23

6

T67

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1107

1

T5

13

T23

9

T67

10

auto[1]

1033

1

T5

7

T23

11

T67

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1067

1

T5

7

T23

10

T67

10

auto[1]

1073

1

T5

13

T23

10

T67

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T23

1

T67

1

T3

1

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T3

1

T47

1

T95

1

auto[0]

from_1to0

auto[1]

auto[0]

67

1

T23

2

T3

2

T47

1

auto[0]

from_1to0

auto[1]

auto[1]

53

1

T5

1

T67

2

T3

1

auto[0]

from_0to1

auto[0]

auto[0]

60

1

T23

1

T253

1

T115

2

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T5

1

T3

1

T95

2

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T23

1

T67

1

T3

1

auto[0]

from_0to1

auto[1]

auto[1]

63

1

T23

1

T3

2

T95

1

auto[1]

from_1to0

auto[0]

auto[0]

67

1

T5

2

T3

1

T47

1

auto[1]

from_1to0

auto[0]

auto[1]

61

1

T5

1

T23

2

T67

1

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T67

1

T3

1

T95

1

auto[1]

from_1to0

auto[1]

auto[1]

70

1

T5

1

T23

1

T47

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T5

1

T23

1

T67

1

auto[1]

from_0to1

auto[0]

auto[1]

68

1

T5

2

T67

1

T3

1

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T5

1

T23

1

T67

2

auto[1]

from_0to1

auto[1]

auto[1]

67

1

T23

1

T47

1

T95

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1081

1

T5

9

T23

10

T67

13

auto[1]

1059

1

T5

11

T23

10

T67

7

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

511

1

T5

6

T23

3

T67

5

from_0to1

503

1

T5

6

T23

3

T67

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T5

4

T23

15

T67

11

auto[1]

1065

1

T5

16

T23

5

T67

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088

1

T5

8

T23

6

T67

7

auto[1]

1052

1

T5

12

T23

14

T67

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

64

1

T253

1

T422

1

T343

1

auto[0]

from_1to0

auto[0]

auto[1]

60

1

T23

1

T67

2

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T5

3

T3

1

T47

1

auto[0]

from_1to0

auto[1]

auto[1]

62

1

T5

1

T67

1

T95

1

auto[0]

from_0to1

auto[0]

auto[0]

75

1

T23

1

T67

1

T3

2

auto[0]

from_0to1

auto[0]

auto[1]

59

1

T23

1

T67

1

T3

2

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T3

1

T47

1

T422

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T5

2

T3

1

T253

2

auto[1]

from_1to0

auto[0]

auto[0]

66

1

T3

2

T47

1

T422

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T23

1

T3

1

T95

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T5

1

T23

1

T67

2

auto[1]

from_1to0

auto[1]

auto[1]

62

1

T5

1

T3

2

T47

1

auto[1]

from_0to1

auto[0]

auto[0]

64

1

T47

1

T95

1

T422

1

auto[1]

from_0to1

auto[0]

auto[1]

62

1

T5

3

T23

1

T67

1

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T67

1

T3

1

T95

1

auto[1]

from_0to1

auto[1]

auto[1]

57

1

T5

1

T67

1

T47

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1063

1

T5

13

T23

10

T67

14

auto[1]

1077

1

T5

7

T23

10

T67

6

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

502

1

T5

4

T23

4

T67

5

from_0to1

500

1

T5

5

T23

4

T67

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1080

1

T5

9

T23

8

T67

10

auto[1]

1060

1

T5

11

T23

12

T67

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T5

12

T23

9

T67

12

auto[1]

1069

1

T5

8

T23

11

T67

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T5

1

T67

1

T253

2

auto[0]

from_1to0

auto[0]

auto[1]

71

1

T67

1

T3

1

T95

1

auto[0]

from_1to0

auto[1]

auto[0]

61

1

T5

1

T23

1

T3

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T23

1

T67

1

T3

3

auto[0]

from_0to1

auto[0]

auto[0]

57

1

T5

1

T23

1

T253

1

auto[0]

from_0to1

auto[0]

auto[1]

55

1

T5

1

T23

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

74

1

T5

1

T67

1

T422

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T47

1

T253

1

T422

1

auto[1]

from_1to0

auto[0]

auto[0]

50

1

T253

3

T39

1

T115

2

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T5

2

T47

1

T422

2

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T67

1

T3

1

T47

2

auto[1]

from_1to0

auto[1]

auto[1]

61

1

T23

2

T67

1

T3

2

auto[1]

from_0to1

auto[0]

auto[0]

66

1

T23

1

T67

1

T3

2

auto[1]

from_0to1

auto[0]

auto[1]

60

1

T23

1

T3

3

T95

2

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T5

1

T3

1

T95

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T5

1

T67

1

T3

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1090

1

T5

11

T23

9

T67

8

auto[1]

1050

1

T5

9

T23

11

T67

12

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

506

1

T5

5

T23

3

T67

5

from_0to1

501

1

T5

5

T23

4

T67

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1101

1

T5

10

T23

9

T67

11

auto[1]

1039

1

T5

10

T23

11

T67

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1040

1

T5

11

T23

10

T67

9

auto[1]

1100

1

T5

9

T23

10

T67

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

52

1

T5

2

T3

2

T47

1

auto[0]

from_1to0

auto[0]

auto[1]

58

1

T67

1

T3

1

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T5

1

T422

1

T39

1

auto[0]

from_1to0

auto[1]

auto[1]

70

1

T23

1

T67

1

T95

2

auto[0]

from_0to1

auto[0]

auto[0]

64

1

T5

1

T23

1

T3

1

auto[0]

from_0to1

auto[0]

auto[1]

75

1

T67

1

T3

1

T47

1

auto[0]

from_0to1

auto[1]

auto[0]

62

1

T67

1

T3

1

T253

1

auto[0]

from_0to1

auto[1]

auto[1]

52

1

T5

1

T23

1

T67

1

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T5

1

T23

1

T3

2

auto[1]

from_1to0

auto[0]

auto[1]

70

1

T23

1

T67

3

T3

1

auto[1]

from_1to0

auto[1]

auto[0]

59

1

T3

2

T47

1

T253

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T5

1

T3

1

T47

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T5

1

T47

2

T95

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T5

1

T3

1

T422

1

auto[1]

from_0to1

auto[1]

auto[0]

58

1

T5

1

T23

1

T67

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T23

1

T3

2

T47

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1108

1

T5

11

T23

14

T67

6

auto[1]

1032

1

T5

9

T23

6

T67

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

519

1

T5

3

T23

4

T67

4

from_0to1

511

1

T5

2

T23

4

T67

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T5

12

T23

11

T67

12

auto[1]

1069

1

T5

8

T23

9

T67

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1077

1

T5

10

T23

11

T67

9

auto[1]

1063

1

T5

10

T23

9

T67

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

74

1

T3

2

T95

1

T253

1

auto[0]

from_1to0

auto[0]

auto[1]

72

1

T5

1

T23

1

T3

1

auto[0]

from_1to0

auto[1]

auto[0]

68

1

T23

1

T3

2

T95

2

auto[0]

from_1to0

auto[1]

auto[1]

65

1

T23

2

T67

1

T3

1

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T67

1

T3

3

T115

2

auto[0]

from_0to1

auto[0]

auto[1]

60

1

T23

1

T3

2

T47

1

auto[0]

from_0to1

auto[1]

auto[0]

70

1

T5

1

T67

1

T47

1

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T23

1

T67

1

T3

1

auto[1]

from_1to0

auto[0]

auto[0]

65

1

T67

2

T3

1

T47

1

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T5

1

T3

2

T47

1

auto[1]

from_1to0

auto[1]

auto[0]

55

1

T67

1

T3

2

T95

1

auto[1]

from_1to0

auto[1]

auto[1]

66

1

T5

1

T3

1

T95

1

auto[1]

from_0to1

auto[0]

auto[0]

59

1

T5

1

T23

2

T3

2

auto[1]

from_0to1

auto[0]

auto[1]

69

1

T67

1

T3

2

T47

1

auto[1]

from_0to1

auto[1]

auto[0]

70

1

T3

3

T47

1

T95

1

auto[1]

from_0to1

auto[1]

auto[1]

49

1

T253

1

T39

1

T342

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1077

1

T5

10

T23

10

T67

9

auto[1]

1063

1

T5

10

T23

10

T67

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

529

1

T5

6

T23

7

T67

4

from_0to1

525

1

T5

5

T23

7

T67

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1090

1

T5

10

T23

10

T67

11

auto[1]

1050

1

T5

10

T23

10

T67

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1086

1

T5

4

T23

12

T67

13

auto[1]

1054

1

T5

16

T23

8

T67

7

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

75

1

T23

1

T67

1

T3

1

auto[0]

from_1to0

auto[0]

auto[1]

54

1

T5

1

T23

1

T3

1

auto[0]

from_1to0

auto[1]

auto[0]

65

1

T23

3

T3

1

T47

2

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T5

1

T23

1

T3

2

auto[0]

from_0to1

auto[0]

auto[0]

67

1

T23

2

T3

1

T47

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T5

1

T95

1

T422

1

auto[0]

from_0to1

auto[1]

auto[0]

61

1

T23

1

T67

2

T3

1

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T5

1

T23

1

T67

1

auto[1]

from_1to0

auto[0]

auto[0]

57

1

T5

1

T67

1

T3

3

auto[1]

from_1to0

auto[0]

auto[1]

58

1

T5

1

T67

1

T95

1

auto[1]

from_1to0

auto[1]

auto[0]

71

1

T253

1

T343

2

T34

2

auto[1]

from_1to0

auto[1]

auto[1]

80

1

T5

2

T23

1

T67

1

auto[1]

from_0to1

auto[0]

auto[0]

70

1

T23

2

T3

1

T47

1

auto[1]

from_0to1

auto[0]

auto[1]

61

1

T5

2

T3

3

T253

1

auto[1]

from_0to1

auto[1]

auto[0]

76

1

T67

1

T3

1

T253

1

auto[1]

from_0to1

auto[1]

auto[1]

64

1

T5

1

T23

1

T47

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1071

1

T5

9

T23

10

T67

10

auto[1]

1069

1

T5

11

T23

10

T67

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

510

1

T5

7

T23

4

T67

5

from_0to1

515

1

T5

8

T23

5

T67

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T5

7

T23

8

T67

12

auto[1]

1065

1

T5

13

T23

12

T67

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1049

1

T5

9

T23

7

T67

7

auto[1]

1091

1

T5

11

T23

13

T67

13

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

45

1

T23

1

T95

1

T39

2

auto[0]

from_1to0

auto[0]

auto[1]

61

1

T5

2

T3

2

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

72

1

T5

1

T23

1

T3

2

auto[0]

from_1to0

auto[1]

auto[1]

67

1

T23

1

T67

2

T47

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T5

1

T3

2

T95

2

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T5

1

T23

1

T67

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T5

1

T23

1

T3

2

auto[0]

from_0to1

auto[1]

auto[1]

61

1

T5

1

T67

1

T47

2

auto[1]

from_1to0

auto[0]

auto[0]

76

1

T5

1

T67

1

T3

2

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T23

1

T67

2

T3

1

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T5

1

T3

1

T47

1

auto[1]

from_1to0

auto[1]

auto[1]

63

1

T5

2

T47

1

T126

2

auto[1]

from_0to1

auto[0]

auto[0]

55

1

T23

1

T3

2

T47

1

auto[1]

from_0to1

auto[0]

auto[1]

72

1

T23

2

T67

2

T3

1

auto[1]

from_0to1

auto[1]

auto[0]

69

1

T5

2

T3

1

T39

1

auto[1]

from_0to1

auto[1]

auto[1]

55

1

T5

2

T67

1

T253

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1088

1

T5

8

T23

8

T67

9

auto[1]

1052

1

T5

12

T23

12

T67

11

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

514

1

T5

5

T23

4

T67

4

from_0to1

529

1

T5

6

T23

4

T67

3

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1065

1

T5

9

T23

6

T67

7

auto[1]

1075

1

T5

11

T23

14

T67

13

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T5

11

T23

11

T67

10

auto[1]

1065

1

T5

9

T23

9

T67

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

58

1

T5

1

T3

2

T95

1

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T5

2

T3

1

T47

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T23

1

T67

1

T95

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T67

1

T3

3

T39

1

auto[0]

from_0to1

auto[0]

auto[0]

70

1

T67

1

T422

1

T39

1

auto[0]

from_0to1

auto[0]

auto[1]

61

1

T5

1

T67

1

T47

1

auto[0]

from_0to1

auto[1]

auto[0]

78

1

T5

1

T67

1

T3

3

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T23

2

T3

2

T253

1

auto[1]

from_1to0

auto[0]

auto[0]

64

1

T23

1

T67

1

T3

1

auto[1]

from_1to0

auto[0]

auto[1]

79

1

T23

1

T422

1

T39

1

auto[1]

from_1to0

auto[1]

auto[0]

69

1

T23

1

T3

1

T95

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T5

2

T67

1

T3

3

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T5

2

T3

1

T95

1

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T23

1

T3

3

T47

1

auto[1]

from_0to1

auto[1]

auto[0]

51

1

T5

2

T3

2

T39

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T23

1

T95

1

T253

1