Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	145492	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

111016

1

T4

15

T5

50

T6

22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	130828	1			T4	22		T5	62		T6	22
values[0x0]	62608	1			T4	13		T5	34		T6	13
values[0x1]	63072	1			T4	10		T5	27		T6	9

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	118121	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

138387

1

T4

22

T5

59

T6

25

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	829	1			T18	1		T67	4		T3	5
valid_sources[0x01]	1054	1			T23	1		T3	3		T8	4
valid_sources[0x02]	780	1			T5	1		T3	4		T9	9
valid_sources[0x03]	740	1			T5	1		T3	3		T9	1
valid_sources[0x04]	851	1			T5	1		T23	1		T2	1
valid_sources[0x05]	763	1			T5	1		T3	7		T8	4
valid_sources[0x06]	903	1			T2	1		T3	2		T9	6
valid_sources[0x07]	1300	1			T3	1		T9	14		T47	1
valid_sources[0x08]	682	1			T5	1		T23	1		T14	1
valid_sources[0x09]	1892	1			T3	3		T69	1		T9	8
valid_sources[0x0a]	811	1			T3	7		T8	4		T9	10
valid_sources[0x0b]	822	1			T5	1		T23	2		T67	5
valid_sources[0x0c]	1032	1			T3	10		T68	2		T9	3
valid_sources[0x0d]	630	1			T2	1		T3	2		T68	2
valid_sources[0x0e]	892	1			T2	1		T3	4		T69	1
valid_sources[0x0f]	835	1			T5	2		T67	4		T8	19
valid_sources[0x10]	1065	1			T21	2		T3	3		T8	3
valid_sources[0x11]	944	1			T3	7		T9	6		T76	1
valid_sources[0x12]	713	1			T23	2		T3	3		T9	4
valid_sources[0x13]	1038	1			T5	1		T2	1		T3	10
valid_sources[0x14]	1255	1			T5	1		T23	5		T3	4
valid_sources[0x15]	1747	1			T3	4		T9	6		T55	3
valid_sources[0x16]	763	1			T5	4		T23	1		T3	1
valid_sources[0x17]	818	1			T23	1		T8	8		T9	8
valid_sources[0x18]	780	1			T5	1		T66	1		T3	4
valid_sources[0x19]	1134	1			T69	1		T9	6		T49	5
valid_sources[0x1a]	786	1			T23	1		T68	7		T9	3
valid_sources[0x1b]	845	1			T5	1		T67	1		T3	3
valid_sources[0x1c]	990	1			T5	1		T67	1		T45	1
valid_sources[0x1d]	831	1			T3	1		T9	1		T47	1
valid_sources[0x1e]	1675	1			T23	2		T3	1		T8	21
valid_sources[0x1f]	1044	1			T23	2		T21	10		T3	12
valid_sources[0x20]	832	1			T3	3		T9	10		T47	2
valid_sources[0x21]	2653	1			T3	2		T68	2		T8	10
valid_sources[0x22]	795	1			T3	7		T9	5		T13	5
valid_sources[0x23]	706	1			T5	1		T23	2		T66	2
valid_sources[0x24]	782	1			T23	1		T3	2		T9	2
valid_sources[0x25]	1036	1			T66	1		T67	1		T3	2
valid_sources[0x26]	901	1			T3	3		T8	18		T9	4
valid_sources[0x27]	804	1			T3	9		T69	1		T9	3
valid_sources[0x28]	755	1			T3	8		T68	1		T9	7
valid_sources[0x29]	2105	1			T5	1		T23	2		T8	4
valid_sources[0x2a]	841	1			T3	3		T69	1		T9	6
valid_sources[0x2b]	765	1			T5	2		T3	1		T9	6
valid_sources[0x2c]	678	1			T18	2		T3	1		T8	8
valid_sources[0x2d]	865	1			T5	1		T18	1		T3	7
valid_sources[0x2e]	729	1			T23	1		T3	7		T49	10
valid_sources[0x2f]	813	1			T23	2		T8	12		T9	7
valid_sources[0x30]	896	1			T1	82		T3	3		T8	5
valid_sources[0x31]	851	1			T69	1		T9	4		T71	1
valid_sources[0x32]	813	1			T5	1		T23	1		T67	4
valid_sources[0x33]	995	1			T67	1		T9	6		T47	2
valid_sources[0x34]	744	1			T5	1		T2	1		T3	7
valid_sources[0x35]	798	1			T3	6		T69	1		T8	2
valid_sources[0x36]	941	1			T23	1		T3	1		T45	1
valid_sources[0x37]	737	1			T5	1		T68	5		T8	37
valid_sources[0x38]	715	1			T5	1		T21	1		T67	2
valid_sources[0x39]	812	1			T3	1		T69	1		T8	24
valid_sources[0x3a]	1756	1			T5	1		T8	5		T9	8
valid_sources[0x3b]	887	1			T23	1		T3	1		T8	3
valid_sources[0x3c]	716	1			T3	7		T8	8		T9	4
valid_sources[0x3d]	821	1			T3	6		T8	17		T9	6
valid_sources[0x3e]	1461	1			T3	7		T9	3		T47	6
valid_sources[0x3f]	2136	1			T5	1		T3	2		T8	26
valid_sources[0x40]	1017	1			T66	1		T3	5		T45	1
valid_sources[0x41]	759	1			T5	1		T23	1		T2	1
valid_sources[0x42]	846	1			T5	2		T23	1		T3	1
valid_sources[0x43]	765	1			T9	2		T13	1		T49	3
valid_sources[0x44]	1342	1			T3	10		T8	3		T9	10
valid_sources[0x45]	676	1			T5	1		T21	8		T67	1
valid_sources[0x46]	845	1			T3	6		T69	2		T9	2
valid_sources[0x47]	900	1			T3	2		T13	17		T50	1
valid_sources[0x48]	1540	1			T5	1		T21	2		T3	10
valid_sources[0x49]	717	1			T5	2		T21	4		T67	2
valid_sources[0x4a]	801	1			T5	1		T67	1		T3	3
valid_sources[0x4b]	1391	1			T3	6		T69	1		T8	4
valid_sources[0x4c]	876	1			T23	2		T17	45		T3	2
valid_sources[0x4d]	743	1			T5	1		T23	1		T24	17
valid_sources[0x4e]	742	1			T3	2		T8	6		T47	3
valid_sources[0x4f]	810	1			T5	1		T69	1		T8	4
valid_sources[0x50]	738	1			T3	7		T9	2		T47	1
valid_sources[0x51]	689	1			T5	1		T23	2		T75	5
valid_sources[0x52]	805	1			T67	2		T3	11		T69	1
valid_sources[0x53]	889	1			T75	5		T9	6		T71	1
valid_sources[0x54]	1595	1			T23	1		T67	2		T3	4
valid_sources[0x55]	713	1			T5	1		T3	4		T9	4
valid_sources[0x56]	1012	1			T3	2		T9	13		T76	1
valid_sources[0x57]	1381	1			T3	1		T9	11		T47	3
valid_sources[0x58]	1053	1			T19	15		T66	1		T3	2
valid_sources[0x59]	864	1			T9	4		T71	1		T47	2
valid_sources[0x5a]	2189	1			T67	1		T3	4		T8	3
valid_sources[0x5b]	773	1			T5	1		T3	7		T9	9
valid_sources[0x5c]	1017	1			T5	3		T23	1		T45	1
valid_sources[0x5d]	1884	1			T5	1		T3	1		T69	1
valid_sources[0x5e]	792	1			T66	1		T3	11		T9	2
valid_sources[0x5f]	806	1			T5	1		T67	2		T8	1
valid_sources[0x60]	671	1			T23	2		T9	3		T47	1
valid_sources[0x61]	739	1			T67	1		T3	2		T9	3
valid_sources[0x62]	777	1			T5	1		T23	3		T3	5
valid_sources[0x63]	1335	1			T5	1		T3	3		T9	5
valid_sources[0x64]	814	1			T8	10		T9	3		T47	1
valid_sources[0x65]	794	1			T5	1		T23	2		T3	6
valid_sources[0x66]	923	1			T67	5		T9	4		T13	14
valid_sources[0x67]	791	1			T23	1		T21	2		T3	2
valid_sources[0x68]	840	1			T2	1		T3	2		T8	4
valid_sources[0x69]	1445	1			T23	1		T3	6		T8	3
valid_sources[0x6a]	738	1			T5	1		T23	1		T67	2
valid_sources[0x6b]	1464	1			T23	1		T75	4		T9	8
valid_sources[0x6c]	984	1			T3	1		T75	1		T9	5
valid_sources[0x6d]	1108	1			T5	1		T1	4		T3	6
valid_sources[0x6e]	933	1			T67	3		T3	1		T9	4
valid_sources[0x6f]	1373	1			T3	2		T69	1		T8	3
valid_sources[0x70]	881	1			T3	4		T71	1		T47	2
valid_sources[0x71]	749	1			T5	1		T3	8		T9	6
valid_sources[0x72]	957	1			T4	45		T5	1		T23	1
valid_sources[0x73]	786	1			T3	10		T8	15		T9	5
valid_sources[0x74]	1056	1			T3	10		T7	1		T68	2
valid_sources[0x75]	1015	1			T5	1		T23	4		T9	7
valid_sources[0x76]	1302	1			T5	1		T23	2		T3	9
valid_sources[0x77]	1829	1			T3	4		T9	2		T76	2
valid_sources[0x78]	795	1			T5	1		T23	2		T3	14
valid_sources[0x79]	1048	1			T8	18		T75	1		T9	1
valid_sources[0x7a]	716	1			T3	3		T69	1		T9	7
valid_sources[0x7b]	1621	1			T5	1		T20	794		T3	14
valid_sources[0x7c]	1082	1			T3	2		T8	39		T45	1
valid_sources[0x7d]	918	1			T5	1		T3	1		T69	1
valid_sources[0x7e]	831	1			T5	1		T45	1		T9	2
valid_sources[0x7f]	892	1			T2	1		T3	4		T45	1
valid_sources[0x80]	1426	1			T21	2		T3	2		T68	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

59623

1

T4

10

T5

36

T6

12

values[0x0]

all_enables

biggest_size

30145

1

T4

3

T5

11

T6

8

values[0x1]

all_enables

biggest_size

21248

1

T4

2

T5

3

T6

2