Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1313527755	9200	0	0
auto_block_debounce_ctl_rd_A	1313527755	1767	0	0
auto_block_out_ctl_rd_A	1313527755	2160	0	0
com_det_ctl_0_rd_A	1313527755	3154	0	0
com_det_ctl_1_rd_A	1313527755	3083	0	0
com_det_ctl_2_rd_A	1313527755	3299	0	0
com_det_ctl_3_rd_A	1313527755	2995	0	0
com_out_ctl_0_rd_A	1313527755	3692	0	0
com_out_ctl_1_rd_A	1313527755	3675	0	0
com_out_ctl_2_rd_A	1313527755	3522	0	0
com_out_ctl_3_rd_A	1313527755	3588	0	0
com_pre_det_ctl_0_rd_A	1313527755	1125	0	0
com_pre_det_ctl_1_rd_A	1313527755	1324	0	0
com_pre_det_ctl_2_rd_A	1313527755	1170	0	0
com_pre_det_ctl_3_rd_A	1313527755	1169	0	0
com_pre_sel_ctl_0_rd_A	1313527755	3531	0	0
com_pre_sel_ctl_1_rd_A	1313527755	3549	0	0
com_pre_sel_ctl_2_rd_A	1313527755	3799	0	0
com_pre_sel_ctl_3_rd_A	1313527755	3758	0	0
com_sel_ctl_0_rd_A	1313527755	3689	0	0
com_sel_ctl_1_rd_A	1313527755	3663	0	0
com_sel_ctl_2_rd_A	1313527755	3673	0	0
com_sel_ctl_3_rd_A	1313527755	3775	0	0
ec_rst_ctl_rd_A	1313527755	1963	0	0
intr_enable_rd_A	1313527755	1834	0	0
key_intr_ctl_rd_A	1313527755	3493	0	0
key_intr_debounce_ctl_rd_A	1313527755	1225	0	0
key_invert_ctl_rd_A	1313527755	5664	0	0
pin_allowed_ctl_rd_A	1313527755	5335	0	0
pin_out_ctl_rd_A	1313527755	4545	0	0
pin_out_value_rd_A	1313527755	4316	0	0
regwen_rd_A	1313527755	1382	0	0
ulp_ac_debounce_ctl_rd_A	1313527755	1325	0	0
ulp_ctl_rd_A	1313527755	1271	0	0
ulp_lid_debounce_ctl_rd_A	1313527755	1273	0	0
ulp_pwrb_debounce_ctl_rd_A	1313527755	1278	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	9200	0	0
T3	156941	17	0	0
T7	64293	0	0	0
T8	342782	0	0	0
T34	0	5	0	0
T39	0	14	0	0
T40	0	7	0	0
T45	521685	0	0	0
T46	33879	0	0	0
T47	0	6	0	0
T52	0	4	0	0
T60	72271	0	0	0
T64	0	6	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T70	246776	0	0	0
T75	29087	0	0	0
T130	0	9	0	0
T335	0	11	0	0
T336	0	5	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1767	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	61	0	0
T40	0	38	0	0
T52	242888	22	0	0
T62	205104	0	0	0
T73	219718	0	0	0
T74	246321	0	0	0
T84	0	9	0	0
T119	0	11	0	0
T122	0	6	0	0
T131	0	9	0	0
T200	59747	0	0	0
T202	0	12	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	31	0	0
T337	0	3	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	2160	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	60	0	0
T40	0	19	0	0
T43	0	6	0	0
T52	242888	23	0	0
T62	205104	0	0	0
T73	219718	0	0	0
T74	246321	0	0	0
T119	0	6	0	0
T122	0	7	0	0
T131	0	9	0	0
T200	59747	0	0	0
T202	0	15	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	19	0	0
T337	0	9	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3154	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	61	0	0
T9	0	100	0	0
T20	353252	26	0	0
T21	100440	0	0	0
T34	0	50	0	0
T50	0	23	0	0
T52	0	8	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	66	0	0
T82	0	30	0	0
T100	0	52	0	0
T128	0	68	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3083	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	49	0	0
T9	0	71	0	0
T20	353252	38	0	0
T21	100440	0	0	0
T34	0	37	0	0
T50	0	40	0	0
T52	0	6	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	94	0	0
T82	0	61	0	0
T100	0	60	0	0
T128	0	82	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3299	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	43	0	0
T9	0	95	0	0
T20	353252	18	0	0
T21	100440	0	0	0
T34	0	42	0	0
T50	0	26	0	0
T52	0	22	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	66	0	0
T82	0	26	0	0
T100	0	65	0	0
T128	0	48	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	2995	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	50	0	0
T9	0	65	0	0
T20	353252	30	0	0
T21	100440	0	0	0
T34	0	39	0	0
T50	0	21	0	0
T52	0	16	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	53	0	0
T82	0	22	0	0
T100	0	58	0	0
T128	0	58	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3692	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	66	0	0
T9	0	66	0	0
T20	353252	25	0	0
T21	100440	0	0	0
T34	0	39	0	0
T50	0	59	0	0
T52	0	17	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	68	0	0
T82	0	42	0	0
T100	0	71	0	0
T128	0	75	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3675	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	55	0	0
T9	0	121	0	0
T20	353252	11	0	0
T21	100440	0	0	0
T34	0	61	0	0
T50	0	23	0	0
T52	0	4	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	79	0	0
T82	0	49	0	0
T100	0	81	0	0
T128	0	49	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3522	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	66	0	0
T9	0	82	0	0
T20	353252	25	0	0
T21	100440	0	0	0
T34	0	41	0	0
T50	0	36	0	0
T52	0	20	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	65	0	0
T82	0	49	0	0
T100	0	77	0	0
T128	0	77	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3588	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	46	0	0
T9	0	84	0	0
T20	353252	47	0	0
T21	100440	0	0	0
T34	0	31	0	0
T50	0	27	0	0
T52	0	19	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	74	0	0
T82	0	27	0	0
T100	0	81	0	0
T128	0	60	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1125	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	15	0	0
T43	0	12	0	0
T52	242888	7	0	0
T62	205104	0	0	0
T73	219718	0	0	0
T74	246321	0	0	0
T200	59747	0	0	0
T202	0	23	0	0
T261	0	23	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	14	0	0
T338	0	17	0	0
T339	0	29	0	0
T340	0	12	0	0
T341	0	5	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1324	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	31	0	0
T40	0	3	0	0
T43	0	7	0	0
T52	242888	14	0	0
T62	205104	0	0	0
T73	219718	0	0	0
T74	246321	0	0	0
T122	0	22	0	0
T198	0	6	0	0
T200	59747	0	0	0
T202	0	17	0	0
T261	0	26	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	8	0	0
T338	0	32	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1170	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	29	0	0
T43	0	18	0	0
T52	242888	17	0	0
T62	205104	0	0	0
T73	219718	0	0	0
T74	246321	0	0	0
T200	59747	0	0	0
T202	0	8	0	0
T261	0	19	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	9	0	0
T338	0	26	0	0
T339	0	13	0	0
T340	0	1	0	0
T341	0	5	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1169	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	28	0	0
T43	0	10	0	0
T52	242888	13	0	0
T62	205104	0	0	0
T73	219718	0	0	0
T74	246321	0	0	0
T122	0	1	0	0
T198	0	2	0	0
T200	59747	0	0	0
T202	0	21	0	0
T261	0	18	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	18	0	0
T338	0	23	0	0
T339	0	17	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3531	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	46	0	0
T9	0	81	0	0
T20	353252	31	0	0
T21	100440	0	0	0
T34	0	40	0	0
T50	0	20	0	0
T52	0	13	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	61	0	0
T82	0	42	0	0
T100	0	92	0	0
T128	0	83	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3549	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	44	0	0
T9	0	55	0	0
T20	353252	19	0	0
T21	100440	0	0	0
T34	0	43	0	0
T50	0	41	0	0
T52	0	14	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	47	0	0
T82	0	37	0	0
T100	0	62	0	0
T128	0	76	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3799	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	56	0	0
T9	0	108	0	0
T20	353252	25	0	0
T21	100440	0	0	0
T34	0	27	0	0
T50	0	56	0	0
T52	0	12	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	62	0	0
T82	0	36	0	0
T100	0	68	0	0
T128	0	70	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3758	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	60	0	0
T9	0	64	0	0
T20	353252	33	0	0
T21	100440	0	0	0
T34	0	28	0	0
T50	0	48	0	0
T52	0	12	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	89	0	0
T82	0	26	0	0
T100	0	59	0	0
T128	0	65	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3689	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	52	0	0
T9	0	72	0	0
T20	353252	27	0	0
T21	100440	0	0	0
T34	0	63	0	0
T50	0	39	0	0
T52	0	12	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	82	0	0
T82	0	68	0	0
T100	0	70	0	0
T128	0	82	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3663	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	59	0	0
T9	0	91	0	0
T20	353252	17	0	0
T21	100440	0	0	0
T34	0	39	0	0
T50	0	26	0	0
T52	0	15	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	82	0	0
T82	0	50	0	0
T100	0	57	0	0
T128	0	71	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3673	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	62	0	0
T9	0	94	0	0
T20	353252	17	0	0
T21	100440	0	0	0
T34	0	35	0	0
T50	0	41	0	0
T52	0	12	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	78	0	0
T82	0	26	0	0
T100	0	82	0	0
T128	0	54	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3775	0	0
T2	114013	0	0	0
T3	156941	0	0	0
T7	64293	0	0	0
T8	0	70	0	0
T9	0	87	0	0
T20	353252	21	0	0
T21	100440	0	0	0
T34	0	46	0	0
T50	0	50	0	0
T52	0	11	0	0
T60	72271	0	0	0
T66	205410	0	0	0
T67	43106	0	0	0
T68	106930	0	0	0
T69	244908	0	0	0
T80	0	84	0	0
T82	0	48	0	0
T100	0	66	0	0
T128	0	54	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1963	0	0
T1	757169	0	0	0
T8	0	11	0	0
T9	0	68	0	0
T14	173097	0	0	0
T15	63177	0	0	0
T16	15305	0	0	0
T17	145460	0	0	0
T18	278477	0	0	0
T19	167933	0	0	0
T22	219524	1	0	0
T23	60717	0	0	0
T24	77795	0	0	0
T50	0	3	0	0
T52	0	23	0	0
T80	0	7	0	0
T82	0	13	0	0
T98	0	5	0	0
T100	0	32	0	0
T295	0	3	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1834	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	89	0	0
T40	0	22	0	0
T43	0	38	0	0
T52	242888	13	0	0
T62	205104	0	0	0
T73	219718	0	0	0
T74	246321	0	0	0
T122	0	14	0	0
T186	0	17	0	0
T200	59747	0	0	0
T202	0	11	0	0
T261	0	27	0	0
T289	0	19	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	18	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	3493	0	0
T30	288842	0	0	0
T31	96892	5	0	0
T34	0	23	0	0
T37	0	6	0	0
T38	0	5	0	0
T40	0	4	0	0
T52	242888	12	0	0
T54	0	69	0	0
T62	205104	0	0	0
T73	219718	0	0	0
T74	246321	0	0	0
T122	0	9	0	0
T200	59747	0	0	0
T202	0	29	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	19	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1225	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	13	0	0
T40	0	3	0	0
T43	0	12	0	0
T52	242888	7	0	0
T62	205104	0	0	0
T73	219718	0	0	0
T74	246321	0	0	0
T200	59747	0	0	0
T202	0	21	0	0
T261	0	25	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	11	0	0
T338	0	30	0	0
T339	0	17	0	0
T340	0	20	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	5664	0	0
T1	757169	0	0	0
T6	120434	91	0	0
T14	173097	0	0	0
T15	63177	0	0	0
T16	15305	0	0	0
T17	145460	0	0	0
T18	278477	0	0	0
T22	219524	0	0	0
T23	60717	0	0	0
T24	77795	0	0	0
T34	0	15	0	0
T40	0	102	0	0
T52	0	19	0	0
T71	0	59	0	0
T72	0	76	0	0
T74	0	43	0	0
T230	0	58	0	0
T336	0	76	0	0
T342	0	76	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	5335	0	0
T1	757169	0	0	0
T5	125938	52	0	0
T6	120434	0	0	0
T14	173097	0	0	0
T15	63177	0	0	0
T16	15305	0	0	0
T17	145460	0	0	0
T22	219524	0	0	0
T23	60717	78	0	0
T24	77795	0	0	0
T34	0	90	0	0
T40	0	156	0	0
T52	0	12	0	0
T253	0	67	0	0
T336	0	15	0	0
T342	0	84	0	0
T343	0	58	0	0
T344	0	69	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	4545	0	0
T1	757169	0	0	0
T5	125938	71	0	0
T6	120434	0	0	0
T14	173097	0	0	0
T15	63177	0	0	0
T16	15305	0	0	0
T17	145460	0	0	0
T22	219524	0	0	0
T23	60717	42	0	0
T24	77795	0	0	0
T34	0	76	0	0
T40	0	148	0	0
T52	0	18	0	0
T253	0	67	0	0
T336	0	3	0	0
T342	0	49	0	0
T343	0	36	0	0
T344	0	82	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	4316	0	0
T1	757169	0	0	0
T5	125938	63	0	0
T6	120434	0	0	0
T14	173097	0	0	0
T15	63177	0	0	0
T16	15305	0	0	0
T17	145460	0	0	0
T22	219524	0	0	0
T23	60717	81	0	0
T24	77795	0	0	0
T34	0	97	0	0
T40	0	135	0	0
T52	0	11	0	0
T253	0	69	0	0
T336	0	7	0	0
T342	0	81	0	0
T343	0	39	0	0
T344	0	53	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1382	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	19	0	0
T40	0	2	0	0
T43	0	17	0	0
T52	242888	11	0	0
T62	205104	0	0	0
T73	219718	0	0	0
T74	246321	0	0	0
T122	0	2	0	0
T198	0	3	0	0
T200	59747	0	0	0
T202	0	19	0	0
T261	0	36	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	17	0	0
T338	0	28	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1325	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	29	0	0
T40	0	3	0	0
T43	0	9	0	0
T52	242888	12	0	0
T62	205104	0	0	0
T73	219718	0	0	0
T74	246321	0	0	0
T87	0	12	0	0
T121	0	3	0	0
T122	0	3	0	0
T200	59747	0	0	0
T202	0	22	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	23	0	0
T345	0	3	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1271	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	40	0	0
T40	0	6	0	0
T52	242888	10	0	0
T61	62256	5	0	0
T77	400455	0	0	0
T87	0	6	0	0
T121	0	8	0	0
T122	0	2	0	0
T202	0	8	0	0
T294	250508	0	0	0
T295	176694	0	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	31	0	0
T345	0	8	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1273	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	26	0	0
T43	0	15	0	0
T52	242888	19	0	0
T61	62256	9	0	0
T77	400455	0	0	0
T87	0	7	0	0
T121	0	8	0	0
T122	0	2	0	0
T202	0	32	0	0
T294	250508	0	0	0
T295	176694	0	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	20	0	0
T346	0	2	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1313527755	1278	0	0
T30	288842	0	0	0
T31	96892	0	0	0
T34	0	22	0	0
T40	0	8	0	0
T43	0	14	0	0
T52	242888	28	0	0
T61	62256	14	0	0
T77	400455	0	0	0
T87	0	5	0	0
T121	0	4	0	0
T122	0	3	0	0
T202	0	23	0	0
T294	250508	0	0	0
T295	176694	0	0	0
T296	25945	0	0	0
T297	18853	0	0	0
T317	49614	0	0	0
T336	0	5	0	0