Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1051

1

T2

32

T18

12

T43

26

auto[1]

1009

1

T2

28

T18

8

T43

14

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

493

1

T2

15

T18

6

T43

9

from_0to1

479

1

T2

16

T18

5

T43

9

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T2

29

T18

9

T43

20

auto[1]

1041

1

T2

31

T18

11

T43

20

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1022

1

T2

35

T18

8

T43

20

auto[1]

1038

1

T2

25

T18

12

T43

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T2

1

T43

1

T61

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T2

2

T18

2

T43

2

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T2

2

T18

1

T43

2

auto[0]

from_1to0

auto[1]

auto[1]

69

1

T2

3

T18

1

T43

1

auto[0]

from_0to1

auto[0]

auto[0]

74

1

T2

2

T18

1

T43

2

auto[0]

from_0to1

auto[0]

auto[1]

50

1

T2

1

T18

2

T61

2

auto[0]

from_0to1

auto[1]

auto[0]

53

1

T2

3

T18

1

T43

3

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T2

1

T18

1

T43

2

auto[1]

from_1to0

auto[0]

auto[0]

56

1

T2

3

T61

1

T10

1

auto[1]

from_1to0

auto[0]

auto[1]

59

1

T18

1

T43

2

T10

4

auto[1]

from_1to0

auto[1]

auto[0]

50

1

T2

3

T18

1

T43

1

auto[1]

from_1to0

auto[1]

auto[1]

65

1

T2

1

T10

3

T251

1

auto[1]

from_0to1

auto[0]

auto[0]

57

1

T2

1

T251

1

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

64

1

T2

1

T43

1

T61

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T2

5

T43

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T2

2

T72

1

T102

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

984

1

T2

28

T18

12

T43

12

auto[1]

1076

1

T2

32

T18

8

T43

28

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

480

1

T2

12

T18

6

T43

11

from_0to1

486

1

T2

13

T18

5

T43

12

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1024

1

T2

31

T18

10

T43

24

auto[1]

1036

1

T2

29

T18

10

T43

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1031

1

T2

34

T18

10

T43

20

auto[1]

1029

1

T2

26

T18

10

T43

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

66

1

T2

2

T43

1

T61

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T2

1

T18

2

T43

1

auto[0]

from_1to0

auto[1]

auto[0]

48

1

T2

1

T43

1

T10

1

auto[0]

from_1to0

auto[1]

auto[1]

56

1

T2

3

T18

2

T61

2

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T2

2

T18

2

T10

1

auto[0]

from_0to1

auto[0]

auto[1]

51

1

T2

1

T43

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

66

1

T2

1

T43

1

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

64

1

T2

2

T18

2

T43

2

auto[1]

from_1to0

auto[0]

auto[0]

69

1

T2

1

T18

1

T43

3

auto[1]

from_1to0

auto[0]

auto[1]

65

1

T2

1

T43

3

T251

1

auto[1]

from_1to0

auto[1]

auto[0]

62

1

T2

2

T18

1

T43

2

auto[1]

from_1to0

auto[1]

auto[1]

52

1

T2

1

T10

1

T251

3

auto[1]

from_0to1

auto[0]

auto[0]

50

1

T2

2

T43

4

T72

1

auto[1]

from_0to1

auto[0]

auto[1]

77

1

T2

1

T43

1

T251

1

auto[1]

from_0to1

auto[1]

auto[0]

62

1

T2

3

T61

1

T10

3

auto[1]

from_0to1

auto[1]

auto[1]

58

1

T2

1

T18

1

T43

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T2

32

T18

8

T43

16

auto[1]

1041

1

T2

28

T18

12

T43

24

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

484

1

T2

14

T18

3

T43

10

from_0to1

484

1

T2

15

T18

2

T43

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1068

1

T2

32

T18

14

T43

17

auto[1]

992

1

T2

28

T18

6

T43

23

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

983

1

T2

32

T18

9

T43

16

auto[1]

1077

1

T2

28

T18

11

T43

24

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

57

1

T2

4

T10

1

T102

1

auto[0]

from_1to0

auto[0]

auto[1]

76

1

T2

2

T43

1

T10

1

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T2

2

T61

1

T10

3

auto[0]

from_1to0

auto[1]

auto[1]

51

1

T2

1

T43

1

T251

2

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T2

2

T18

2

T43

2

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T2

2

T10

2

T251

2

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T2

1

T61

2

T10

2

auto[0]

from_0to1

auto[1]

auto[1]

69

1

T2

1

T43

3

T61

1

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T2

1

T18

1

T43

1

auto[1]

from_1to0

auto[0]

auto[1]

77

1

T2

1

T18

2

T43

3

auto[1]

from_1to0

auto[1]

auto[0]

53

1

T2

3

T43

2

T61

1

auto[1]

from_1to0

auto[1]

auto[1]

56

1

T43

2

T10

1

T251

1

auto[1]

from_0to1

auto[0]

auto[0]

65

1

T2

5

T43

2

T61

1

auto[1]

from_0to1

auto[0]

auto[1]

51

1

T2

1

T43

1

T61

1

auto[1]

from_0to1

auto[1]

auto[0]

65

1

T2

3

T43

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

61

1

T43

1

T10

1

T132

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1039

1

T2

29

T18

10

T43

22

auto[1]

1021

1

T2

31

T18

10

T43

18

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

497

1

T2

14

T18

6

T43

8

from_0to1

489

1

T2

14

T18

5

T43

8

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1005

1

T2

32

T18

12

T43

24

auto[1]

1055

1

T2

28

T18

8

T43

16

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

999

1

T2

30

T18

10

T43

20

auto[1]

1061

1

T2

30

T18

10

T43

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

62

1

T2

1

T43

2

T10

2

auto[0]

from_1to0

auto[0]

auto[1]

64

1

T2

2

T18

1

T43

2

auto[0]

from_1to0

auto[1]

auto[0]

52

1

T2

3

T18

1

T43

1

auto[0]

from_1to0

auto[1]

auto[1]

76

1

T2

2

T18

1

T43

1

auto[0]

from_0to1

auto[0]

auto[0]

65

1

T2

1

T18

1

T43

2

auto[0]

from_0to1

auto[0]

auto[1]

68

1

T2

6

T18

1

T43

1

auto[0]

from_0to1

auto[1]

auto[0]

55

1

T2

1

T43

2

T61

1

auto[0]

from_0to1

auto[1]

auto[1]

51

1

T2

1

T18

1

T43

1

auto[1]

from_1to0

auto[0]

auto[0]

52

1

T2

2

T18

2

T10

2

auto[1]

from_1to0

auto[0]

auto[1]

54

1

T10

1

T72

1

T88

3

auto[1]

from_1to0

auto[1]

auto[0]

66

1

T2

3

T18

1

T43

1

auto[1]

from_1to0

auto[1]

auto[1]

71

1

T2

1

T43

1

T10

1

auto[1]

from_0to1

auto[0]

auto[0]

53

1

T18

1

T61

1

T72

2

auto[1]

from_0to1

auto[0]

auto[1]

71

1

T2

2

T18

1

T43

1

auto[1]

from_0to1

auto[1]

auto[0]

67

1

T2

2

T43

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T2

1

T130

1

T132

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1021

1

T2

27

T18

8

T43

22

auto[1]

1039

1

T2

33

T18

12

T43

18

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

496

1

T2

16

T18

4

T43

11

from_0to1

500

1

T2

16

T18

5

T43

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1029

1

T2

30

T18

9

T43

22

auto[1]

1031

1

T2

30

T18

11

T43

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1075

1

T2

32

T18

14

T43

18

auto[1]

985

1

T2

28

T18

6

T43

22

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

61

1

T2

2

T43

3

T10

2

auto[0]

from_1to0

auto[0]

auto[1]

68

1

T2

5

T43

3

T10

1

auto[0]

from_1to0

auto[1]

auto[0]

70

1

T18

1

T72

2

T130

2

auto[0]

from_1to0

auto[1]

auto[1]

60

1

T2

2

T43

2

T61

1

auto[0]

from_0to1

auto[0]

auto[0]

62

1

T2

2

T18

1

T43

1

auto[0]

from_0to1

auto[0]

auto[1]

56

1

T2

2

T43

2

T10

1

auto[0]

from_0to1

auto[1]

auto[0]

63

1

T2

1

T43

2

T10

1

auto[0]

from_0to1

auto[1]

auto[1]

56

1

T2

1

T18

2

T43

2

auto[1]

from_1to0

auto[0]

auto[0]

59

1

T2

2

T18

2

T43

1

auto[1]

from_1to0

auto[0]

auto[1]

56

1

T43

1

T61

2

T10

1

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T2

3

T18

1

T43

1

auto[1]

from_1to0

auto[1]

auto[1]

59

1

T2

2

T61

1

T10

4

auto[1]

from_0to1

auto[0]

auto[0]

76

1

T2

4

T18

1

T61

2

auto[1]

from_0to1

auto[0]

auto[1]

58

1

T2

2

T61

1

T10

2

auto[1]

from_0to1

auto[1]

auto[0]

60

1

T2

1

T18

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

69

1

T2

3

T43

3

T251

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1054

1

T2

29

T18

10

T43

18

auto[1]

1006

1

T2

31

T18

10

T43

22

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

507

1

T2

16

T18

5

T43

10

from_0to1

505

1

T2

16

T18

5

T43

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1025

1

T2

35

T18

8

T43

15

auto[1]

1035

1

T2

25

T18

12

T43

25

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1019

1

T2

23

T18

13

T43

20

auto[1]

1041

1

T2

37

T18

7

T43

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

56

1

T2

3

T43

1

T61

1

auto[0]

from_1to0

auto[0]

auto[1]

65

1

T2

2

T43

1

T61

1

auto[0]

from_1to0

auto[1]

auto[0]

60

1

T2

2

T18

2

T43

2

auto[0]

from_1to0

auto[1]

auto[1]

73

1

T2

2

T43

2

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

72

1

T2

2

T18

1

T43

1

auto[0]

from_0to1

auto[0]

auto[1]

64

1

T2

3

T43

2

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

57

1

T2

1

T61

1

T10

2

auto[0]

from_0to1

auto[1]

auto[1]

65

1

T2

2

T18

1

T43

1

auto[1]

from_1to0

auto[0]

auto[0]

61

1

T2

1

T61

1

T10

1

auto[1]

from_1to0

auto[0]

auto[1]

66

1

T2

2

T43

2

T10

1

auto[1]

from_1to0

auto[1]

auto[0]

68

1

T2

3

T18

1

T43

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T2

1

T18

2

T43

1

auto[1]

from_0to1

auto[0]

auto[0]

60

1

T2

2

T18

3

T43

1

auto[1]

from_0to1

auto[0]

auto[1]

56

1

T2

2

T61

1

T251

3

auto[1]

from_0to1

auto[1]

auto[0]

61

1

T43

4

T10

1

T102

1

auto[1]

from_0to1

auto[1]

auto[1]

70

1

T2

4

T43

1

T10

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1035

1

T2

27

T18

11

T43

24

auto[1]

1025

1

T2

33

T18

9

T43

16

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

496

1

T2

17

T18

6

T43

10

from_0to1

497

1

T2

17

T18

5

T43

10

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1002

1

T2

29

T18

8

T43

22

auto[1]

1058

1

T2

31

T18

12

T43

18

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1038

1

T2

29

T18

8

T43

19

auto[1]

1022

1

T2

31

T18

12

T43

21

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

59

1

T2

2

T18

1

T43

2

auto[0]

from_1to0

auto[0]

auto[1]

53

1

T2

1

T18

2

T43

1

auto[0]

from_1to0

auto[1]

auto[0]

63

1

T2

3

T18

1

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

78

1

T2

1

T18

1

T43

2

auto[0]

from_0to1

auto[0]

auto[0]

58

1

T2

3

T43

2

T72

1

auto[0]

from_0to1

auto[0]

auto[1]

62

1

T2

1

T18

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

64

1

T2

1

T18

1

T43

2

auto[0]

from_0to1

auto[1]

auto[1]

67

1

T2

1

T43

1

T10

2

auto[1]

from_1to0

auto[0]

auto[0]

60

1

T2

2

T43

4

T72

1

auto[1]

from_1to0

auto[0]

auto[1]

62

1

T2

3

T43

1

T10

3

auto[1]

from_1to0

auto[1]

auto[0]

63

1

T2

4

T18

1

T72

1

auto[1]

from_1to0

auto[1]

auto[1]

58

1

T2

1

T61

1

T10

3

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T2

1

T18

2

T43

1

auto[1]

from_0to1

auto[0]

auto[1]

55

1

T251

2

T102

1

T132

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T2

3

T43

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

66

1

T2

7

T18

1

T43

3

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1023

1

T2

30

T18

11

T43

19

auto[1]

1037

1

T2

30

T18

9

T43

21

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

480

1

T2

12

T18

5

T43

6

from_0to1

495

1

T2

13

T18

4

T43

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1010

1

T2

29

T18

13

T43

14

auto[1]

1050

1

T2

31

T18

7

T43

26

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

988

1

T2

21

T18

6

T43

20

auto[1]

1072

1

T2

39

T18

14

T43

20

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

54

1

T61

3

T130

3

T88

2

auto[0]

from_1to0

auto[0]

auto[1]

62

1

T2

2

T18

1

T43

2

auto[0]

from_1to0

auto[1]

auto[0]

55

1

T2

3

T43

1

T61

1

auto[0]

from_1to0

auto[1]

auto[1]

66

1

T2

3

T43

1

T10

1

auto[0]

from_0to1

auto[0]

auto[0]

59

1

T2

2

T18

2

T43

1

auto[0]

from_0to1

auto[0]

auto[1]

70

1

T2

2

T43

1

T61

1

auto[0]

from_0to1

auto[1]

auto[0]

65

1

T2

1

T61

1

T10

1

auto[0]

from_0to1

auto[1]

auto[1]

60

1

T2

1

T18

1

T43

3

auto[1]

from_1to0

auto[0]

auto[0]

49

1

T10

1

T251

2

T130

1

auto[1]

from_1to0

auto[0]

auto[1]

60

1

T2

1

T18

3

T10

1

auto[1]

from_1to0

auto[1]

auto[0]

65

1

T2

2

T18

1

T43

1

auto[1]

from_1to0

auto[1]

auto[1]

69

1

T2

1

T43

1

T130

1

auto[1]

from_0to1

auto[0]

auto[0]

61

1

T2

1

T18

1

T10

2

auto[1]

from_0to1

auto[0]

auto[1]

57

1

T2

2

T43

1

T72

1

auto[1]

from_0to1

auto[1]

auto[0]

64

1

T2

2

T43

1

T61

1

auto[1]

from_0to1

auto[1]

auto[1]

59

1

T2

2

T61

2

T10

1