Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	0	1
164	0	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T14,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T14,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T14,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T14,T2,T3
1	0	Covered	T4,T1,T13
1	1	Covered	T14,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T3
0	1	Covered	T2,T77,T94
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T2,T3
0	1	Covered	T14,T2,T3
1	0	Covered	T73,T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T2,T3
1	-	Covered	T14,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T2,T3
DetectSt	168	Covered	T14,T2,T3
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T14,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T2,T3
DebounceSt->IdleSt	163	Covered	T2,T3,T10
DetectSt->IdleSt	186	Covered	T2,T77,T94
DetectSt->StableSt	191	Covered	T14,T2,T3
IdleSt->DebounceSt	148	Covered	T14,T2,T3
StableSt->IdleSt	206	Covered	T14,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T14,T2,T3
0	1	Covered	T14,T2,T3
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T14,T2,T3
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T14,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T3,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T2,T77,T94
DetectSt	-	-	-	-	0	1	-	Covered	T14,T2,T3
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T14,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T14,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	266	0	0
CntIncr_A	8184812	119083	0	0
CntNoWrap_A	8184812	7524676	0	0
DetectStDropOut_A	8184812	3	0	0
DetectedOut_A	8184812	738	0	0
DetectedPulseOut_A	8184812	117	0	0
DisabledIdleSt_A	8184812	7399762	0	0
DisabledNoDetection_A	8184812	7402137	0	0
EnterDebounceSt_A	8184812	153	0	0
EnterDetectSt_A	8184812	120	0	0
EnterStableSt_A	8184812	117	0	0
PulseIsPulse_A	8184812	117	0	0
StayInStableSt	8184812	621	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8184812	6819	0	0
gen_low_level_sva.LowLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	115	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	266	0	0
T2	14635	9	0	0
T3	11546	6	0	0
T10	0	3	0	0
T14	708	4	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T43	8215	2	0	0
T44	0	4	0	0
T46	0	8	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	119083	0	0
T2	14635	356	0	0
T3	11546	327	0	0
T10	0	51	0	0
T14	708	72	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T43	8215	26	0	0
T44	0	106	0	0
T46	0	281	0	0
T47	0	20	0	0
T48	0	58	0	0
T49	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524676	0	0
T1	32514	32087	0	0
T2	14635	2988	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	303	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	3	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T77	0	1	0	0
T94	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	738	0	0
T2	14635	25	0	0
T3	11546	12	0	0
T10	0	3	0	0
T14	708	13	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T43	8215	6	0	0
T44	0	15	0	0
T46	0	24	0	0
T47	0	2	0	0
T49	0	6	0	0
T104	0	15	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	117	0	0
T2	14635	3	0	0
T3	11546	2	0	0
T10	0	1	0	0
T14	708	2	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T43	8215	1	0	0
T44	0	2	0	0
T46	0	4	0	0
T47	0	1	0	0
T49	0	1	0	0
T104	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7399762	0	0
T1	32514	32087	0	0
T2	14635	2413	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	148	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7402137	0	0
T1	32514	32101	0	0
T2	14635	2439	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	148	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	153	0	0
T2	14635	5	0	0
T3	11546	5	0	0
T10	0	2	0	0
T14	708	2	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T43	8215	1	0	0
T44	0	2	0	0
T46	0	4	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	120	0	0
T2	14635	4	0	0
T3	11546	2	0	0
T10	0	1	0	0
T14	708	2	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T43	8215	1	0	0
T44	0	2	0	0
T46	0	4	0	0
T47	0	1	0	0
T49	0	1	0	0
T104	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	117	0	0
T2	14635	3	0	0
T3	11546	2	0	0
T10	0	1	0	0
T14	708	2	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T43	8215	1	0	0
T44	0	2	0	0
T46	0	4	0	0
T47	0	1	0	0
T49	0	1	0	0
T104	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	117	0	0
T2	14635	3	0	0
T3	11546	2	0	0
T10	0	1	0	0
T14	708	2	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T43	8215	1	0	0
T44	0	2	0	0
T46	0	4	0	0
T47	0	1	0	0
T49	0	1	0	0
T104	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	621	0	0
T2	14635	22	0	0
T3	11546	10	0	0
T10	0	2	0	0
T14	708	11	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T43	8215	5	0	0
T44	0	13	0	0
T46	0	20	0	0
T47	0	1	0	0
T49	0	5	0	0
T104	0	12	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	6819	0	0
T1	32514	10	0	0
T2	14635	62	0	0
T3	0	42	0	0
T4	492	8	0	0
T5	551	0	0	0
T13	422	2	0	0
T14	708	3	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	8	0	0
T18	503	7	0	0
T19	0	6	0	0
T20	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	115	0	0
T2	14635	3	0	0
T3	11546	2	0	0
T10	0	1	0	0
T14	708	2	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T43	8215	1	0	0
T44	0	2	0	0
T46	0	4	0	0
T47	0	1	0	0
T49	0	1	0	0
T104	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T10
1	0	Covered	T4,T1,T13
1	1	Covered	T3,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T3,T11,T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Unreachable
1	0	Covered	T3,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T10
DetectSt	168	Covered	T3,T10,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T11
DebounceSt->IdleSt	163	Covered	T8,T11,T57
DetectSt->IdleSt	186	Covered	T3,T11,T84
DetectSt->StableSt	191	Covered	T3,T10,T11
IdleSt->DebounceSt	148	Covered	T3,T8,T10
StableSt->IdleSt	206	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T10
0	1	Covered	T3,T8,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T11,T57
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T3,T11,T84
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	197	0	0
CntIncr_A	8184812	443787	0	0
CntNoWrap_A	8184812	7524745	0	0
DetectStDropOut_A	8184812	24	0	0
DetectedOut_A	8184812	458039	0	0
DetectedPulseOut_A	8184812	49	0	0
DisabledIdleSt_A	8184812	5697991	0	0
DisabledNoDetection_A	8184812	5700427	0	0
EnterDebounceSt_A	8184812	125	0	0
EnterDetectSt_A	8184812	73	0	0
EnterStableSt_A	8184812	49	0	0
PulseIsPulse_A	8184812	49	0	0
StayInStableSt	8184812	457990	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8184812	6819	0	0
gen_low_level_sva.LowLevelEvent_A	8184812	7527380	0	0
gen_sticky_sva.StableStDropOut_A	8184812	463217	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	197	0	0
T3	11546	6	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	2	0	0
T10	0	2	0	0
T11	0	7	0	0
T25	8781	0	0	0
T34	0	2	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	3	0	0
T59	0	1	0	0
T60	0	4	0	0
T61	505	0	0	0
T69	0	2	0	0
T70	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	443787	0	0
T3	11546	182	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	170	0	0
T10	0	50	0	0
T11	0	376	0	0
T25	8781	0	0	0
T34	0	31	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	93096	0	0
T59	0	83	0	0
T60	0	88	0	0
T61	505	0	0	0
T69	0	83	0	0
T70	0	65	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524745	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	24	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T7	821	0	0	0
T11	0	2	0	0
T25	8781	0	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T61	505	0	0	0
T84	0	3	0	0
T111	0	4	0	0
T112	0	4	0	0
T113	0	2	0	0
T114	0	1	0	0
T115	0	2	0	0
T116	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	458039	0	0
T3	11546	87	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	180	0	0
T11	0	1	0	0
T25	8781	0	0	0
T34	0	7	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T61	505	0	0	0
T69	0	475	0	0
T70	0	246	0	0
T79	0	99	0	0
T108	0	214	0	0
T109	0	65	0	0
T110	0	230	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	49	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T34	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T61	505	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T79	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	5697991	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	5700427	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	125	0	0
T3	11546	3	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	2	0	0
T10	0	1	0	0
T11	0	4	0	0
T25	8781	0	0	0
T34	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	3	0	0
T59	0	1	0	0
T60	0	4	0	0
T61	505	0	0	0
T69	0	1	0	0
T70	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	73	0	0
T3	11546	3	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	1	0	0
T11	0	3	0	0
T25	8781	0	0	0
T34	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T61	505	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T79	0	1	0	0
T84	0	3	0	0
T108	0	1	0	0
T109	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	49	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T34	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T61	505	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T79	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	49	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T34	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T61	505	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T79	0	1	0	0
T108	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	457990	0	0
T3	11546	86	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	179	0	0
T25	8781	0	0	0
T34	0	6	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T61	505	0	0	0
T69	0	474	0	0
T70	0	245	0	0
T79	0	98	0	0
T108	0	213	0	0
T109	0	64	0	0
T110	0	229	0	0
T117	0	612	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	6819	0	0
T1	32514	10	0	0
T2	14635	62	0	0
T3	0	42	0	0
T4	492	8	0	0
T5	551	0	0	0
T13	422	2	0	0
T14	708	3	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	8	0	0
T18	503	7	0	0
T19	0	6	0	0
T20	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	463217	0	0
T3	11546	249	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	263	0	0
T11	0	26	0	0
T25	8781	0	0	0
T34	0	32	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T61	505	0	0	0
T69	0	134	0	0
T70	0	57	0	0
T79	0	115	0	0
T108	0	75	0	0
T109	0	225	0	0
T110	0	435	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T13,T17

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T13,T17
1	1	Covered	T4,T13,T17

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T10
1	0	Covered	T4,T13,T17
1	1	Covered	T3,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T10
0	1	Covered	T77,T82,T83
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T10
0	1	Unreachable
1	0	Covered	T3,T8,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T10
DetectSt	168	Covered	T3,T8,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T8,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T10
DebounceSt->IdleSt	163	Covered	T59,T60,T34
DetectSt->IdleSt	186	Covered	T77,T82,T83
DetectSt->StableSt	191	Covered	T3,T8,T10
IdleSt->DebounceSt	148	Covered	T3,T8,T10
StableSt->IdleSt	206	Covered	T3,T8,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T10
0	1	Covered	T3,T8,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T13,T17
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T59,T60,T34
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T77,T82,T83
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T10
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	170	0	0
CntIncr_A	8184812	372894	0	0
CntNoWrap_A	8184812	7524772	0	0
DetectStDropOut_A	8184812	10	0	0
DetectedOut_A	8184812	172082	0	0
DetectedPulseOut_A	8184812	44	0	0
DisabledIdleSt_A	8184812	5697991	0	0
DisabledNoDetection_A	8184812	5700427	0	0
EnterDebounceSt_A	8184812	117	0	0
EnterDetectSt_A	8184812	54	0	0
EnterStableSt_A	8184812	44	0	0
PulseIsPulse_A	8184812	44	0	0
StayInStableSt	8184812	172038	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_sticky_sva.StableStDropOut_A	8184812	595418	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	170	0	0
T3	11546	4	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T25	8781	0	0	0
T34	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	2	0	0
T59	0	1	0	0
T60	0	4	0	0
T61	505	0	0	0
T69	0	2	0	0
T70	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	372894	0	0
T3	11546	122	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	90	0	0
T10	0	85	0	0
T11	0	42	0	0
T25	8781	0	0	0
T34	0	54	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	19	0	0
T59	0	65	0	0
T60	0	272	0	0
T61	505	0	0	0
T69	0	14	0	0
T70	0	52	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524772	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	10	0	0
T77	6012	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T116	0	6	0	0
T118	11955	0	0	0
T119	717	0	0	0
T120	523	0	0	0
T121	421	0	0	0
T122	403	0	0	0
T123	15281	0	0	0
T124	402	0	0	0
T125	1891	0	0	0
T126	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	172082	0	0
T3	11546	316	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	156	0	0
T10	0	334	0	0
T11	0	223	0	0
T25	8781	0	0	0
T40	0	21	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	85	0	0
T61	505	0	0	0
T69	0	67	0	0
T70	0	177	0	0
T84	0	149	0	0
T108	0	263	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	44	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T40	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	1	0	0
T61	505	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T84	0	1	0	0
T108	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	5697991	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	5700427	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	117	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T34	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	1	0	0
T59	0	1	0	0
T60	0	4	0	0
T61	505	0	0	0
T69	0	1	0	0
T70	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	54	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T40	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	1	0	0
T61	505	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T84	0	1	0	0
T108	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	44	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T40	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	1	0	0
T61	505	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T84	0	1	0	0
T108	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	44	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	1	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T40	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	1	0	0
T61	505	0	0	0
T69	0	1	0	0
T70	0	1	0	0
T84	0	1	0	0
T108	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	172038	0	0
T3	11546	314	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	155	0	0
T10	0	333	0	0
T11	0	222	0	0
T25	8781	0	0	0
T40	0	20	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	84	0	0
T61	505	0	0	0
T69	0	66	0	0
T70	0	176	0	0
T84	0	148	0	0
T108	0	261	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	595418	0	0
T3	11546	118	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	208	0	0
T10	0	67	0	0
T11	0	185	0	0
T25	8781	0	0	0
T40	0	265	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	93048	0	0
T61	505	0	0	0
T69	0	600	0	0
T70	0	133	0	0
T84	0	144	0	0
T108	0	144	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T8,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T8,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T10
1	0	Covered	T4,T1,T13
1	1	Covered	T3,T8,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Covered	T34,T70,T79
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T10,T11
0	1	Unreachable
1	0	Covered	T3,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T10
DetectSt	168	Covered	T3,T10,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T10,T11
DebounceSt->IdleSt	163	Covered	T8,T57,T60
DetectSt->IdleSt	186	Covered	T34,T70,T79
DetectSt->StableSt	191	Covered	T3,T10,T11
IdleSt->DebounceSt	148	Covered	T3,T8,T10
StableSt->IdleSt	206	Covered	T3,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T8,T10
0	1	Covered	T3,T8,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T10,T11
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T57,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T10
DetectSt	-	-	-	-	1	-	-	Covered	T34,T70,T79
DetectSt	-	-	-	-	0	1	-	Covered	T3,T10,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	201	0	0
CntIncr_A	8184812	137191	0	0
CntNoWrap_A	8184812	7524741	0	0
DetectStDropOut_A	8184812	26	0	0
DetectedOut_A	8184812	193165	0	0
DetectedPulseOut_A	8184812	45	0	0
DisabledIdleSt_A	8184812	5697991	0	0
DisabledNoDetection_A	8184812	5700427	0	0
EnterDebounceSt_A	8184812	131	0	0
EnterDetectSt_A	8184812	71	0	0
EnterStableSt_A	8184812	45	0	0
PulseIsPulse_A	8184812	45	0	0
StayInStableSt	8184812	193120	0	0
gen_high_event_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_sticky_sva.StableStDropOut_A	8184812	1029347	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	201	0	0
T3	11546	4	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	2	0	0
T10	0	2	0	0
T11	0	2	0	0
T25	8781	0	0	0
T34	0	2	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	3	0	0
T59	0	2	0	0
T60	0	4	0	0
T61	505	0	0	0
T69	0	4	0	0
T70	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	137191	0	0
T3	11546	108	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	180	0	0
T10	0	54	0	0
T11	0	26	0	0
T25	8781	0	0	0
T34	0	16	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	210	0	0
T59	0	90	0	0
T60	0	396	0	0
T61	505	0	0	0
T69	0	136	0	0
T70	0	258	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524741	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	26	0	0
T34	8173	1	0	0
T68	10665	0	0	0
T70	0	3	0	0
T79	0	3	0	0
T102	462131	0	0	0
T103	2127	0	0	0
T106	13560	0	0	0
T110	0	1	0	0
T111	0	1	0	0
T113	0	1	0	0
T117	0	3	0	0
T127	0	4	0	0
T128	0	1	0	0
T129	0	2	0	0
T130	2434	0	0	0
T131	522	0	0	0
T132	57645	0	0	0
T133	2682	0	0	0
T134	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	193165	0	0
T3	11546	264	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	304	0	0
T11	0	102	0	0
T25	8781	0	0	0
T40	0	102	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T59	0	77	0	0
T61	505	0	0	0
T77	0	108	0	0
T108	0	84	0	0
T109	0	76	0	0
T110	0	68	0	0
T111	0	93	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	45	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T40	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T59	0	1	0	0
T61	505	0	0	0
T77	0	1	0	0
T108	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	5697991	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	5700427	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	131	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T7	821	0	0	0
T8	0	2	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T34	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T57	0	3	0	0
T59	0	1	0	0
T60	0	4	0	0
T61	505	0	0	0
T69	0	4	0	0
T70	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	71	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T59	0	1	0	0
T61	505	0	0	0
T70	0	3	0	0
T77	0	1	0	0
T79	0	3	0	0
T108	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	45	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T40	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T59	0	1	0	0
T61	505	0	0	0
T77	0	1	0	0
T108	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	45	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	1	0	0
T11	0	1	0	0
T25	8781	0	0	0
T40	0	1	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T59	0	1	0	0
T61	505	0	0	0
T77	0	1	0	0
T108	0	2	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	193120	0	0
T3	11546	262	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	303	0	0
T11	0	101	0	0
T25	8781	0	0	0
T40	0	101	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T59	0	76	0	0
T61	505	0	0	0
T77	0	107	0	0
T108	0	82	0	0
T109	0	75	0	0
T110	0	67	0	0
T111	0	92	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	1029347	0	0
T3	11546	213	0	0
T6	31846	0	0	0
T7	821	0	0	0
T10	0	144	0	0
T11	0	339	0	0
T25	8781	0	0	0
T40	0	153	0	0
T43	8215	0	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T59	0	65	0	0
T61	505	0	0	0
T77	0	208	0	0
T108	0	363	0	0
T109	0	212	0	0
T110	0	241	0	0
T111	0	386	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T35
1	0	Covered	T4,T5,T1
1	1	Covered	T2,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T35,T36
0	1	Covered	T135
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T35,T36
0	1	Covered	T2,T36,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T35,T36
1	-	Covered	T2,T36,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T35,T36
DetectSt	168	Covered	T2,T35,T36
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T35,T36
DebounceSt->IdleSt	163	Covered	T136,T73,T74
DetectSt->IdleSt	186	Covered	T135
DetectSt->StableSt	191	Covered	T2,T35,T36
IdleSt->DebounceSt	148	Covered	T2,T35,T36
StableSt->IdleSt	206	Covered	T2,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T35,T36
0	1	Covered	T2,T35,T36
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T35,T36
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T136
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T135
DetectSt	-	-	-	-	0	1	-	Covered	T2,T35,T36
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T36,T37
StableSt	-	-	-	-	-	-	0	Covered	T2,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	99	0	0
CntIncr_A	8184812	2261	0	0
CntNoWrap_A	8184812	7524843	0	0
DetectStDropOut_A	8184812	1	0	0
DetectedOut_A	8184812	3998	0	0
DetectedPulseOut_A	8184812	47	0	0
DisabledIdleSt_A	8184812	7507081	0	0
DisabledNoDetection_A	8184812	7509469	0	0
EnterDebounceSt_A	8184812	51	0	0
EnterDetectSt_A	8184812	48	0	0
EnterStableSt_A	8184812	47	0	0
PulseIsPulse_A	8184812	47	0	0
StayInStableSt	8184812	3927	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	99	0	0
T2	14635	6	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	2	0	0
T36	0	6	0	0
T37	0	4	0	0
T41	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T80	0	2	0	0
T136	0	3	0	0
T137	0	2	0	0
T138	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2261	0	0
T2	14635	45	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	16	0	0
T36	0	169	0	0
T37	0	138	0	0
T41	0	53	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	38	0	0
T80	0	30	0	0
T136	0	160	0	0
T137	0	25	0	0
T138	0	43	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524843	0	0
T1	32514	32087	0	0
T2	14635	2991	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	1	0	0
T135	548	1	0	0
T139	24292	0	0	0
T140	6150	0	0	0
T141	523	0	0	0
T142	426	0	0	0
T143	666	0	0	0
T144	20047	0	0	0
T145	23783	0	0	0
T146	1727	0	0	0
T147	20651	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	3998	0	0
T2	14635	236	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	69	0	0
T36	0	272	0	0
T37	0	202	0	0
T41	0	39	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	114	0	0
T136	0	57	0	0
T137	0	42	0	0
T138	0	115	0	0
T148	0	65	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	47	0	0
T2	14635	3	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T148	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7507081	0	0
T1	32514	32087	0	0
T2	14635	2541	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7509469	0	0
T1	32514	32101	0	0
T2	14635	2568	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	51	0	0
T2	14635	3	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T80	0	1	0	0
T136	0	2	0	0
T137	0	1	0	0
T138	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	48	0	0
T2	14635	3	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T148	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	47	0	0
T2	14635	3	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T148	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	47	0	0
T2	14635	3	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	1	0	0
T36	0	3	0	0
T37	0	2	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T148	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	3927	0	0
T2	14635	232	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T35	0	67	0	0
T36	0	269	0	0
T37	0	199	0	0
T41	0	37	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	113	0	0
T136	0	55	0	0
T137	0	40	0	0
T138	0	114	0	0
T148	0	62	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	23	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T36	0	3	0	0
T37	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T113	0	1	0	0
T138	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T151	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T7,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T35
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T7,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T35
0	1	Covered	T7,T82,T152
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T35
0	1	Covered	T2,T35,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T35
1	-	Covered	T2,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T35
DetectSt	168	Covered	T2,T7,T35
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T7,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T35
DebounceSt->IdleSt	163	Covered	T2,T36,T59
DetectSt->IdleSt	186	Covered	T7,T82,T152
DetectSt->StableSt	191	Covered	T2,T7,T35
IdleSt->DebounceSt	148	Covered	T2,T7,T35
StableSt->IdleSt	206	Covered	T2,T35,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T35
0	1	Covered	T2,T7,T35
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T35
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T36,T149
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T35
DetectSt	-	-	-	-	1	-	-	Covered	T7,T82,T152
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	139	0	0
CntIncr_A	8184812	60730	0	0
CntNoWrap_A	8184812	7524803	0	0
DetectStDropOut_A	8184812	4	0	0
DetectedOut_A	8184812	60354	0	0
DetectedPulseOut_A	8184812	60	0	0
DisabledIdleSt_A	8184812	7392562	0	0
DisabledNoDetection_A	8184812	7394952	0	0
EnterDebounceSt_A	8184812	77	0	0
EnterDetectSt_A	8184812	64	0	0
EnterStableSt_A	8184812	60	0	0
PulseIsPulse_A	8184812	60	0	0
StayInStableSt	8184812	60268	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8184812	2538	0	0
gen_low_level_sva.LowLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	34	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	139	0	0
T2	14635	5	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	4	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T36	0	9	0	0
T37	0	4	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T80	0	4	0	0
T102	0	2	0	0
T153	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	60730	0	0
T2	14635	51	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	162	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	48	0	0
T35	0	16	0	0
T36	0	261	0	0
T37	0	138	0	0
T43	8215	0	0	0
T51	491	0	0	0
T59	0	17	0	0
T61	505	0	0	0
T73	0	38	0	0
T80	0	60	0	0
T102	0	58	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524803	0	0
T1	32514	32087	0	0
T2	14635	2992	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	4	0	0
T7	821	1	0	0
T8	2045	0	0	0
T26	12377	0	0	0
T45	7360	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T82	0	1	0	0
T105	405	0	0	0
T152	0	1	0	0
T154	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	60354	0	0
T2	14635	56	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	126	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	57	0	0
T35	0	67	0	0
T36	0	205	0	0
T37	0	85	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	97	0	0
T102	0	43	0	0
T153	0	44	0	0
T155	0	124	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	60	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	4	0	0
T37	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	2	0	0
T102	0	1	0	0
T153	0	1	0	0
T155	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7392562	0	0
T1	32514	32087	0	0
T2	14635	2753	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7394952	0	0
T1	32514	32101	0	0
T2	14635	2781	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	77	0	0
T2	14635	3	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	2	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	5	0	0
T37	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T59	0	1	0	0
T61	505	0	0	0
T73	0	1	0	0
T80	0	2	0	0
T102	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	64	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	2	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	4	0	0
T37	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	2	0	0
T102	0	1	0	0
T153	0	1	0	0
T155	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	60	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	4	0	0
T37	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	2	0	0
T102	0	1	0	0
T153	0	1	0	0
T155	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	60	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	4	0	0
T37	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	2	0	0
T102	0	1	0	0
T153	0	1	0	0
T155	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	60268	0	0
T2	14635	53	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	124	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	54	0	0
T35	0	66	0	0
T36	0	199	0	0
T37	0	83	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	94	0	0
T102	0	41	0	0
T153	0	42	0	0
T155	0	121	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2538	0	0
T1	32514	0	0	0
T2	14635	55	0	0
T3	0	23	0	0
T4	492	4	0	0
T5	551	0	0	0
T13	422	2	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	5	0	0
T18	503	5	0	0
T19	0	4	0	0
T20	0	4	0	0
T43	0	15	0	0
T61	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	34	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T35	0	1	0	0
T36	0	2	0	0
T37	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T150	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	3	0	0