Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T9,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T7,T9,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T7,T9,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T9,T38
1	0	Covered	T4,T1,T13
1	1	Covered	T7,T9,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T38
0	1	Covered	T38,T162,T82
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T9,T38
0	1	Covered	T7,T9,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T9,T38
1	-	Covered	T7,T9,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T9,T38
DetectSt	168	Covered	T7,T9,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T7,T9,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T9,T38
DebounceSt->IdleSt	163	Covered	T39,T36,T73
DetectSt->IdleSt	186	Covered	T38,T162,T82
DetectSt->StableSt	191	Covered	T7,T9,T38
IdleSt->DebounceSt	148	Covered	T7,T9,T38
StableSt->IdleSt	206	Covered	T7,T9,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T9,T38
0	1	Covered	T7,T9,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T9,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T9,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T39,T36,T155
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T9,T38
DetectSt	-	-	-	-	1	-	-	Covered	T38,T162,T82
DetectSt	-	-	-	-	0	1	-	Covered	T7,T9,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T9,T38
StableSt	-	-	-	-	-	-	0	Covered	T7,T9,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	129	0	0
CntIncr_A	8184812	50620	0	0
CntNoWrap_A	8184812	7524813	0	0
DetectStDropOut_A	8184812	4	0	0
DetectedOut_A	8184812	109438	0	0
DetectedPulseOut_A	8184812	57	0	0
DisabledIdleSt_A	8184812	7247031	0	0
DisabledNoDetection_A	8184812	7249418	0	0
EnterDebounceSt_A	8184812	68	0	0
EnterDetectSt_A	8184812	61	0	0
EnterStableSt_A	8184812	57	0	0
PulseIsPulse_A	8184812	57	0	0
StayInStableSt	8184812	109362	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	129	0	0
T7	821	2	0	0
T8	2045	0	0	0
T9	0	2	0	0
T26	12377	0	0	0
T34	0	4	0	0
T36	0	1	0	0
T37	0	4	0	0
T38	0	4	0	0
T39	0	3	0	0
T40	0	2	0	0
T45	7360	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T73	0	1	0	0
T105	405	0	0	0
T136	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	50620	0	0
T7	821	81	0	0
T8	2045	0	0	0
T9	0	17	0	0
T26	12377	0	0	0
T34	0	48	0	0
T36	0	15	0	0
T37	0	138	0	0
T38	0	148	0	0
T39	0	36	0	0
T40	0	82	0	0
T45	7360	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T73	0	39	0	0
T105	405	0	0	0
T136	0	80	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524813	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	4	0	0
T36	3051	0	0	0
T37	976	0	0	0
T38	804	1	0	0
T39	668	0	0	0
T59	6493	0	0	0
T66	16087	0	0	0
T82	0	1	0	0
T107	40216	0	0	0
T162	0	1	0	0
T199	0	1	0	0
T209	1298	0	0	0
T210	633	0	0	0
T211	417	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	109438	0	0
T7	821	40	0	0
T8	2045	0	0	0
T9	0	40	0	0
T26	12377	0	0	0
T34	0	44	0	0
T37	0	79	0	0
T38	0	18	0	0
T39	0	164	0	0
T40	0	77	0	0
T45	7360	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T105	405	0	0	0
T136	0	230	0	0
T137	0	84	0	0
T155	0	9	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	57	0	0
T7	821	1	0	0
T8	2045	0	0	0
T9	0	1	0	0
T26	12377	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	7360	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T105	405	0	0	0
T136	0	1	0	0
T137	0	2	0	0
T155	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7247031	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7249418	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	68	0	0
T7	821	1	0	0
T8	2045	0	0	0
T9	0	1	0	0
T26	12377	0	0	0
T34	0	2	0	0
T36	0	1	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	1	0	0
T45	7360	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T73	0	1	0	0
T105	405	0	0	0
T136	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	61	0	0
T7	821	1	0	0
T8	2045	0	0	0
T9	0	1	0	0
T26	12377	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	2	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	7360	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T105	405	0	0	0
T136	0	1	0	0
T137	0	2	0	0
T155	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	57	0	0
T7	821	1	0	0
T8	2045	0	0	0
T9	0	1	0	0
T26	12377	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	7360	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T105	405	0	0	0
T136	0	1	0	0
T137	0	2	0	0
T155	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	57	0	0
T7	821	1	0	0
T8	2045	0	0	0
T9	0	1	0	0
T26	12377	0	0	0
T34	0	2	0	0
T37	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T45	7360	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T105	405	0	0	0
T136	0	1	0	0
T137	0	2	0	0
T155	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	109362	0	0
T7	821	39	0	0
T8	2045	0	0	0
T9	0	39	0	0
T26	12377	0	0	0
T34	0	42	0	0
T37	0	76	0	0
T38	0	17	0	0
T39	0	162	0	0
T40	0	76	0	0
T45	7360	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T105	405	0	0	0
T136	0	229	0	0
T137	0	81	0	0
T155	0	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	38	0	0
T7	821	1	0	0
T8	2045	0	0	0
T9	0	1	0	0
T26	12377	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T38	0	1	0	0
T40	0	1	0	0
T45	7360	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T105	405	0	0	0
T136	0	1	0	0
T137	0	1	0	0
T138	0	2	0	0
T155	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T9,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T9,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T38
1	0	Covered	T4,T1,T13
1	1	Covered	T9,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T38,T39
0	1	Covered	T212
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T38,T39
0	1	Covered	T38,T39,T37
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T38,T39
1	-	Covered	T38,T39,T37

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T38,T39
DetectSt	168	Covered	T9,T38,T39
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T9,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T38,T39
DebounceSt->IdleSt	163	Covered	T73,T156,T74
DetectSt->IdleSt	186	Covered	T212
DetectSt->StableSt	191	Covered	T9,T38,T39
IdleSt->DebounceSt	148	Covered	T9,T38,T39
StableSt->IdleSt	206	Covered	T38,T39,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T38,T39
0	1	Covered	T9,T38,T39
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T9,T38,T39
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T38,T39
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T212
DetectSt	-	-	-	-	0	1	-	Covered	T9,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T39,T37
StableSt	-	-	-	-	-	-	0	Covered	T9,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	100	0	0
CntIncr_A	8184812	51802	0	0
CntNoWrap_A	8184812	7524842	0	0
DetectStDropOut_A	8184812	1	0	0
DetectedOut_A	8184812	25995	0	0
DetectedPulseOut_A	8184812	48	0	0
DisabledIdleSt_A	8184812	7130435	0	0
DisabledNoDetection_A	8184812	7132813	0	0
EnterDebounceSt_A	8184812	52	0	0
EnterDetectSt_A	8184812	49	0	0
EnterStableSt_A	8184812	48	0	0
PulseIsPulse_A	8184812	48	0	0
StayInStableSt	8184812	25921	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8184812	6148	0	0
gen_low_level_sva.LowLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	100	0	0
T9	2598	2	0	0
T10	26028	0	0	0
T11	896	0	0	0
T12	23579	0	0	0
T34	0	4	0	0
T35	579	0	0	0
T36	0	2	0	0
T37	0	2	0	0
T38	0	4	0	0
T39	0	2	0	0
T41	0	2	0	0
T46	3972	0	0	0
T64	522	0	0	0
T73	0	1	0	0
T103	0	2	0	0
T136	0	2	0	0
T213	497	0	0	0
T214	586	0	0	0
T215	494	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	51802	0	0
T9	2598	17	0	0
T10	26028	0	0	0
T11	896	0	0	0
T12	23579	0	0	0
T34	0	48	0	0
T35	579	0	0	0
T36	0	15	0	0
T37	0	69	0	0
T38	0	148	0	0
T39	0	18	0	0
T41	0	53	0	0
T46	3972	0	0	0
T64	522	0	0	0
T73	0	37	0	0
T103	0	37	0	0
T136	0	80	0	0
T213	497	0	0	0
T214	586	0	0	0
T215	494	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524842	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	1	0	0
T212	22331	1	0	0
T216	526	0	0	0
T217	497	0	0	0
T218	503	0	0	0
T219	9136	0	0	0
T220	29004	0	0	0
T221	408	0	0	0
T222	524	0	0	0
T223	501	0	0	0
T224	20897	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	25995	0	0
T9	2598	55	0	0
T10	26028	0	0	0
T11	896	0	0	0
T12	23579	0	0	0
T34	0	80	0	0
T35	579	0	0	0
T36	0	117	0	0
T37	0	142	0	0
T38	0	78	0	0
T39	0	41	0	0
T41	0	38	0	0
T46	3972	0	0	0
T64	522	0	0	0
T80	0	262	0	0
T103	0	102	0	0
T136	0	166	0	0
T213	497	0	0	0
T214	586	0	0	0
T215	494	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	48	0	0
T9	2598	1	0	0
T10	26028	0	0	0
T11	896	0	0	0
T12	23579	0	0	0
T34	0	2	0	0
T35	579	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T46	3972	0	0	0
T64	522	0	0	0
T80	0	1	0	0
T103	0	1	0	0
T136	0	1	0	0
T213	497	0	0	0
T214	586	0	0	0
T215	494	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7130435	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7132813	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	52	0	0
T9	2598	1	0	0
T10	26028	0	0	0
T11	896	0	0	0
T12	23579	0	0	0
T34	0	2	0	0
T35	579	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T46	3972	0	0	0
T64	522	0	0	0
T73	0	1	0	0
T103	0	1	0	0
T136	0	1	0	0
T213	497	0	0	0
T214	586	0	0	0
T215	494	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	49	0	0
T9	2598	1	0	0
T10	26028	0	0	0
T11	896	0	0	0
T12	23579	0	0	0
T34	0	2	0	0
T35	579	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T46	3972	0	0	0
T64	522	0	0	0
T80	0	1	0	0
T103	0	1	0	0
T136	0	1	0	0
T213	497	0	0	0
T214	586	0	0	0
T215	494	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	48	0	0
T9	2598	1	0	0
T10	26028	0	0	0
T11	896	0	0	0
T12	23579	0	0	0
T34	0	2	0	0
T35	579	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T46	3972	0	0	0
T64	522	0	0	0
T80	0	1	0	0
T103	0	1	0	0
T136	0	1	0	0
T213	497	0	0	0
T214	586	0	0	0
T215	494	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	48	0	0
T9	2598	1	0	0
T10	26028	0	0	0
T11	896	0	0	0
T12	23579	0	0	0
T34	0	2	0	0
T35	579	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	2	0	0
T39	0	1	0	0
T41	0	1	0	0
T46	3972	0	0	0
T64	522	0	0	0
T80	0	1	0	0
T103	0	1	0	0
T136	0	1	0	0
T213	497	0	0	0
T214	586	0	0	0
T215	494	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	25921	0	0
T9	2598	53	0	0
T10	26028	0	0	0
T11	896	0	0	0
T12	23579	0	0	0
T34	0	77	0	0
T35	579	0	0	0
T36	0	115	0	0
T37	0	141	0	0
T38	0	75	0	0
T39	0	40	0	0
T41	0	36	0	0
T46	3972	0	0	0
T64	522	0	0	0
T80	0	260	0	0
T103	0	100	0	0
T136	0	164	0	0
T213	497	0	0	0
T214	586	0	0	0
T215	494	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	6148	0	0
T1	32514	11	0	0
T2	14635	56	0	0
T3	0	25	0	0
T4	492	8	0	0
T5	551	0	0	0
T13	422	2	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	8	0	0
T18	503	4	0	0
T19	0	8	0	0
T20	0	3	0	0
T43	0	14	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	22	0	0
T34	0	1	0	0
T36	3051	0	0	0
T37	976	1	0	0
T38	804	1	0	0
T39	668	1	0	0
T59	6493	0	0	0
T66	16087	0	0	0
T107	40216	0	0	0
T113	0	1	0	0
T137	0	1	0	0
T138	0	1	0	0
T155	0	1	0	0
T157	0	2	0	0
T162	0	1	0	0
T209	1298	0	0	0
T210	633	0	0	0
T211	417	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T3,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T38
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T3,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T38
0	1	Covered	T82,T174,T225
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T38
0	1	Covered	T2,T39,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T38
1	-	Covered	T2,T39,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T38
DetectSt	168	Covered	T2,T3,T38
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T3,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T38
DebounceSt->IdleSt	163	Covered	T73,T158,T149
DetectSt->IdleSt	186	Covered	T82,T174,T225
DetectSt->StableSt	191	Covered	T2,T3,T38
IdleSt->DebounceSt	148	Covered	T2,T3,T38
StableSt->IdleSt	206	Covered	T2,T3,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T38
0	1	Covered	T2,T3,T38
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T38
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T158,T149,T226
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T38
DetectSt	-	-	-	-	1	-	-	Covered	T82,T174,T225
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T39,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	117	0	0
CntIncr_A	8184812	112935	0	0
CntNoWrap_A	8184812	7524825	0	0
DetectStDropOut_A	8184812	4	0	0
DetectedOut_A	8184812	129335	0	0
DetectedPulseOut_A	8184812	52	0	0
DisabledIdleSt_A	8184812	7273523	0	0
DisabledNoDetection_A	8184812	7275911	0	0
EnterDebounceSt_A	8184812	62	0	0
EnterDetectSt_A	8184812	56	0	0
EnterStableSt_A	8184812	52	0	0
PulseIsPulse_A	8184812	52	0	0
StayInStableSt	8184812	129259	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	117	0	0
T2	14635	4	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	4	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T102	0	2	0	0
T138	0	4	0	0
T148	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	112935	0	0
T2	14635	22	0	0
T3	11546	30	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	48	0	0
T38	0	74	0	0
T39	0	18	0	0
T40	0	82	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	38	0	0
T102	0	58	0	0
T138	0	86	0	0
T148	0	100	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524825	0	0
T1	32514	32087	0	0
T2	14635	2993	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	4	0	0
T82	289757	1	0	0
T154	0	1	0	0
T174	0	1	0	0
T225	0	1	0	0
T227	502086	0	0	0
T228	649	0	0	0
T229	715	0	0	0
T230	1015	0	0	0
T231	16942	0	0	0
T232	437	0	0	0
T233	23771	0	0	0
T234	5272	0	0	0
T235	9751	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	129335	0	0
T2	14635	51	0	0
T3	11546	157	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	57	0	0
T38	0	113	0	0
T39	0	136	0	0
T40	0	166	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T102	0	43	0	0
T138	0	140	0	0
T148	0	156	0	0
T158	0	49	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	52	0	0
T2	14635	2	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T102	0	1	0	0
T138	0	2	0	0
T148	0	2	0	0
T158	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7273523	0	0
T1	32514	32087	0	0
T2	14635	2785	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7275911	0	0
T1	32514	32101	0	0
T2	14635	2813	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	62	0	0
T2	14635	2	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T102	0	1	0	0
T138	0	2	0	0
T148	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	56	0	0
T2	14635	2	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T102	0	1	0	0
T138	0	2	0	0
T148	0	2	0	0
T158	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	52	0	0
T2	14635	2	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T102	0	1	0	0
T138	0	2	0	0
T148	0	2	0	0
T158	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	52	0	0
T2	14635	2	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T102	0	1	0	0
T138	0	2	0	0
T148	0	2	0	0
T158	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	129259	0	0
T2	14635	48	0	0
T3	11546	155	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	54	0	0
T38	0	111	0	0
T39	0	135	0	0
T40	0	165	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T102	0	41	0	0
T138	0	137	0	0
T148	0	153	0	0
T158	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	28	0	0
T2	14635	1	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T138	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T150	0	1	0	0
T158	0	1	0	0
T236	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T35,T36,T37

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T35,T36,T37

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T35,T36,T37

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T38,T36
1	0	Covered	T4,T1,T13
1	1	Covered	T35,T36,T37

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T212
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Covered	T35,T37,T80
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T37
1	-	Covered	T35,T37,T80

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T36,T37
DetectSt	168	Covered	T35,T36,T37
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T35,T36,T37

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T36,T37
DebounceSt->IdleSt	163	Covered	T59,T73,T151
DetectSt->IdleSt	186	Covered	T212
DetectSt->StableSt	191	Covered	T35,T36,T37
IdleSt->DebounceSt	148	Covered	T35,T36,T37
StableSt->IdleSt	206	Covered	T35,T36,T37

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T35,T36,T37
0	1	Covered	T35,T36,T37
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T37
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T36,T37
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T36,T37
DebounceSt	-	0	1	0	-	-	-	Covered	T151
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	1	-	-	Covered	T212
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T37
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T37,T80
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T37
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	81	0	0
CntIncr_A	8184812	2433	0	0
CntNoWrap_A	8184812	7524861	0	0
DetectStDropOut_A	8184812	1	0	0
DetectedOut_A	8184812	2568	0	0
DetectedPulseOut_A	8184812	38	0	0
DisabledIdleSt_A	8184812	7130478	0	0
DisabledNoDetection_A	8184812	7132860	0	0
EnterDebounceSt_A	8184812	43	0	0
EnterDetectSt_A	8184812	39	0	0
EnterStableSt_A	8184812	38	0	0
PulseIsPulse_A	8184812	38	0	0
StayInStableSt	8184812	2510	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8184812	6042	0	0
gen_low_level_sva.LowLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	81	0	0
T32	22057	0	0	0
T35	579	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T40	0	2	0	0
T42	13810	0	0	0
T47	721	0	0	0
T48	639	0	0	0
T57	217815	0	0	0
T73	0	1	0	0
T80	0	2	0	0
T136	0	2	0	0
T148	0	2	0	0
T153	0	2	0	0
T158	0	4	0	0
T215	494	0	0	0
T237	431	0	0	0
T238	402	0	0	0
T239	965	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2433	0	0
T32	22057	0	0	0
T35	579	16	0	0
T36	0	15	0	0
T37	0	138	0	0
T40	0	82	0	0
T42	13810	0	0	0
T47	721	0	0	0
T48	639	0	0	0
T57	217815	0	0	0
T59	0	16	0	0
T73	0	38	0	0
T80	0	30	0	0
T136	0	80	0	0
T148	0	50	0	0
T153	0	53	0	0
T215	494	0	0	0
T237	431	0	0	0
T238	402	0	0	0
T239	965	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524861	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	1	0	0
T212	22331	1	0	0
T216	526	0	0	0
T217	497	0	0	0
T218	503	0	0	0
T219	9136	0	0	0
T220	29004	0	0	0
T221	408	0	0	0
T222	524	0	0	0
T223	501	0	0	0
T224	20897	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2568	0	0
T32	22057	0	0	0
T35	579	12	0	0
T36	0	39	0	0
T37	0	60	0	0
T40	0	42	0	0
T42	13810	0	0	0
T47	721	0	0	0
T48	639	0	0	0
T57	217815	0	0	0
T80	0	10	0	0
T136	0	58	0	0
T148	0	52	0	0
T149	0	155	0	0
T153	0	45	0	0
T158	0	88	0	0
T215	494	0	0	0
T237	431	0	0	0
T238	402	0	0	0
T239	965	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	38	0	0
T32	22057	0	0	0
T35	579	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	13810	0	0	0
T47	721	0	0	0
T48	639	0	0	0
T57	217815	0	0	0
T80	0	1	0	0
T136	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T153	0	1	0	0
T158	0	2	0	0
T215	494	0	0	0
T237	431	0	0	0
T238	402	0	0	0
T239	965	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7130478	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7132860	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	43	0	0
T32	22057	0	0	0
T35	579	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	13810	0	0	0
T47	721	0	0	0
T48	639	0	0	0
T57	217815	0	0	0
T59	0	1	0	0
T73	0	1	0	0
T80	0	1	0	0
T136	0	1	0	0
T148	0	1	0	0
T153	0	1	0	0
T215	494	0	0	0
T237	431	0	0	0
T238	402	0	0	0
T239	965	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	39	0	0
T32	22057	0	0	0
T35	579	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	13810	0	0	0
T47	721	0	0	0
T48	639	0	0	0
T57	217815	0	0	0
T80	0	1	0	0
T136	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T153	0	1	0	0
T158	0	2	0	0
T215	494	0	0	0
T237	431	0	0	0
T238	402	0	0	0
T239	965	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	38	0	0
T32	22057	0	0	0
T35	579	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	13810	0	0	0
T47	721	0	0	0
T48	639	0	0	0
T57	217815	0	0	0
T80	0	1	0	0
T136	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T153	0	1	0	0
T158	0	2	0	0
T215	494	0	0	0
T237	431	0	0	0
T238	402	0	0	0
T239	965	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	38	0	0
T32	22057	0	0	0
T35	579	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T40	0	1	0	0
T42	13810	0	0	0
T47	721	0	0	0
T48	639	0	0	0
T57	217815	0	0	0
T80	0	1	0	0
T136	0	1	0	0
T148	0	1	0	0
T149	0	2	0	0
T153	0	1	0	0
T158	0	2	0	0
T215	494	0	0	0
T237	431	0	0	0
T238	402	0	0	0
T239	965	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2510	0	0
T32	22057	0	0	0
T35	579	11	0	0
T36	0	37	0	0
T37	0	58	0	0
T40	0	40	0	0
T42	13810	0	0	0
T47	721	0	0	0
T48	639	0	0	0
T57	217815	0	0	0
T80	0	9	0	0
T136	0	56	0	0
T148	0	51	0	0
T149	0	152	0	0
T153	0	43	0	0
T158	0	85	0	0
T215	494	0	0	0
T237	431	0	0	0
T238	402	0	0	0
T239	965	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	6042	0	0
T1	32514	10	0	0
T2	14635	57	0	0
T3	0	28	0	0
T4	492	7	0	0
T5	551	0	0	0
T13	422	2	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	8	0	0
T18	503	6	0	0
T19	0	7	0	0
T20	0	3	0	0
T43	0	17	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	18	0	0
T32	22057	0	0	0
T35	579	1	0	0
T37	0	2	0	0
T42	13810	0	0	0
T47	721	0	0	0
T48	639	0	0	0
T57	217815	0	0	0
T80	0	1	0	0
T113	0	1	0	0
T148	0	1	0	0
T149	0	1	0	0
T151	0	1	0	0
T158	0	1	0	0
T162	0	1	0	0
T207	0	1	0	0
T215	494	0	0	0
T237	431	0	0	0
T238	402	0	0	0
T239	965	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T1,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T1,T13
1	1	Covered	T4,T1,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T7,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T7,T35

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T35
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T7,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T35
0	1	Covered	T162,T151,T152
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T7,T35
0	1	Covered	T2,T39,T36
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T7,T35
1	-	Covered	T2,T39,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T7,T35
DetectSt	168	Covered	T2,T7,T35
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T7,T35

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T7,T35
DebounceSt->IdleSt	163	Covered	T2,T73,T155
DetectSt->IdleSt	186	Covered	T162,T151,T152
DetectSt->StableSt	191	Covered	T2,T7,T35
IdleSt->DebounceSt	148	Covered	T2,T7,T35
StableSt->IdleSt	206	Covered	T2,T39,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T7,T35
0	1	Covered	T2,T7,T35
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T35
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T7,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T13
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T7,T35
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T155,T165
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T7,T35
DetectSt	-	-	-	-	1	-	-	Covered	T162,T151,T152
DetectSt	-	-	-	-	0	1	-	Covered	T2,T7,T35
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T39,T36
StableSt	-	-	-	-	-	-	0	Covered	T2,T7,T35
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	154	0	0
CntIncr_A	8184812	179345	0	0
CntNoWrap_A	8184812	7524788	0	0
DetectStDropOut_A	8184812	4	0	0
DetectedOut_A	8184812	81050	0	0
DetectedPulseOut_A	8184812	68	0	0
DisabledIdleSt_A	8184812	7093937	0	0
DisabledNoDetection_A	8184812	7096320	0	0
EnterDebounceSt_A	8184812	82	0	0
EnterDetectSt_A	8184812	72	0	0
EnterStableSt_A	8184812	68	0	0
PulseIsPulse_A	8184812	68	0	0
StayInStableSt	8184812	80952	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	38	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	154	0	0
T2	14635	9	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	2	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	4	0	0
T35	0	2	0	0
T36	0	2	0	0
T37	0	4	0	0
T39	0	4	0	0
T43	8215	0	0	0
T51	491	0	0	0
T59	0	2	0	0
T61	505	0	0	0
T102	0	2	0	0
T103	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	179345	0	0
T2	14635	73	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	81	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	48	0	0
T35	0	16	0	0
T36	0	15	0	0
T37	0	138	0	0
T39	0	36	0	0
T43	8215	0	0	0
T51	491	0	0	0
T59	0	89	0	0
T61	505	0	0	0
T102	0	58	0	0
T103	0	37	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524788	0	0
T1	32514	32087	0	0
T2	14635	2988	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	4	0	0
T97	27798	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T162	886	1	0	0
T174	0	1	0	0
T206	9040	0	0	0
T240	421	0	0	0
T241	522	0	0	0
T242	735	0	0	0
T243	16018	0	0	0
T244	5727	0	0	0
T245	522	0	0	0
T246	747	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	81050	0	0
T2	14635	147	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	44	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	79	0	0
T35	0	41	0	0
T36	0	51	0	0
T37	0	417	0	0
T39	0	63	0	0
T43	8215	0	0	0
T51	491	0	0	0
T59	0	87	0	0
T61	505	0	0	0
T102	0	50	0	0
T103	0	183	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	68	0	0
T2	14635	4	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T59	0	1	0	0
T61	505	0	0	0
T102	0	1	0	0
T103	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7093937	0	0
T1	32514	32087	0	0
T2	14635	2541	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7096320	0	0
T1	32514	32101	0	0
T2	14635	2568	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	82	0	0
T2	14635	5	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T59	0	1	0	0
T61	505	0	0	0
T102	0	1	0	0
T103	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	72	0	0
T2	14635	4	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T59	0	1	0	0
T61	505	0	0	0
T102	0	1	0	0
T103	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	68	0	0
T2	14635	4	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T59	0	1	0	0
T61	505	0	0	0
T102	0	1	0	0
T103	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	68	0	0
T2	14635	4	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T35	0	1	0	0
T36	0	1	0	0
T37	0	2	0	0
T39	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T59	0	1	0	0
T61	505	0	0	0
T102	0	1	0	0
T103	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	80952	0	0
T2	14635	141	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T7	0	42	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	76	0	0
T35	0	39	0	0
T36	0	50	0	0
T37	0	414	0	0
T39	0	60	0	0
T43	8215	0	0	0
T51	491	0	0	0
T59	0	85	0	0
T61	505	0	0	0
T102	0	48	0	0
T103	0	181	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	38	0	0
T2	14635	2	0	0
T3	11546	0	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T37	0	1	0	0
T39	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T113	0	1	0	0
T150	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0
T205	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T2,T3,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T2,T3,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T7
1	0	Covered	T4,T1,T13
1	1	Covered	T2,T3,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T34
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T34
0	1	Covered	T2,T3,T34
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T34
1	-	Covered	T2,T3,T34

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T9
DetectSt	168	Covered	T2,T3,T34
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T2,T3,T34

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T34
DebounceSt->IdleSt	163	Covered	T9,T37,T136
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T3,T34
IdleSt->DebounceSt	148	Covered	T2,T3,T9
StableSt->IdleSt	206	Covered	T2,T3,T34

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T9
0	1	Covered	T2,T3,T9
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T34
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T37,T136
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T9
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T34
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T34
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T34
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	92	0	0
CntIncr_A	8184812	30386	0	0
CntNoWrap_A	8184812	7524850	0	0
DetectStDropOut_A	8184812	0	0	0
DetectedOut_A	8184812	2898	0	0
DetectedPulseOut_A	8184812	43	0	0
DisabledIdleSt_A	8184812	7471135	0	0
DisabledNoDetection_A	8184812	7473518	0	0
EnterDebounceSt_A	8184812	50	0	0
EnterDetectSt_A	8184812	43	0	0
EnterStableSt_A	8184812	43	0	0
PulseIsPulse_A	8184812	43	0	0
StayInStableSt	8184812	2831	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8184812	6819	0	0
gen_low_level_sva.LowLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	92	0	0
T2	14635	2	0	0
T3	11546	4	0	0
T6	31846	0	0	0
T9	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	2	0	0
T37	0	1	0	0
T40	0	2	0	0
T41	0	2	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T80	0	2	0	0
T136	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	30386	0	0
T2	14635	11	0	0
T3	11546	60	0	0
T6	31846	0	0	0
T9	0	17	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	24	0	0
T37	0	69	0	0
T40	0	82	0	0
T41	0	53	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	39	0	0
T80	0	30	0	0
T136	0	160	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524850	0	0
T1	32514	32087	0	0
T2	14635	2995	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2898	0	0
T2	14635	58	0	0
T3	11546	79	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	23	0	0
T40	0	43	0	0
T41	0	143	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	157	0	0
T136	0	57	0	0
T137	0	73	0	0
T155	0	42	0	0
T159	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	43	0	0
T2	14635	1	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7471135	0	0
T1	32514	32087	0	0
T2	14635	2785	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7473518	0	0
T1	32514	32101	0	0
T2	14635	2813	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	50	0	0
T2	14635	1	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T9	0	1	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T37	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T73	0	1	0	0
T80	0	1	0	0
T136	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	43	0	0
T2	14635	1	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	43	0	0
T2	14635	1	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	43	0	0
T2	14635	1	0	0
T3	11546	2	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0
T155	0	1	0	0
T159	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2831	0	0
T2	14635	57	0	0
T3	11546	76	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	22	0	0
T40	0	41	0	0
T41	0	142	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T80	0	155	0	0
T136	0	55	0	0
T137	0	72	0	0
T155	0	40	0	0
T159	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	6819	0	0
T1	32514	10	0	0
T2	14635	62	0	0
T3	0	42	0	0
T4	492	8	0	0
T5	551	0	0	0
T13	422	2	0	0
T14	708	3	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	8	0	0
T18	503	7	0	0
T19	0	6	0	0
T20	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	19	0	0
T2	14635	1	0	0
T3	11546	1	0	0
T6	31846	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	8781	0	0	0
T34	0	1	0	0
T41	0	1	0	0
T43	8215	0	0	0
T51	491	0	0	0
T61	505	0	0	0
T82	0	1	0	0
T113	0	1	0	0
T137	0	1	0	0
T149	0	2	0	0
T150	0	1	0	0
T208	0	1	0	0