Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T26,T12
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T25,T26,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T25,T26,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T25,T26,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T12
1	0	Covered	T25,T26,T12
1	1	Covered	T25,T26,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T12
0	1	Covered	T50,T33,T85
1	0	Covered	T25,T33,T73

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T26,T12,T42
0	1	Covered	T26,T12,T42
1	0	Covered	T33,T78,T247

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T26,T12,T42
1	-	Covered	T26,T12,T42

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T26,T12
DetectSt	168	Covered	T25,T26,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T26,T12,T42

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T26,T12
DebounceSt->IdleSt	163	Covered	T73,T248,T74
DetectSt->IdleSt	186	Covered	T25,T50,T33
DetectSt->StableSt	191	Covered	T26,T12,T42
IdleSt->DebounceSt	148	Covered	T25,T26,T12
StableSt->IdleSt	206	Covered	T26,T12,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T25,T26,T12
0	1	Covered	T25,T26,T12
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T26,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T25,T26,T12
IdleSt	0	-	-	-	-	-	-	Covered	T25,T26,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T26,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T73,T248,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T26,T12
DetectSt	-	-	-	-	1	-	-	Covered	T25,T50,T33
DetectSt	-	-	-	-	0	1	-	Covered	T26,T12,T42
DetectSt	-	-	-	-	0	0	-	Covered	T25,T26,T12
StableSt	-	-	-	-	-	-	1	Covered	T26,T12,T42
StableSt	-	-	-	-	-	-	0	Covered	T26,T12,T42
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	2705	0	0
CntIncr_A	8184812	96622	0	0
CntNoWrap_A	8184812	7522237	0	0
DetectStDropOut_A	8184812	369	0	0
DetectedOut_A	8184812	72543	0	0
DetectedPulseOut_A	8184812	798	0	0
DisabledIdleSt_A	8184812	7082542	0	0
DisabledNoDetection_A	8184812	7084795	0	0
EnterDebounceSt_A	8184812	1357	0	0
EnterDetectSt_A	8184812	1348	0	0
EnterStableSt_A	8184812	798	0	0
PulseIsPulse_A	8184812	798	0	0
StayInStableSt	8184812	71651	0	0
gen_high_event_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	693	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2705	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	30	0	0
T25	8781	16	0	0
T26	12377	28	0	0
T33	0	24	0	0
T42	0	22	0	0
T44	693	0	0	0
T50	0	16	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	48	0	0
T66	0	10	0	0
T67	0	22	0	0
T68	0	14	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	96622	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	840	0	0
T25	8781	433	0	0
T26	12377	1092	0	0
T33	0	834	0	0
T42	0	484	0	0
T44	693	0	0	0
T50	0	401	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	1200	0	0
T66	0	205	0	0
T67	0	451	0	0
T68	0	238	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7522237	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	369	0	0
T33	9721	2	0	0
T38	804	0	0	0
T39	668	0	0	0
T50	5169	8	0	0
T65	14617	0	0	0
T73	0	1	0	0
T85	0	19	0	0
T86	0	5	0	0
T87	0	15	0	0
T89	0	13	0	0
T90	0	6	0	0
T92	0	3	0	0
T104	683	0	0	0
T249	0	11	0	0
T250	501	0	0	0
T251	504	0	0	0
T252	422	0	0	0
T253	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	72543	0	0
T8	2045	0	0	0
T9	2598	0	0	0
T12	0	767	0	0
T26	12377	1317	0	0
T33	0	2	0	0
T42	0	555	0	0
T45	7360	0	0	0
T46	3972	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T64	522	0	0	0
T65	0	2502	0	0
T66	0	268	0	0
T67	0	1502	0	0
T68	0	2760	0	0
T105	405	0	0	0
T106	0	551	0	0
T213	497	0	0	0
T254	0	94	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	798	0	0
T8	2045	0	0	0
T9	2598	0	0	0
T12	0	15	0	0
T26	12377	14	0	0
T33	0	2	0	0
T42	0	11	0	0
T45	7360	0	0	0
T46	3972	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T64	522	0	0	0
T65	0	24	0	0
T66	0	5	0	0
T67	0	11	0	0
T68	0	7	0	0
T105	405	0	0	0
T106	0	16	0	0
T213	497	0	0	0
T254	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7082542	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7084795	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	1357	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	15	0	0
T25	8781	8	0	0
T26	12377	14	0	0
T33	0	12	0	0
T42	0	11	0	0
T44	693	0	0	0
T50	0	8	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	24	0	0
T66	0	5	0	0
T67	0	11	0	0
T68	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	1348	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	15	0	0
T25	8781	8	0	0
T26	12377	14	0	0
T33	0	12	0	0
T42	0	11	0	0
T44	693	0	0	0
T50	0	8	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	24	0	0
T66	0	5	0	0
T67	0	11	0	0
T68	0	7	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	798	0	0
T8	2045	0	0	0
T9	2598	0	0	0
T12	0	15	0	0
T26	12377	14	0	0
T33	0	2	0	0
T42	0	11	0	0
T45	7360	0	0	0
T46	3972	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T64	522	0	0	0
T65	0	24	0	0
T66	0	5	0	0
T67	0	11	0	0
T68	0	7	0	0
T105	405	0	0	0
T106	0	16	0	0
T213	497	0	0	0
T254	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	798	0	0
T8	2045	0	0	0
T9	2598	0	0	0
T12	0	15	0	0
T26	12377	14	0	0
T33	0	2	0	0
T42	0	11	0	0
T45	7360	0	0	0
T46	3972	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T64	522	0	0	0
T65	0	24	0	0
T66	0	5	0	0
T67	0	11	0	0
T68	0	7	0	0
T105	405	0	0	0
T106	0	16	0	0
T213	497	0	0	0
T254	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	71651	0	0
T8	2045	0	0	0
T9	2598	0	0	0
T12	0	748	0	0
T26	12377	1303	0	0
T42	0	544	0	0
T45	7360	0	0	0
T46	3972	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T64	522	0	0	0
T65	0	2476	0	0
T66	0	261	0	0
T67	0	1491	0	0
T68	0	2753	0	0
T105	405	0	0	0
T106	0	534	0	0
T213	497	0	0	0
T254	0	90	0	0
T255	0	62	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	693	0	0
T8	2045	0	0	0
T9	2598	0	0	0
T12	0	11	0	0
T26	12377	14	0	0
T42	0	11	0	0
T45	7360	0	0	0
T46	3972	0	0	0
T62	495	0	0	0
T63	529	0	0	0
T64	522	0	0	0
T65	0	22	0	0
T66	0	3	0	0
T67	0	11	0	0
T68	0	7	0	0
T105	405	0	0	0
T106	0	15	0	0
T213	497	0	0	0
T254	0	4	0	0
T255	0	7	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T2,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T2,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T71,T72,T73
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T2,T3
1	-	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T2,T3
DetectSt	168	Covered	T1,T2,T3
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T2,T3
DebounceSt->IdleSt	163	Covered	T2,T3,T43
DetectSt->IdleSt	186	Covered	T71,T72,T73
DetectSt->StableSt	191	Covered	T1,T2,T3
IdleSt->DebounceSt	148	Covered	T1,T2,T3
StableSt->IdleSt	206	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T2,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T3,T43
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	1	-	-	Covered	T71,T72,T73
DetectSt	-	-	-	-	0	1	-	Covered	T1,T2,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T2,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T2,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	938	0	0
CntIncr_A	8184812	44360	0	0
CntNoWrap_A	8184812	7524004	0	0
DetectStDropOut_A	8184812	45	0	0
DetectedOut_A	8184812	18244	0	0
DetectedPulseOut_A	8184812	373	0	0
DisabledIdleSt_A	8184812	7164748	0	0
DisabledNoDetection_A	8184812	7166414	0	0
EnterDebounceSt_A	8184812	522	0	0
EnterDetectSt_A	8184812	421	0	0
EnterStableSt_A	8184812	373	0	0
PulseIsPulse_A	8184812	373	0	0
StayInStableSt	8184812	17841	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	338	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	938	0	0
T1	32514	6	0	0
T2	14635	7	0	0
T3	0	3	0	0
T6	0	23	0	0
T10	0	8	0	0
T12	0	8	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T26	0	12	0	0
T32	0	11	0	0
T42	0	4	0	0
T43	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	44360	0	0
T1	32514	291	0	0
T2	14635	110	0	0
T3	0	65	0	0
T6	0	1314	0	0
T9	0	20	0	0
T10	0	312	0	0
T12	0	196	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T26	0	366	0	0
T42	0	108	0	0
T43	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524004	0	0
T1	32514	32081	0	0
T2	14635	2990	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	45	0	0
T34	8173	0	0	0
T60	14945	0	0	0
T67	7000	0	0	0
T71	44971	1	0	0
T72	33800	2	0	0
T73	0	1	0	0
T88	0	1	0	0
T91	0	5	0	0
T93	0	2	0	0
T95	0	5	0	0
T96	0	6	0	0
T97	0	3	0	0
T98	0	2	0	0
T99	768	0	0	0
T100	402	0	0	0
T101	447	0	0	0
T102	462131	0	0	0
T103	2127	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	18244	0	0
T1	32514	172	0	0
T2	14635	7	0	0
T3	0	3	0	0
T6	0	847	0	0
T10	0	82	0	0
T12	0	200	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T26	0	615	0	0
T32	0	178	0	0
T42	0	118	0	0
T65	0	182	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	373	0	0
T1	32514	3	0	0
T2	14635	2	0	0
T3	0	1	0	0
T6	0	11	0	0
T10	0	3	0	0
T12	0	4	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T26	0	6	0	0
T32	0	5	0	0
T42	0	2	0	0
T65	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7164748	0	0
T1	32514	28204	0	0
T2	14635	2664	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7166414	0	0
T1	32514	28204	0	0
T2	14635	2688	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	522	0	0
T1	32514	3	0	0
T2	14635	5	0	0
T3	0	3	0	0
T6	0	12	0	0
T9	0	1	0	0
T10	0	5	0	0
T12	0	4	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T26	0	6	0	0
T42	0	2	0	0
T43	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	421	0	0
T1	32514	3	0	0
T2	14635	2	0	0
T3	0	1	0	0
T6	0	11	0	0
T10	0	3	0	0
T12	0	4	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T26	0	6	0	0
T32	0	5	0	0
T42	0	2	0	0
T65	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	373	0	0
T1	32514	3	0	0
T2	14635	2	0	0
T3	0	1	0	0
T6	0	11	0	0
T10	0	3	0	0
T12	0	4	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T26	0	6	0	0
T32	0	5	0	0
T42	0	2	0	0
T65	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	373	0	0
T1	32514	3	0	0
T2	14635	2	0	0
T3	0	1	0	0
T6	0	11	0	0
T10	0	3	0	0
T12	0	4	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T26	0	6	0	0
T32	0	5	0	0
T42	0	2	0	0
T65	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	17841	0	0
T1	32514	169	0	0
T2	14635	5	0	0
T3	0	2	0	0
T6	0	836	0	0
T10	0	79	0	0
T12	0	192	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T26	0	609	0	0
T32	0	173	0	0
T42	0	116	0	0
T65	0	179	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	338	0	0
T1	32514	3	0	0
T2	14635	2	0	0
T3	0	1	0	0
T6	0	11	0	0
T10	0	3	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T26	0	5	0	0
T32	0	5	0	0
T42	0	2	0	0
T65	0	3	0	0
T107	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T26,T12
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T25,T26,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T25,T26,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T25,T26,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T12
1	0	Covered	T25,T26,T12
1	1	Covered	T25,T26,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T12
0	1	Covered	T50,T33,T67
1	0	Covered	T33,T67,T73

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T12
0	1	Covered	T25,T26,T12
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T25,T26,T12
1	-	Covered	T25,T26,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T26,T12
DetectSt	168	Covered	T25,T26,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T25,T26,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T26,T12
DebounceSt->IdleSt	163	Covered	T73,T248,T74
DetectSt->IdleSt	186	Covered	T50,T33,T67
DetectSt->StableSt	191	Covered	T25,T26,T12
IdleSt->DebounceSt	148	Covered	T25,T26,T12
StableSt->IdleSt	206	Covered	T25,T26,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T25,T26,T12
0	1	Covered	T25,T26,T12
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T26,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T25,T26,T12
IdleSt	0	-	-	-	-	-	-	Covered	T25,T26,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T26,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T73,T248,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T26,T12
DetectSt	-	-	-	-	1	-	-	Covered	T50,T33,T67
DetectSt	-	-	-	-	0	1	-	Covered	T25,T26,T12
DetectSt	-	-	-	-	0	0	-	Covered	T25,T26,T12
StableSt	-	-	-	-	-	-	1	Covered	T25,T26,T12
StableSt	-	-	-	-	-	-	0	Covered	T25,T26,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	2856	0	0
CntIncr_A	8184812	92948	0	0
CntNoWrap_A	8184812	7522086	0	0
DetectStDropOut_A	8184812	444	0	0
DetectedOut_A	8184812	78197	0	0
DetectedPulseOut_A	8184812	822	0	0
DisabledIdleSt_A	8184812	7076487	0	0
DisabledNoDetection_A	8184812	7078720	0	0
EnterDebounceSt_A	8184812	1434	0	0
EnterDetectSt_A	8184812	1423	0	0
EnterStableSt_A	8184812	822	0	0
PulseIsPulse_A	8184812	822	0	0
StayInStableSt	8184812	77260	0	0
gen_high_event_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	707	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2856	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	14	0	0
T25	8781	24	0	0
T26	12377	46	0	0
T33	0	14	0	0
T42	0	40	0	0
T44	693	0	0	0
T50	0	42	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	6	0	0
T66	0	12	0	0
T67	0	16	0	0
T68	0	62	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	92948	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	364	0	0
T25	8781	384	0	0
T26	12377	1748	0	0
T33	0	485	0	0
T42	0	1400	0	0
T44	693	0	0	0
T50	0	1063	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	165	0	0
T66	0	192	0	0
T67	0	500	0	0
T68	0	992	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7522086	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	444	0	0
T33	9721	2	0	0
T38	804	0	0	0
T39	668	0	0	0
T50	5169	21	0	0
T65	14617	0	0	0
T67	0	4	0	0
T73	0	1	0	0
T85	0	22	0	0
T86	0	31	0	0
T89	0	30	0	0
T92	0	11	0	0
T104	683	0	0	0
T118	0	14	0	0
T250	501	0	0	0
T251	504	0	0	0
T252	422	0	0	0
T253	407	0	0	0
T256	0	10	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	78197	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	267	0	0
T25	8781	1724	0	0
T26	12377	534	0	0
T42	0	1604	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	78	0	0
T66	0	953	0	0
T68	0	4160	0	0
T106	0	2220	0	0
T254	0	534	0	0
T255	0	254	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	822	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	7	0	0
T25	8781	12	0	0
T26	12377	23	0	0
T42	0	20	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	3	0	0
T66	0	6	0	0
T68	0	31	0	0
T106	0	28	0	0
T254	0	26	0	0
T255	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7076487	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7078720	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	1434	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	7	0	0
T25	8781	12	0	0
T26	12377	23	0	0
T33	0	7	0	0
T42	0	20	0	0
T44	693	0	0	0
T50	0	21	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	3	0	0
T66	0	6	0	0
T67	0	8	0	0
T68	0	31	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	1423	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	7	0	0
T25	8781	12	0	0
T26	12377	23	0	0
T33	0	7	0	0
T42	0	20	0	0
T44	693	0	0	0
T50	0	21	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	3	0	0
T66	0	6	0	0
T67	0	8	0	0
T68	0	31	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	822	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	7	0	0
T25	8781	12	0	0
T26	12377	23	0	0
T42	0	20	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	3	0	0
T66	0	6	0	0
T68	0	31	0	0
T106	0	28	0	0
T254	0	26	0	0
T255	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	822	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	7	0	0
T25	8781	12	0	0
T26	12377	23	0	0
T42	0	20	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	3	0	0
T66	0	6	0	0
T68	0	31	0	0
T106	0	28	0	0
T254	0	26	0	0
T255	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	77260	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	259	0	0
T25	8781	1711	0	0
T26	12377	509	0	0
T42	0	1581	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	75	0	0
T66	0	943	0	0
T68	0	4128	0	0
T106	0	2189	0	0
T254	0	507	0	0
T255	0	244	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	707	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	6	0	0
T25	8781	11	0	0
T26	12377	21	0	0
T42	0	17	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	3	0	0
T66	0	2	0	0
T68	0	30	0	0
T106	0	25	0	0
T254	0	25	0	0
T255	0	8	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T25,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T25,T6

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T25,T6

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T25,T6

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T25,T6

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T25,T6
0	1	Covered	T72,T257,T170
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T25,T6
0	1	Covered	T1,T6,T10
1	0	Covered	T73,T76

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T25,T6
1	-	Covered	T1,T6,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T25,T6
DetectSt	168	Covered	T1,T25,T6
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T25,T6

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T25,T6
DebounceSt->IdleSt	163	Covered	T1,T25,T10
DetectSt->IdleSt	186	Covered	T72,T73,T257
DetectSt->StableSt	191	Covered	T1,T25,T6
IdleSt->DebounceSt	148	Covered	T1,T25,T6
StableSt->IdleSt	206	Covered	T1,T25,T6

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T25,T6
0	1	Covered	T1,T25,T6
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T25,T6
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T25,T6
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T25,T6
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T25,T10
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T25,T6
DetectSt	-	-	-	-	1	-	-	Covered	T72,T73,T257
DetectSt	-	-	-	-	0	1	-	Covered	T1,T25,T6
DetectSt	-	-	-	-	0	0	-	Covered	T1,T25,T6
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T25,T6
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	844	0	0
CntIncr_A	8184812	43440	0	0
CntNoWrap_A	8184812	7524098	0	0
DetectStDropOut_A	8184812	27	0	0
DetectedOut_A	8184812	16582	0	0
DetectedPulseOut_A	8184812	364	0	0
DisabledIdleSt_A	8184812	7179403	0	0
DisabledNoDetection_A	8184812	7181110	0	0
EnterDebounceSt_A	8184812	450	0	0
EnterDetectSt_A	8184812	396	0	0
EnterStableSt_A	8184812	364	0	0
PulseIsPulse_A	8184812	364	0	0
StayInStableSt	8184812	16188	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	330	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	844	0	0
T1	32514	27	0	0
T2	14635	0	0	0
T6	0	6	0	0
T10	0	6	0	0
T12	0	2	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	0	4	0	0
T26	0	4	0	0
T32	0	16	0	0
T42	0	6	0	0
T66	0	8	0	0
T107	0	26	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	43440	0	0
T1	32514	1563	0	0
T2	14635	0	0	0
T6	0	543	0	0
T10	0	385	0	0
T12	0	55	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	0	79	0	0
T26	0	190	0	0
T32	0	867	0	0
T42	0	102	0	0
T66	0	188	0	0
T107	0	1590	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524098	0	0
T1	32514	32060	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	27	0	0
T34	8173	0	0	0
T60	14945	0	0	0
T67	7000	0	0	0
T68	10665	0	0	0
T72	33800	1	0	0
T95	0	4	0	0
T96	0	1	0	0
T97	0	3	0	0
T102	462131	0	0	0
T103	2127	0	0	0
T130	2434	0	0	0
T131	522	0	0	0
T132	57645	0	0	0
T170	0	1	0	0
T257	0	2	0	0
T258	0	2	0	0
T259	0	3	0	0
T260	0	1	0	0
T261	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	16582	0	0
T1	32514	542	0	0
T2	14635	0	0	0
T6	0	21	0	0
T10	0	61	0	0
T12	0	46	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	0	85	0	0
T26	0	86	0	0
T32	0	658	0	0
T42	0	237	0	0
T66	0	205	0	0
T107	0	1137	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	364	0	0
T1	32514	12	0	0
T2	14635	0	0	0
T6	0	3	0	0
T10	0	2	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	0	1	0	0
T26	0	2	0	0
T32	0	7	0	0
T42	0	3	0	0
T66	0	4	0	0
T107	0	12	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7179403	0	0
T1	32514	28204	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7181110	0	0
T1	32514	28204	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	450	0	0
T1	32514	15	0	0
T2	14635	0	0	0
T6	0	3	0	0
T10	0	4	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	0	3	0	0
T26	0	2	0	0
T32	0	9	0	0
T42	0	3	0	0
T66	0	4	0	0
T107	0	14	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	396	0	0
T1	32514	12	0	0
T2	14635	0	0	0
T6	0	3	0	0
T10	0	2	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	0	1	0	0
T26	0	2	0	0
T32	0	7	0	0
T42	0	3	0	0
T66	0	4	0	0
T107	0	12	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	364	0	0
T1	32514	12	0	0
T2	14635	0	0	0
T6	0	3	0	0
T10	0	2	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	0	1	0	0
T26	0	2	0	0
T32	0	7	0	0
T42	0	3	0	0
T66	0	4	0	0
T107	0	12	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	364	0	0
T1	32514	12	0	0
T2	14635	0	0	0
T6	0	3	0	0
T10	0	2	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	0	1	0	0
T26	0	2	0	0
T32	0	7	0	0
T42	0	3	0	0
T66	0	4	0	0
T107	0	12	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	16188	0	0
T1	32514	530	0	0
T2	14635	0	0	0
T6	0	18	0	0
T10	0	59	0	0
T12	0	45	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T25	0	83	0	0
T26	0	82	0	0
T32	0	651	0	0
T42	0	234	0	0
T66	0	201	0	0
T107	0	1125	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	330	0	0
T1	32514	12	0	0
T2	14635	0	0	0
T6	0	3	0	0
T10	0	2	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T32	0	7	0	0
T42	0	3	0	0
T66	0	4	0	0
T71	0	1	0	0
T72	0	5	0	0
T107	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T25,T26,T12
1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T25,T26,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T25,T26,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T25,T26,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T26,T12
1	0	Covered	T25,T26,T12
1	1	Covered	T25,T26,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T12
0	1	Covered	T50,T66,T85
1	0	Covered	T66,T67,T73

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T25,T26,T12
0	1	Covered	T25,T26,T12
1	0	Covered	T74

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T25,T26,T12
1	-	Covered	T25,T26,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T26,T12
DetectSt	168	Covered	T25,T26,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T25,T26,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T25,T26,T12
DebounceSt->IdleSt	163	Covered	T73,T248,T74
DetectSt->IdleSt	186	Covered	T50,T66,T67
DetectSt->StableSt	191	Covered	T25,T26,T12
IdleSt->DebounceSt	148	Covered	T25,T26,T12
StableSt->IdleSt	206	Covered	T25,T26,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T25,T26,T12
0	1	Covered	T25,T26,T12
0	0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T25,T26,T12
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T25,T26,T12
IdleSt	0	-	-	-	-	-	-	Covered	T25,T26,T12
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T25,T26,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T73,T248,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T26,T12
DetectSt	-	-	-	-	1	-	-	Covered	T50,T66,T67
DetectSt	-	-	-	-	0	1	-	Covered	T25,T26,T12
DetectSt	-	-	-	-	0	0	-	Covered	T25,T26,T12
StableSt	-	-	-	-	-	-	1	Covered	T25,T26,T12
StableSt	-	-	-	-	-	-	0	Covered	T25,T26,T12
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	2996	0	0
CntIncr_A	8184812	101107	0	0
CntNoWrap_A	8184812	7521946	0	0
DetectStDropOut_A	8184812	394	0	0
DetectedOut_A	8184812	80891	0	0
DetectedPulseOut_A	8184812	951	0	0
DisabledIdleSt_A	8184812	7079078	0	0
DisabledNoDetection_A	8184812	7081301	0	0
EnterDebounceSt_A	8184812	1504	0	0
EnterDetectSt_A	8184812	1492	0	0
EnterStableSt_A	8184812	951	0	0
PulseIsPulse_A	8184812	951	0	0
StayInStableSt	8184812	79816	0	0
gen_high_event_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	826	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	2996	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	22	0	0
T25	8781	10	0	0
T26	12377	20	0	0
T33	0	10	0	0
T42	0	18	0	0
T44	693	0	0	0
T50	0	52	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	22	0	0
T66	0	24	0	0
T67	0	22	0	0
T68	0	8	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	101107	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	550	0	0
T25	8781	210	0	0
T26	12377	530	0	0
T33	0	330	0	0
T42	0	414	0	0
T44	693	0	0	0
T50	0	1323	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	869	0	0
T66	0	575	0	0
T67	0	690	0	0
T68	0	120	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7521946	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	394	0	0
T33	9721	0	0	0
T38	804	0	0	0
T39	668	0	0	0
T50	5169	26	0	0
T65	14617	0	0	0
T66	0	7	0	0
T73	0	1	0	0
T85	0	2	0	0
T86	0	5	0	0
T87	0	20	0	0
T89	0	30	0	0
T92	0	8	0	0
T104	683	0	0	0
T118	0	8	0	0
T250	501	0	0	0
T251	504	0	0	0
T252	422	0	0	0
T253	407	0	0	0
T262	0	28	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	80891	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	429	0	0
T25	8781	70	0	0
T26	12377	275	0	0
T33	0	27	0	0
T42	0	369	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	459	0	0
T68	0	401	0	0
T106	0	532	0	0
T254	0	2574	0	0
T255	0	1757	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	951	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	11	0	0
T25	8781	5	0	0
T26	12377	10	0	0
T33	0	5	0	0
T42	0	9	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	11	0	0
T68	0	4	0	0
T106	0	8	0	0
T254	0	25	0	0
T255	0	24	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7079078	0	0
T1	32514	32087	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7081301	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	1504	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	11	0	0
T25	8781	5	0	0
T26	12377	10	0	0
T33	0	5	0	0
T42	0	9	0	0
T44	693	0	0	0
T50	0	26	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	11	0	0
T66	0	12	0	0
T67	0	11	0	0
T68	0	4	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	1492	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	11	0	0
T25	8781	5	0	0
T26	12377	10	0	0
T33	0	5	0	0
T42	0	9	0	0
T44	693	0	0	0
T50	0	26	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	11	0	0
T66	0	12	0	0
T67	0	11	0	0
T68	0	4	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	951	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	11	0	0
T25	8781	5	0	0
T26	12377	10	0	0
T33	0	5	0	0
T42	0	9	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	11	0	0
T68	0	4	0	0
T106	0	8	0	0
T254	0	25	0	0
T255	0	24	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	951	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	11	0	0
T25	8781	5	0	0
T26	12377	10	0	0
T33	0	5	0	0
T42	0	9	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	11	0	0
T68	0	4	0	0
T106	0	8	0	0
T254	0	25	0	0
T255	0	24	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	79816	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	416	0	0
T25	8781	65	0	0
T26	12377	265	0	0
T33	0	22	0	0
T42	0	359	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	447	0	0
T68	0	396	0	0
T106	0	523	0	0
T254	0	2548	0	0
T255	0	1732	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	826	0	0
T6	31846	0	0	0
T7	821	0	0	0
T12	0	9	0	0
T25	8781	5	0	0
T26	12377	10	0	0
T33	0	5	0	0
T42	0	8	0	0
T44	693	0	0	0
T51	491	0	0	0
T52	529	0	0	0
T53	406	0	0	0
T54	524	0	0	0
T55	527	0	0	0
T65	0	10	0	0
T68	0	3	0	0
T106	0	7	0	0
T254	0	24	0	0
T255	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T25,T6
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T6
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T6,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T1,T6,T10

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T1,T6,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T32,T72,T257
1	0	Covered	T73,T74

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
1	0	Covered	T73,T75

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T6,T10
1	-	Covered	T1,T6,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T6,T10
DetectSt	168	Covered	T1,T6,T10
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T1,T6,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T6,T10
DebounceSt->IdleSt	163	Covered	T6,T10,T71
DetectSt->IdleSt	186	Covered	T32,T72,T73
DetectSt->StableSt	191	Covered	T1,T6,T10
IdleSt->DebounceSt	148	Covered	T1,T6,T10
StableSt->IdleSt	206	Covered	T1,T6,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T6,T10
0	1	Covered	T1,T6,T10
0	0	Excluded	T4,T5,T1	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T6,T10
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T6,T10
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T73,T74
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T6,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T6,T10,T71
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T6,T10
DetectSt	-	-	-	-	1	-	-	Covered	T32,T72,T73
DetectSt	-	-	-	-	0	1	-	Covered	T1,T6,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T6,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T6,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T6,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8184812	851	0	0
CntIncr_A	8184812	40873	0	0
CntNoWrap_A	8184812	7524091	0	0
DetectStDropOut_A	8184812	29	0	0
DetectedOut_A	8184812	16971	0	0
DetectedPulseOut_A	8184812	364	0	0
DisabledIdleSt_A	8184812	7160658	0	0
DisabledNoDetection_A	8184812	7162353	0	0
EnterDebounceSt_A	8184812	456	0	0
EnterDetectSt_A	8184812	396	0	0
EnterStableSt_A	8184812	364	0	0
PulseIsPulse_A	8184812	364	0	0
StayInStableSt	8184812	16556	0	0
gen_high_level_sva.HighLevelEvent_A	8184812	7527380	0	0
gen_not_sticky_sva.StableStDropOut_A	8184812	310	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	851	0	0
T1	32514	4	0	0
T2	14635	0	0	0
T6	0	5	0	0
T10	0	8	0	0
T12	0	2	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T32	0	2	0	0
T42	0	2	0	0
T65	0	2	0	0
T71	0	24	0	0
T72	0	9	0	0
T107	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	40873	0	0
T1	32514	216	0	0
T2	14635	0	0	0
T6	0	434	0	0
T10	0	469	0	0
T12	0	37	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T32	0	194	0	0
T42	0	58	0	0
T65	0	63	0	0
T71	0	1582	0	0
T72	0	372	0	0
T107	0	332	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7524091	0	0
T1	32514	32083	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	29	0	0
T32	22057	1	0	0
T33	9721	0	0	0
T49	41368	0	0	0
T50	5169	0	0	0
T58	5648	0	0	0
T72	0	1	0	0
T95	0	4	0	0
T104	683	0	0	0
T171	0	3	0	0
T204	0	1	0	0
T233	0	4	0	0
T235	0	1	0	0
T250	501	0	0	0
T251	504	0	0	0
T252	422	0	0	0
T257	0	2	0	0
T259	0	6	0	0
T263	0	2	0	0
T264	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	16971	0	0
T1	32514	91	0	0
T2	14635	0	0	0
T6	0	24	0	0
T10	0	217	0	0
T12	0	65	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T42	0	55	0	0
T60	0	45	0	0
T65	0	77	0	0
T71	0	167	0	0
T72	0	193	0	0
T107	0	88	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	364	0	0
T1	32514	2	0	0
T2	14635	0	0	0
T6	0	2	0	0
T10	0	3	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T42	0	1	0	0
T60	0	1	0	0
T65	0	1	0	0
T71	0	11	0	0
T72	0	3	0	0
T107	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7160658	0	0
T1	32514	28204	0	0
T2	14635	2997	0	0
T4	492	91	0	0
T5	551	150	0	0
T13	422	21	0	0
T14	708	307	0	0
T15	405	4	0	0
T16	1007	606	0	0
T17	495	94	0	0
T18	503	102	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7162353	0	0
T1	32514	28204	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	456	0	0
T1	32514	2	0	0
T2	14635	0	0	0
T6	0	3	0	0
T10	0	5	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T32	0	1	0	0
T42	0	1	0	0
T65	0	1	0	0
T71	0	13	0	0
T72	0	5	0	0
T107	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	396	0	0
T1	32514	2	0	0
T2	14635	0	0	0
T6	0	2	0	0
T10	0	3	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T32	0	1	0	0
T42	0	1	0	0
T65	0	1	0	0
T71	0	11	0	0
T72	0	4	0	0
T107	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	364	0	0
T1	32514	2	0	0
T2	14635	0	0	0
T6	0	2	0	0
T10	0	3	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T42	0	1	0	0
T60	0	1	0	0
T65	0	1	0	0
T71	0	11	0	0
T72	0	3	0	0
T107	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	364	0	0
T1	32514	2	0	0
T2	14635	0	0	0
T6	0	2	0	0
T10	0	3	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T42	0	1	0	0
T60	0	1	0	0
T65	0	1	0	0
T71	0	11	0	0
T72	0	3	0	0
T107	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	16556	0	0
T1	32514	89	0	0
T2	14635	0	0	0
T6	0	22	0	0
T10	0	214	0	0
T12	0	64	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T42	0	54	0	0
T60	0	44	0	0
T65	0	75	0	0
T71	0	156	0	0
T72	0	190	0	0
T107	0	86	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	7527380	0	0
T1	32514	32101	0	0
T2	14635	3026	0	0
T4	492	92	0	0
T5	551	151	0	0
T13	422	22	0	0
T14	708	308	0	0
T15	405	5	0	0
T16	1007	607	0	0
T17	495	95	0	0
T18	503	103	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8184812	310	0	0
T1	32514	2	0	0
T2	14635	0	0	0
T6	0	2	0	0
T10	0	3	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	708	0	0	0
T15	405	0	0	0
T16	1007	0	0	0
T17	495	0	0	0
T18	503	0	0	0
T19	494	0	0	0
T20	434	0	0	0
T42	0	1	0	0
T60	0	1	0	0
T71	0	11	0	0
T72	0	3	0	0
T107	0	2	0	0
T132	0	8	0	0